pwm-atmel-tcb.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) Overkiz SAS 2012
  4. *
  5. * Author: Boris BREZILLON <b.brezillon@overkiz.com>
  6. */
  7. #include <linux/module.h>
  8. #include <linux/init.h>
  9. #include <linux/clocksource.h>
  10. #include <linux/clockchips.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/irq.h>
  13. #include <linux/clk.h>
  14. #include <linux/err.h>
  15. #include <linux/ioport.h>
  16. #include <linux/io.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pwm.h>
  19. #include <linux/of_device.h>
  20. #include <linux/slab.h>
  21. #include <soc/at91/atmel_tcb.h>
  22. #define NPWM 6
  23. #define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
  24. ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
  25. #define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
  26. ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
  27. struct atmel_tcb_pwm_device {
  28. enum pwm_polarity polarity; /* PWM polarity */
  29. unsigned div; /* PWM clock divider */
  30. unsigned duty; /* PWM duty expressed in clk cycles */
  31. unsigned period; /* PWM period expressed in clk cycles */
  32. };
  33. struct atmel_tcb_channel {
  34. u32 enabled;
  35. u32 cmr;
  36. u32 ra;
  37. u32 rb;
  38. u32 rc;
  39. };
  40. struct atmel_tcb_pwm_chip {
  41. struct pwm_chip chip;
  42. spinlock_t lock;
  43. struct atmel_tc *tc;
  44. struct atmel_tcb_pwm_device *pwms[NPWM];
  45. struct atmel_tcb_channel bkup[NPWM / 2];
  46. };
  47. static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
  48. {
  49. return container_of(chip, struct atmel_tcb_pwm_chip, chip);
  50. }
  51. static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
  52. struct pwm_device *pwm,
  53. enum pwm_polarity polarity)
  54. {
  55. struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
  56. tcbpwm->polarity = polarity;
  57. return 0;
  58. }
  59. static int atmel_tcb_pwm_request(struct pwm_chip *chip,
  60. struct pwm_device *pwm)
  61. {
  62. struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
  63. struct atmel_tcb_pwm_device *tcbpwm;
  64. struct atmel_tc *tc = tcbpwmc->tc;
  65. void __iomem *regs = tc->regs;
  66. unsigned group = pwm->hwpwm / 2;
  67. unsigned index = pwm->hwpwm % 2;
  68. unsigned cmr;
  69. int ret;
  70. tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
  71. if (!tcbpwm)
  72. return -ENOMEM;
  73. ret = clk_prepare_enable(tc->clk[group]);
  74. if (ret) {
  75. devm_kfree(chip->dev, tcbpwm);
  76. return ret;
  77. }
  78. pwm_set_chip_data(pwm, tcbpwm);
  79. tcbpwm->polarity = PWM_POLARITY_NORMAL;
  80. tcbpwm->duty = 0;
  81. tcbpwm->period = 0;
  82. tcbpwm->div = 0;
  83. spin_lock(&tcbpwmc->lock);
  84. cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
  85. /*
  86. * Get init config from Timer Counter registers if
  87. * Timer Counter is already configured as a PWM generator.
  88. */
  89. if (cmr & ATMEL_TC_WAVE) {
  90. if (index == 0)
  91. tcbpwm->duty =
  92. __raw_readl(regs + ATMEL_TC_REG(group, RA));
  93. else
  94. tcbpwm->duty =
  95. __raw_readl(regs + ATMEL_TC_REG(group, RB));
  96. tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
  97. tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC));
  98. cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
  99. ATMEL_TC_BCMR_MASK);
  100. } else
  101. cmr = 0;
  102. cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
  103. __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
  104. spin_unlock(&tcbpwmc->lock);
  105. tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
  106. return 0;
  107. }
  108. static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
  109. {
  110. struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
  111. struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
  112. struct atmel_tc *tc = tcbpwmc->tc;
  113. clk_disable_unprepare(tc->clk[pwm->hwpwm / 2]);
  114. tcbpwmc->pwms[pwm->hwpwm] = NULL;
  115. devm_kfree(chip->dev, tcbpwm);
  116. }
  117. static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  118. {
  119. struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
  120. struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
  121. struct atmel_tc *tc = tcbpwmc->tc;
  122. void __iomem *regs = tc->regs;
  123. unsigned group = pwm->hwpwm / 2;
  124. unsigned index = pwm->hwpwm % 2;
  125. unsigned cmr;
  126. enum pwm_polarity polarity = tcbpwm->polarity;
  127. /*
  128. * If duty is 0 the timer will be stopped and we have to
  129. * configure the output correctly on software trigger:
  130. * - set output to high if PWM_POLARITY_INVERSED
  131. * - set output to low if PWM_POLARITY_NORMAL
  132. *
  133. * This is why we're reverting polarity in this case.
  134. */
  135. if (tcbpwm->duty == 0)
  136. polarity = !polarity;
  137. spin_lock(&tcbpwmc->lock);
  138. cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
  139. /* flush old setting and set the new one */
  140. if (index == 0) {
  141. cmr &= ~ATMEL_TC_ACMR_MASK;
  142. if (polarity == PWM_POLARITY_INVERSED)
  143. cmr |= ATMEL_TC_ASWTRG_CLEAR;
  144. else
  145. cmr |= ATMEL_TC_ASWTRG_SET;
  146. } else {
  147. cmr &= ~ATMEL_TC_BCMR_MASK;
  148. if (polarity == PWM_POLARITY_INVERSED)
  149. cmr |= ATMEL_TC_BSWTRG_CLEAR;
  150. else
  151. cmr |= ATMEL_TC_BSWTRG_SET;
  152. }
  153. __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
  154. /*
  155. * Use software trigger to apply the new setting.
  156. * If both PWM devices in this group are disabled we stop the clock.
  157. */
  158. if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
  159. __raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS,
  160. regs + ATMEL_TC_REG(group, CCR));
  161. tcbpwmc->bkup[group].enabled = 1;
  162. } else {
  163. __raw_writel(ATMEL_TC_SWTRG, regs +
  164. ATMEL_TC_REG(group, CCR));
  165. tcbpwmc->bkup[group].enabled = 0;
  166. }
  167. spin_unlock(&tcbpwmc->lock);
  168. }
  169. static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  170. {
  171. struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
  172. struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
  173. struct atmel_tc *tc = tcbpwmc->tc;
  174. void __iomem *regs = tc->regs;
  175. unsigned group = pwm->hwpwm / 2;
  176. unsigned index = pwm->hwpwm % 2;
  177. u32 cmr;
  178. enum pwm_polarity polarity = tcbpwm->polarity;
  179. /*
  180. * If duty is 0 the timer will be stopped and we have to
  181. * configure the output correctly on software trigger:
  182. * - set output to high if PWM_POLARITY_INVERSED
  183. * - set output to low if PWM_POLARITY_NORMAL
  184. *
  185. * This is why we're reverting polarity in this case.
  186. */
  187. if (tcbpwm->duty == 0)
  188. polarity = !polarity;
  189. spin_lock(&tcbpwmc->lock);
  190. cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
  191. /* flush old setting and set the new one */
  192. cmr &= ~ATMEL_TC_TCCLKS;
  193. if (index == 0) {
  194. cmr &= ~ATMEL_TC_ACMR_MASK;
  195. /* Set CMR flags according to given polarity */
  196. if (polarity == PWM_POLARITY_INVERSED)
  197. cmr |= ATMEL_TC_ASWTRG_CLEAR;
  198. else
  199. cmr |= ATMEL_TC_ASWTRG_SET;
  200. } else {
  201. cmr &= ~ATMEL_TC_BCMR_MASK;
  202. if (polarity == PWM_POLARITY_INVERSED)
  203. cmr |= ATMEL_TC_BSWTRG_CLEAR;
  204. else
  205. cmr |= ATMEL_TC_BSWTRG_SET;
  206. }
  207. /*
  208. * If duty is 0 or equal to period there's no need to register
  209. * a specific action on RA/RB and RC compare.
  210. * The output will be configured on software trigger and keep
  211. * this config till next config call.
  212. */
  213. if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
  214. if (index == 0) {
  215. if (polarity == PWM_POLARITY_INVERSED)
  216. cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
  217. else
  218. cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
  219. } else {
  220. if (polarity == PWM_POLARITY_INVERSED)
  221. cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
  222. else
  223. cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
  224. }
  225. }
  226. cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
  227. __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
  228. if (index == 0)
  229. __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA));
  230. else
  231. __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB));
  232. __raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC));
  233. /* Use software trigger to apply the new setting */
  234. __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
  235. regs + ATMEL_TC_REG(group, CCR));
  236. tcbpwmc->bkup[group].enabled = 1;
  237. spin_unlock(&tcbpwmc->lock);
  238. return 0;
  239. }
  240. static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  241. int duty_ns, int period_ns)
  242. {
  243. struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
  244. struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
  245. unsigned group = pwm->hwpwm / 2;
  246. unsigned index = pwm->hwpwm % 2;
  247. struct atmel_tcb_pwm_device *atcbpwm = NULL;
  248. struct atmel_tc *tc = tcbpwmc->tc;
  249. int i;
  250. int slowclk = 0;
  251. unsigned period;
  252. unsigned duty;
  253. unsigned rate = clk_get_rate(tc->clk[group]);
  254. unsigned long long min;
  255. unsigned long long max;
  256. /*
  257. * Find best clk divisor:
  258. * the smallest divisor which can fulfill the period_ns requirements.
  259. */
  260. for (i = 0; i < 5; ++i) {
  261. if (atmel_tc_divisors[i] == 0) {
  262. slowclk = i;
  263. continue;
  264. }
  265. min = div_u64((u64)NSEC_PER_SEC * atmel_tc_divisors[i], rate);
  266. max = min << tc->tcb_config->counter_width;
  267. if (max >= period_ns)
  268. break;
  269. }
  270. /*
  271. * If none of the divisor are small enough to represent period_ns
  272. * take slow clock (32KHz).
  273. */
  274. if (i == 5) {
  275. i = slowclk;
  276. rate = clk_get_rate(tc->slow_clk);
  277. min = div_u64(NSEC_PER_SEC, rate);
  278. max = min << tc->tcb_config->counter_width;
  279. /* If period is too big return ERANGE error */
  280. if (max < period_ns)
  281. return -ERANGE;
  282. }
  283. duty = div_u64(duty_ns, min);
  284. period = div_u64(period_ns, min);
  285. if (index == 0)
  286. atcbpwm = tcbpwmc->pwms[pwm->hwpwm + 1];
  287. else
  288. atcbpwm = tcbpwmc->pwms[pwm->hwpwm - 1];
  289. /*
  290. * PWM devices provided by TCB driver are grouped by 2:
  291. * - group 0: PWM 0 & 1
  292. * - group 1: PWM 2 & 3
  293. * - group 2: PWM 4 & 5
  294. *
  295. * PWM devices in a given group must be configured with the
  296. * same period_ns.
  297. *
  298. * We're checking the period value of the second PWM device
  299. * in this group before applying the new config.
  300. */
  301. if ((atcbpwm && atcbpwm->duty > 0 &&
  302. atcbpwm->duty != atcbpwm->period) &&
  303. (atcbpwm->div != i || atcbpwm->period != period)) {
  304. dev_err(chip->dev,
  305. "failed to configure period_ns: PWM group already configured with a different value\n");
  306. return -EINVAL;
  307. }
  308. tcbpwm->period = period;
  309. tcbpwm->div = i;
  310. tcbpwm->duty = duty;
  311. /* If the PWM is enabled, call enable to apply the new conf */
  312. if (pwm_is_enabled(pwm))
  313. atmel_tcb_pwm_enable(chip, pwm);
  314. return 0;
  315. }
  316. static const struct pwm_ops atmel_tcb_pwm_ops = {
  317. .request = atmel_tcb_pwm_request,
  318. .free = atmel_tcb_pwm_free,
  319. .config = atmel_tcb_pwm_config,
  320. .set_polarity = atmel_tcb_pwm_set_polarity,
  321. .enable = atmel_tcb_pwm_enable,
  322. .disable = atmel_tcb_pwm_disable,
  323. .owner = THIS_MODULE,
  324. };
  325. static int atmel_tcb_pwm_probe(struct platform_device *pdev)
  326. {
  327. struct atmel_tcb_pwm_chip *tcbpwm;
  328. struct device_node *np = pdev->dev.of_node;
  329. struct atmel_tc *tc;
  330. int err;
  331. int tcblock;
  332. err = of_property_read_u32(np, "tc-block", &tcblock);
  333. if (err < 0) {
  334. dev_err(&pdev->dev,
  335. "failed to get Timer Counter Block number from device tree (error: %d)\n",
  336. err);
  337. return err;
  338. }
  339. tc = atmel_tc_alloc(tcblock);
  340. if (tc == NULL) {
  341. dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n");
  342. return -ENOMEM;
  343. }
  344. tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
  345. if (tcbpwm == NULL) {
  346. err = -ENOMEM;
  347. goto err_free_tc;
  348. }
  349. tcbpwm->chip.dev = &pdev->dev;
  350. tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
  351. tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
  352. tcbpwm->chip.of_pwm_n_cells = 3;
  353. tcbpwm->chip.base = -1;
  354. tcbpwm->chip.npwm = NPWM;
  355. tcbpwm->tc = tc;
  356. err = clk_prepare_enable(tc->slow_clk);
  357. if (err)
  358. goto err_free_tc;
  359. spin_lock_init(&tcbpwm->lock);
  360. err = pwmchip_add(&tcbpwm->chip);
  361. if (err < 0)
  362. goto err_disable_clk;
  363. platform_set_drvdata(pdev, tcbpwm);
  364. return 0;
  365. err_disable_clk:
  366. clk_disable_unprepare(tcbpwm->tc->slow_clk);
  367. err_free_tc:
  368. atmel_tc_free(tc);
  369. return err;
  370. }
  371. static int atmel_tcb_pwm_remove(struct platform_device *pdev)
  372. {
  373. struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
  374. int err;
  375. clk_disable_unprepare(tcbpwm->tc->slow_clk);
  376. err = pwmchip_remove(&tcbpwm->chip);
  377. if (err < 0)
  378. return err;
  379. atmel_tc_free(tcbpwm->tc);
  380. return 0;
  381. }
  382. static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
  383. { .compatible = "atmel,tcb-pwm", },
  384. { /* sentinel */ }
  385. };
  386. MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
  387. #ifdef CONFIG_PM_SLEEP
  388. static int atmel_tcb_pwm_suspend(struct device *dev)
  389. {
  390. struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
  391. void __iomem *base = tcbpwm->tc->regs;
  392. int i;
  393. for (i = 0; i < (NPWM / 2); i++) {
  394. struct atmel_tcb_channel *chan = &tcbpwm->bkup[i];
  395. chan->cmr = readl(base + ATMEL_TC_REG(i, CMR));
  396. chan->ra = readl(base + ATMEL_TC_REG(i, RA));
  397. chan->rb = readl(base + ATMEL_TC_REG(i, RB));
  398. chan->rc = readl(base + ATMEL_TC_REG(i, RC));
  399. }
  400. return 0;
  401. }
  402. static int atmel_tcb_pwm_resume(struct device *dev)
  403. {
  404. struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
  405. void __iomem *base = tcbpwm->tc->regs;
  406. int i;
  407. for (i = 0; i < (NPWM / 2); i++) {
  408. struct atmel_tcb_channel *chan = &tcbpwm->bkup[i];
  409. writel(chan->cmr, base + ATMEL_TC_REG(i, CMR));
  410. writel(chan->ra, base + ATMEL_TC_REG(i, RA));
  411. writel(chan->rb, base + ATMEL_TC_REG(i, RB));
  412. writel(chan->rc, base + ATMEL_TC_REG(i, RC));
  413. if (chan->enabled) {
  414. writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
  415. base + ATMEL_TC_REG(i, CCR));
  416. }
  417. }
  418. return 0;
  419. }
  420. #endif
  421. static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
  422. atmel_tcb_pwm_resume);
  423. static struct platform_driver atmel_tcb_pwm_driver = {
  424. .driver = {
  425. .name = "atmel-tcb-pwm",
  426. .of_match_table = atmel_tcb_pwm_dt_ids,
  427. .pm = &atmel_tcb_pwm_pm_ops,
  428. },
  429. .probe = atmel_tcb_pwm_probe,
  430. .remove = atmel_tcb_pwm_remove,
  431. };
  432. module_platform_driver(atmel_tcb_pwm_driver);
  433. MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
  434. MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
  435. MODULE_LICENSE("GPL v2");