ptp_clockmatrix.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
  4. * synchronization devices.
  5. *
  6. * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
  7. */
  8. #include <linux/firmware.h>
  9. #include <linux/i2c.h>
  10. #include <linux/module.h>
  11. #include <linux/ptp_clock_kernel.h>
  12. #include <linux/delay.h>
  13. #include <linux/jiffies.h>
  14. #include <linux/kernel.h>
  15. #include <linux/timekeeping.h>
  16. #include <linux/string.h>
  17. #include "ptp_private.h"
  18. #include "ptp_clockmatrix.h"
  19. MODULE_DESCRIPTION("Driver for IDT ClockMatrix(TM) family");
  20. MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
  21. MODULE_AUTHOR("IDT support-1588 <IDT-support-1588@lm.renesas.com>");
  22. MODULE_VERSION("1.0");
  23. MODULE_LICENSE("GPL");
  24. /*
  25. * The name of the firmware file to be loaded
  26. * over-rides any automatic selection
  27. */
  28. static char *firmware;
  29. module_param(firmware, charp, 0);
  30. #define SETTIME_CORRECTION (0)
  31. static long set_write_phase_ready(struct ptp_clock_info *ptp)
  32. {
  33. struct idtcm_channel *channel =
  34. container_of(ptp, struct idtcm_channel, caps);
  35. channel->write_phase_ready = 1;
  36. return 0;
  37. }
  38. static int char_array_to_timespec(u8 *buf,
  39. u8 count,
  40. struct timespec64 *ts)
  41. {
  42. u8 i;
  43. u64 nsec;
  44. time64_t sec;
  45. if (count < TOD_BYTE_COUNT)
  46. return 1;
  47. /* Sub-nanoseconds are in buf[0]. */
  48. nsec = buf[4];
  49. for (i = 0; i < 3; i++) {
  50. nsec <<= 8;
  51. nsec |= buf[3 - i];
  52. }
  53. sec = buf[10];
  54. for (i = 0; i < 5; i++) {
  55. sec <<= 8;
  56. sec |= buf[9 - i];
  57. }
  58. ts->tv_sec = sec;
  59. ts->tv_nsec = nsec;
  60. return 0;
  61. }
  62. static int timespec_to_char_array(struct timespec64 const *ts,
  63. u8 *buf,
  64. u8 count)
  65. {
  66. u8 i;
  67. s32 nsec;
  68. time64_t sec;
  69. if (count < TOD_BYTE_COUNT)
  70. return 1;
  71. nsec = ts->tv_nsec;
  72. sec = ts->tv_sec;
  73. /* Sub-nanoseconds are in buf[0]. */
  74. buf[0] = 0;
  75. for (i = 1; i < 5; i++) {
  76. buf[i] = nsec & 0xff;
  77. nsec >>= 8;
  78. }
  79. for (i = 5; i < TOD_BYTE_COUNT; i++) {
  80. buf[i] = sec & 0xff;
  81. sec >>= 8;
  82. }
  83. return 0;
  84. }
  85. static int idtcm_strverscmp(const char *version1, const char *version2)
  86. {
  87. u8 ver1[3], ver2[3];
  88. int i;
  89. if (sscanf(version1, "%hhu.%hhu.%hhu",
  90. &ver1[0], &ver1[1], &ver1[2]) != 3)
  91. return -1;
  92. if (sscanf(version2, "%hhu.%hhu.%hhu",
  93. &ver2[0], &ver2[1], &ver2[2]) != 3)
  94. return -1;
  95. for (i = 0; i < 3; i++) {
  96. if (ver1[i] > ver2[i])
  97. return 1;
  98. if (ver1[i] < ver2[i])
  99. return -1;
  100. }
  101. return 0;
  102. }
  103. static int idtcm_xfer_read(struct idtcm *idtcm,
  104. u8 regaddr,
  105. u8 *buf,
  106. u16 count)
  107. {
  108. struct i2c_client *client = idtcm->client;
  109. struct i2c_msg msg[2];
  110. int cnt;
  111. char *fmt = "i2c_transfer failed at %d in %s, at addr: %04X!\n";
  112. msg[0].addr = client->addr;
  113. msg[0].flags = 0;
  114. msg[0].len = 1;
  115. msg[0].buf = &regaddr;
  116. msg[1].addr = client->addr;
  117. msg[1].flags = I2C_M_RD;
  118. msg[1].len = count;
  119. msg[1].buf = buf;
  120. cnt = i2c_transfer(client->adapter, msg, 2);
  121. if (cnt < 0) {
  122. dev_err(&client->dev,
  123. fmt,
  124. __LINE__,
  125. __func__,
  126. regaddr);
  127. return cnt;
  128. } else if (cnt != 2) {
  129. dev_err(&client->dev,
  130. "i2c_transfer sent only %d of %d messages\n", cnt, 2);
  131. return -EIO;
  132. }
  133. return 0;
  134. }
  135. static int idtcm_xfer_write(struct idtcm *idtcm,
  136. u8 regaddr,
  137. u8 *buf,
  138. u16 count)
  139. {
  140. struct i2c_client *client = idtcm->client;
  141. /* we add 1 byte for device register */
  142. u8 msg[IDTCM_MAX_WRITE_COUNT + 1];
  143. int cnt;
  144. char *fmt = "i2c_master_send failed at %d in %s, at addr: %04X!\n";
  145. if (count > IDTCM_MAX_WRITE_COUNT)
  146. return -EINVAL;
  147. msg[0] = regaddr;
  148. memcpy(&msg[1], buf, count);
  149. cnt = i2c_master_send(client, msg, count + 1);
  150. if (cnt < 0) {
  151. dev_err(&client->dev,
  152. fmt,
  153. __LINE__,
  154. __func__,
  155. regaddr);
  156. return cnt;
  157. }
  158. return 0;
  159. }
  160. static int idtcm_page_offset(struct idtcm *idtcm, u8 val)
  161. {
  162. u8 buf[4];
  163. int err;
  164. if (idtcm->page_offset == val)
  165. return 0;
  166. buf[0] = 0x0;
  167. buf[1] = val;
  168. buf[2] = 0x10;
  169. buf[3] = 0x20;
  170. err = idtcm_xfer_write(idtcm, PAGE_ADDR, buf, sizeof(buf));
  171. if (err) {
  172. idtcm->page_offset = 0xff;
  173. dev_err(&idtcm->client->dev, "failed to set page offset\n");
  174. } else {
  175. idtcm->page_offset = val;
  176. }
  177. return err;
  178. }
  179. static int _idtcm_rdwr(struct idtcm *idtcm,
  180. u16 regaddr,
  181. u8 *buf,
  182. u16 count,
  183. bool write)
  184. {
  185. u8 hi;
  186. u8 lo;
  187. int err;
  188. hi = (regaddr >> 8) & 0xff;
  189. lo = regaddr & 0xff;
  190. err = idtcm_page_offset(idtcm, hi);
  191. if (err)
  192. return err;
  193. if (write)
  194. return idtcm_xfer_write(idtcm, lo, buf, count);
  195. return idtcm_xfer_read(idtcm, lo, buf, count);
  196. }
  197. static int idtcm_read(struct idtcm *idtcm,
  198. u16 module,
  199. u16 regaddr,
  200. u8 *buf,
  201. u16 count)
  202. {
  203. return _idtcm_rdwr(idtcm, module + regaddr, buf, count, false);
  204. }
  205. static int idtcm_write(struct idtcm *idtcm,
  206. u16 module,
  207. u16 regaddr,
  208. u8 *buf,
  209. u16 count)
  210. {
  211. return _idtcm_rdwr(idtcm, module + regaddr, buf, count, true);
  212. }
  213. static int _idtcm_gettime(struct idtcm_channel *channel,
  214. struct timespec64 *ts)
  215. {
  216. struct idtcm *idtcm = channel->idtcm;
  217. u8 buf[TOD_BYTE_COUNT];
  218. u8 timeout = 10;
  219. u8 trigger;
  220. int err;
  221. err = idtcm_read(idtcm, channel->tod_read_primary,
  222. TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
  223. if (err)
  224. return err;
  225. trigger &= ~(TOD_READ_TRIGGER_MASK << TOD_READ_TRIGGER_SHIFT);
  226. trigger |= (1 << TOD_READ_TRIGGER_SHIFT);
  227. trigger &= ~TOD_READ_TRIGGER_MODE; /* single shot */
  228. err = idtcm_write(idtcm, channel->tod_read_primary,
  229. TOD_READ_PRIMARY_CMD, &trigger, sizeof(trigger));
  230. if (err)
  231. return err;
  232. /* wait trigger to be 0 */
  233. while (trigger & TOD_READ_TRIGGER_MASK) {
  234. if (idtcm->calculate_overhead_flag)
  235. idtcm->start_time = ktime_get_raw();
  236. err = idtcm_read(idtcm, channel->tod_read_primary,
  237. TOD_READ_PRIMARY_CMD, &trigger,
  238. sizeof(trigger));
  239. if (err)
  240. return err;
  241. if (--timeout == 0)
  242. return -EIO;
  243. }
  244. err = idtcm_read(idtcm, channel->tod_read_primary,
  245. TOD_READ_PRIMARY, buf, sizeof(buf));
  246. if (err)
  247. return err;
  248. err = char_array_to_timespec(buf, sizeof(buf), ts);
  249. return err;
  250. }
  251. static int _sync_pll_output(struct idtcm *idtcm,
  252. u8 pll,
  253. u8 sync_src,
  254. u8 qn,
  255. u8 qn_plus_1)
  256. {
  257. int err;
  258. u8 val;
  259. u16 sync_ctrl0;
  260. u16 sync_ctrl1;
  261. u8 temp;
  262. if ((qn == 0) && (qn_plus_1 == 0))
  263. return 0;
  264. switch (pll) {
  265. case 0:
  266. sync_ctrl0 = HW_Q0_Q1_CH_SYNC_CTRL_0;
  267. sync_ctrl1 = HW_Q0_Q1_CH_SYNC_CTRL_1;
  268. break;
  269. case 1:
  270. sync_ctrl0 = HW_Q2_Q3_CH_SYNC_CTRL_0;
  271. sync_ctrl1 = HW_Q2_Q3_CH_SYNC_CTRL_1;
  272. break;
  273. case 2:
  274. sync_ctrl0 = HW_Q4_Q5_CH_SYNC_CTRL_0;
  275. sync_ctrl1 = HW_Q4_Q5_CH_SYNC_CTRL_1;
  276. break;
  277. case 3:
  278. sync_ctrl0 = HW_Q6_Q7_CH_SYNC_CTRL_0;
  279. sync_ctrl1 = HW_Q6_Q7_CH_SYNC_CTRL_1;
  280. break;
  281. case 4:
  282. sync_ctrl0 = HW_Q8_CH_SYNC_CTRL_0;
  283. sync_ctrl1 = HW_Q8_CH_SYNC_CTRL_1;
  284. break;
  285. case 5:
  286. sync_ctrl0 = HW_Q9_CH_SYNC_CTRL_0;
  287. sync_ctrl1 = HW_Q9_CH_SYNC_CTRL_1;
  288. break;
  289. case 6:
  290. sync_ctrl0 = HW_Q10_CH_SYNC_CTRL_0;
  291. sync_ctrl1 = HW_Q10_CH_SYNC_CTRL_1;
  292. break;
  293. case 7:
  294. sync_ctrl0 = HW_Q11_CH_SYNC_CTRL_0;
  295. sync_ctrl1 = HW_Q11_CH_SYNC_CTRL_1;
  296. break;
  297. default:
  298. return -EINVAL;
  299. }
  300. val = SYNCTRL1_MASTER_SYNC_RST;
  301. /* Place master sync in reset */
  302. err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
  303. if (err)
  304. return err;
  305. err = idtcm_write(idtcm, 0, sync_ctrl0, &sync_src, sizeof(sync_src));
  306. if (err)
  307. return err;
  308. /* Set sync trigger mask */
  309. val |= SYNCTRL1_FBDIV_FRAME_SYNC_TRIG | SYNCTRL1_FBDIV_SYNC_TRIG;
  310. if (qn)
  311. val |= SYNCTRL1_Q0_DIV_SYNC_TRIG;
  312. if (qn_plus_1)
  313. val |= SYNCTRL1_Q1_DIV_SYNC_TRIG;
  314. err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
  315. if (err)
  316. return err;
  317. /* PLL5 can have OUT8 as second additional output. */
  318. if ((pll == 5) && (qn_plus_1 != 0)) {
  319. err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
  320. &temp, sizeof(temp));
  321. if (err)
  322. return err;
  323. temp &= ~(Q9_TO_Q8_SYNC_TRIG);
  324. err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
  325. &temp, sizeof(temp));
  326. if (err)
  327. return err;
  328. temp |= Q9_TO_Q8_SYNC_TRIG;
  329. err = idtcm_write(idtcm, 0, HW_Q8_CTRL_SPARE,
  330. &temp, sizeof(temp));
  331. if (err)
  332. return err;
  333. }
  334. /* PLL6 can have OUT11 as second additional output. */
  335. if ((pll == 6) && (qn_plus_1 != 0)) {
  336. err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
  337. &temp, sizeof(temp));
  338. if (err)
  339. return err;
  340. temp &= ~(Q10_TO_Q11_SYNC_TRIG);
  341. err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
  342. &temp, sizeof(temp));
  343. if (err)
  344. return err;
  345. temp |= Q10_TO_Q11_SYNC_TRIG;
  346. err = idtcm_write(idtcm, 0, HW_Q11_CTRL_SPARE,
  347. &temp, sizeof(temp));
  348. if (err)
  349. return err;
  350. }
  351. /* Place master sync out of reset */
  352. val &= ~(SYNCTRL1_MASTER_SYNC_RST);
  353. err = idtcm_write(idtcm, 0, sync_ctrl1, &val, sizeof(val));
  354. return err;
  355. }
  356. static int sync_source_dpll_tod_pps(u16 tod_addr, u8 *sync_src)
  357. {
  358. int err = 0;
  359. switch (tod_addr) {
  360. case TOD_0:
  361. *sync_src = SYNC_SOURCE_DPLL0_TOD_PPS;
  362. break;
  363. case TOD_1:
  364. *sync_src = SYNC_SOURCE_DPLL1_TOD_PPS;
  365. break;
  366. case TOD_2:
  367. *sync_src = SYNC_SOURCE_DPLL2_TOD_PPS;
  368. break;
  369. case TOD_3:
  370. *sync_src = SYNC_SOURCE_DPLL3_TOD_PPS;
  371. break;
  372. default:
  373. err = -EINVAL;
  374. }
  375. return err;
  376. }
  377. static int idtcm_sync_pps_output(struct idtcm_channel *channel)
  378. {
  379. struct idtcm *idtcm = channel->idtcm;
  380. u8 pll;
  381. u8 sync_src;
  382. u8 qn;
  383. u8 qn_plus_1;
  384. int err = 0;
  385. u8 out8_mux = 0;
  386. u8 out11_mux = 0;
  387. u8 temp;
  388. u16 output_mask = channel->output_mask;
  389. err = sync_source_dpll_tod_pps(channel->tod_n, &sync_src);
  390. if (err)
  391. return err;
  392. err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
  393. &temp, sizeof(temp));
  394. if (err)
  395. return err;
  396. if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
  397. Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
  398. out8_mux = 1;
  399. err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
  400. &temp, sizeof(temp));
  401. if (err)
  402. return err;
  403. if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
  404. Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
  405. out11_mux = 1;
  406. for (pll = 0; pll < 8; pll++) {
  407. qn = 0;
  408. qn_plus_1 = 0;
  409. if (pll < 4) {
  410. /* First 4 pll has 2 outputs */
  411. qn = output_mask & 0x1;
  412. output_mask = output_mask >> 1;
  413. qn_plus_1 = output_mask & 0x1;
  414. output_mask = output_mask >> 1;
  415. } else if (pll == 4) {
  416. if (out8_mux == 0) {
  417. qn = output_mask & 0x1;
  418. output_mask = output_mask >> 1;
  419. }
  420. } else if (pll == 5) {
  421. if (out8_mux) {
  422. qn_plus_1 = output_mask & 0x1;
  423. output_mask = output_mask >> 1;
  424. }
  425. qn = output_mask & 0x1;
  426. output_mask = output_mask >> 1;
  427. } else if (pll == 6) {
  428. qn = output_mask & 0x1;
  429. output_mask = output_mask >> 1;
  430. if (out11_mux) {
  431. qn_plus_1 = output_mask & 0x1;
  432. output_mask = output_mask >> 1;
  433. }
  434. } else if (pll == 7) {
  435. if (out11_mux == 0) {
  436. qn = output_mask & 0x1;
  437. output_mask = output_mask >> 1;
  438. }
  439. }
  440. if ((qn != 0) || (qn_plus_1 != 0))
  441. err = _sync_pll_output(idtcm, pll, sync_src, qn,
  442. qn_plus_1);
  443. if (err)
  444. return err;
  445. }
  446. return err;
  447. }
  448. static int _idtcm_set_dpll_hw_tod(struct idtcm_channel *channel,
  449. struct timespec64 const *ts,
  450. enum hw_tod_write_trig_sel wr_trig)
  451. {
  452. struct idtcm *idtcm = channel->idtcm;
  453. u8 buf[TOD_BYTE_COUNT];
  454. u8 cmd;
  455. int err;
  456. struct timespec64 local_ts = *ts;
  457. s64 total_overhead_ns;
  458. /* Configure HW TOD write trigger. */
  459. err = idtcm_read(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
  460. &cmd, sizeof(cmd));
  461. if (err)
  462. return err;
  463. cmd &= ~(0x0f);
  464. cmd |= wr_trig | 0x08;
  465. err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
  466. &cmd, sizeof(cmd));
  467. if (err)
  468. return err;
  469. if (wr_trig != HW_TOD_WR_TRIG_SEL_MSB) {
  470. err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
  471. if (err)
  472. return err;
  473. err = idtcm_write(idtcm, channel->hw_dpll_n,
  474. HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
  475. if (err)
  476. return err;
  477. }
  478. /* ARM HW TOD write trigger. */
  479. cmd &= ~(0x08);
  480. err = idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_CTRL_1,
  481. &cmd, sizeof(cmd));
  482. if (wr_trig == HW_TOD_WR_TRIG_SEL_MSB) {
  483. if (idtcm->calculate_overhead_flag) {
  484. /* Assumption: I2C @ 400KHz */
  485. total_overhead_ns = ktime_to_ns(ktime_get_raw()
  486. - idtcm->start_time)
  487. + idtcm->tod_write_overhead_ns
  488. + SETTIME_CORRECTION;
  489. timespec64_add_ns(&local_ts, total_overhead_ns);
  490. idtcm->calculate_overhead_flag = 0;
  491. }
  492. err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
  493. if (err)
  494. return err;
  495. err = idtcm_write(idtcm, channel->hw_dpll_n,
  496. HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
  497. }
  498. return err;
  499. }
  500. static int _idtcm_set_dpll_scsr_tod(struct idtcm_channel *channel,
  501. struct timespec64 const *ts,
  502. enum scsr_tod_write_trig_sel wr_trig,
  503. enum scsr_tod_write_type_sel wr_type)
  504. {
  505. struct idtcm *idtcm = channel->idtcm;
  506. unsigned char buf[TOD_BYTE_COUNT], cmd;
  507. struct timespec64 local_ts = *ts;
  508. int err, count = 0;
  509. timespec64_add_ns(&local_ts, SETTIME_CORRECTION);
  510. err = timespec_to_char_array(&local_ts, buf, sizeof(buf));
  511. if (err)
  512. return err;
  513. err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE,
  514. buf, sizeof(buf));
  515. if (err)
  516. return err;
  517. /* Trigger the write operation. */
  518. err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
  519. &cmd, sizeof(cmd));
  520. if (err)
  521. return err;
  522. cmd &= ~(TOD_WRITE_SELECTION_MASK << TOD_WRITE_SELECTION_SHIFT);
  523. cmd &= ~(TOD_WRITE_TYPE_MASK << TOD_WRITE_TYPE_SHIFT);
  524. cmd |= (wr_trig << TOD_WRITE_SELECTION_SHIFT);
  525. cmd |= (wr_type << TOD_WRITE_TYPE_SHIFT);
  526. err = idtcm_write(idtcm, channel->tod_write, TOD_WRITE_CMD,
  527. &cmd, sizeof(cmd));
  528. if (err)
  529. return err;
  530. /* Wait for the operation to complete. */
  531. while (1) {
  532. /* pps trigger takes up to 1 sec to complete */
  533. if (wr_trig == SCSR_TOD_WR_TRIG_SEL_TODPPS)
  534. msleep(50);
  535. err = idtcm_read(idtcm, channel->tod_write, TOD_WRITE_CMD,
  536. &cmd, sizeof(cmd));
  537. if (err)
  538. return err;
  539. if (cmd == 0)
  540. break;
  541. if (++count > 20) {
  542. dev_err(&idtcm->client->dev,
  543. "Timed out waiting for the write counter\n");
  544. return -EIO;
  545. }
  546. }
  547. return 0;
  548. }
  549. static int _idtcm_settime(struct idtcm_channel *channel,
  550. struct timespec64 const *ts,
  551. enum hw_tod_write_trig_sel wr_trig)
  552. {
  553. struct idtcm *idtcm = channel->idtcm;
  554. int err;
  555. int i;
  556. u8 trig_sel;
  557. err = _idtcm_set_dpll_hw_tod(channel, ts, wr_trig);
  558. if (err)
  559. return err;
  560. /* Wait for the operation to complete. */
  561. for (i = 0; i < 10000; i++) {
  562. err = idtcm_read(idtcm, channel->hw_dpll_n,
  563. HW_DPLL_TOD_CTRL_1, &trig_sel,
  564. sizeof(trig_sel));
  565. if (err)
  566. return err;
  567. if (trig_sel == 0x4a)
  568. break;
  569. err = 1;
  570. }
  571. if (err) {
  572. dev_err(&idtcm->client->dev,
  573. "Failed at line %d in func %s!\n",
  574. __LINE__,
  575. __func__);
  576. return err;
  577. }
  578. return idtcm_sync_pps_output(channel);
  579. }
  580. static int _idtcm_settime_v487(struct idtcm_channel *channel,
  581. struct timespec64 const *ts,
  582. enum scsr_tod_write_type_sel wr_type)
  583. {
  584. return _idtcm_set_dpll_scsr_tod(channel, ts,
  585. SCSR_TOD_WR_TRIG_SEL_IMMEDIATE,
  586. wr_type);
  587. }
  588. static int idtcm_set_phase_pull_in_offset(struct idtcm_channel *channel,
  589. s32 offset_ns)
  590. {
  591. int err;
  592. int i;
  593. struct idtcm *idtcm = channel->idtcm;
  594. u8 buf[4];
  595. for (i = 0; i < 4; i++) {
  596. buf[i] = 0xff & (offset_ns);
  597. offset_ns >>= 8;
  598. }
  599. err = idtcm_write(idtcm, channel->dpll_phase_pull_in, PULL_IN_OFFSET,
  600. buf, sizeof(buf));
  601. return err;
  602. }
  603. static int idtcm_set_phase_pull_in_slope_limit(struct idtcm_channel *channel,
  604. u32 max_ffo_ppb)
  605. {
  606. int err;
  607. u8 i;
  608. struct idtcm *idtcm = channel->idtcm;
  609. u8 buf[3];
  610. if (max_ffo_ppb & 0xff000000)
  611. max_ffo_ppb = 0;
  612. for (i = 0; i < 3; i++) {
  613. buf[i] = 0xff & (max_ffo_ppb);
  614. max_ffo_ppb >>= 8;
  615. }
  616. err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
  617. PULL_IN_SLOPE_LIMIT, buf, sizeof(buf));
  618. return err;
  619. }
  620. static int idtcm_start_phase_pull_in(struct idtcm_channel *channel)
  621. {
  622. int err;
  623. struct idtcm *idtcm = channel->idtcm;
  624. u8 buf;
  625. err = idtcm_read(idtcm, channel->dpll_phase_pull_in, PULL_IN_CTRL,
  626. &buf, sizeof(buf));
  627. if (err)
  628. return err;
  629. if (buf == 0) {
  630. buf = 0x01;
  631. err = idtcm_write(idtcm, channel->dpll_phase_pull_in,
  632. PULL_IN_CTRL, &buf, sizeof(buf));
  633. } else {
  634. err = -EBUSY;
  635. }
  636. return err;
  637. }
  638. static int idtcm_do_phase_pull_in(struct idtcm_channel *channel,
  639. s32 offset_ns,
  640. u32 max_ffo_ppb)
  641. {
  642. int err;
  643. err = idtcm_set_phase_pull_in_offset(channel, -offset_ns);
  644. if (err)
  645. return err;
  646. err = idtcm_set_phase_pull_in_slope_limit(channel, max_ffo_ppb);
  647. if (err)
  648. return err;
  649. err = idtcm_start_phase_pull_in(channel);
  650. return err;
  651. }
  652. static int set_tod_write_overhead(struct idtcm_channel *channel)
  653. {
  654. struct idtcm *idtcm = channel->idtcm;
  655. s64 current_ns = 0;
  656. s64 lowest_ns = 0;
  657. int err;
  658. u8 i;
  659. ktime_t start;
  660. ktime_t stop;
  661. char buf[TOD_BYTE_COUNT] = {0};
  662. /* Set page offset */
  663. idtcm_write(idtcm, channel->hw_dpll_n, HW_DPLL_TOD_OVR__0,
  664. buf, sizeof(buf));
  665. for (i = 0; i < TOD_WRITE_OVERHEAD_COUNT_MAX; i++) {
  666. start = ktime_get_raw();
  667. err = idtcm_write(idtcm, channel->hw_dpll_n,
  668. HW_DPLL_TOD_OVR__0, buf, sizeof(buf));
  669. if (err)
  670. return err;
  671. stop = ktime_get_raw();
  672. current_ns = ktime_to_ns(stop - start);
  673. if (i == 0) {
  674. lowest_ns = current_ns;
  675. } else {
  676. if (current_ns < lowest_ns)
  677. lowest_ns = current_ns;
  678. }
  679. }
  680. idtcm->tod_write_overhead_ns = lowest_ns;
  681. return err;
  682. }
  683. static int _idtcm_adjtime(struct idtcm_channel *channel, s64 delta)
  684. {
  685. int err;
  686. struct idtcm *idtcm = channel->idtcm;
  687. struct timespec64 ts;
  688. s64 now;
  689. if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS) {
  690. err = idtcm_do_phase_pull_in(channel, delta, 0);
  691. } else {
  692. idtcm->calculate_overhead_flag = 1;
  693. err = set_tod_write_overhead(channel);
  694. if (err)
  695. return err;
  696. err = _idtcm_gettime(channel, &ts);
  697. if (err)
  698. return err;
  699. now = timespec64_to_ns(&ts);
  700. now += delta;
  701. ts = ns_to_timespec64(now);
  702. err = _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
  703. }
  704. return err;
  705. }
  706. static int idtcm_state_machine_reset(struct idtcm *idtcm)
  707. {
  708. int err;
  709. u8 byte = SM_RESET_CMD;
  710. err = idtcm_write(idtcm, RESET_CTRL, SM_RESET, &byte, sizeof(byte));
  711. if (!err)
  712. msleep_interruptible(POST_SM_RESET_DELAY_MS);
  713. return err;
  714. }
  715. static int idtcm_read_hw_rev_id(struct idtcm *idtcm, u8 *hw_rev_id)
  716. {
  717. return idtcm_read(idtcm, HW_REVISION, REV_ID, hw_rev_id, sizeof(u8));
  718. }
  719. static int idtcm_read_product_id(struct idtcm *idtcm, u16 *product_id)
  720. {
  721. int err;
  722. u8 buf[2] = {0};
  723. err = idtcm_read(idtcm, GENERAL_STATUS, PRODUCT_ID, buf, sizeof(buf));
  724. *product_id = (buf[1] << 8) | buf[0];
  725. return err;
  726. }
  727. static int idtcm_read_major_release(struct idtcm *idtcm, u8 *major)
  728. {
  729. int err;
  730. u8 buf = 0;
  731. err = idtcm_read(idtcm, GENERAL_STATUS, MAJ_REL, &buf, sizeof(buf));
  732. *major = buf >> 1;
  733. return err;
  734. }
  735. static int idtcm_read_minor_release(struct idtcm *idtcm, u8 *minor)
  736. {
  737. return idtcm_read(idtcm, GENERAL_STATUS, MIN_REL, minor, sizeof(u8));
  738. }
  739. static int idtcm_read_hotfix_release(struct idtcm *idtcm, u8 *hotfix)
  740. {
  741. return idtcm_read(idtcm,
  742. GENERAL_STATUS,
  743. HOTFIX_REL,
  744. hotfix,
  745. sizeof(u8));
  746. }
  747. static int idtcm_read_otp_scsr_config_select(struct idtcm *idtcm,
  748. u8 *config_select)
  749. {
  750. return idtcm_read(idtcm, GENERAL_STATUS, OTP_SCSR_CONFIG_SELECT,
  751. config_select, sizeof(u8));
  752. }
  753. static int set_pll_output_mask(struct idtcm *idtcm, u16 addr, u8 val)
  754. {
  755. int err = 0;
  756. switch (addr) {
  757. case TOD0_OUT_ALIGN_MASK_ADDR:
  758. SET_U16_LSB(idtcm->channel[0].output_mask, val);
  759. break;
  760. case TOD0_OUT_ALIGN_MASK_ADDR + 1:
  761. SET_U16_MSB(idtcm->channel[0].output_mask, val);
  762. break;
  763. case TOD1_OUT_ALIGN_MASK_ADDR:
  764. SET_U16_LSB(idtcm->channel[1].output_mask, val);
  765. break;
  766. case TOD1_OUT_ALIGN_MASK_ADDR + 1:
  767. SET_U16_MSB(idtcm->channel[1].output_mask, val);
  768. break;
  769. case TOD2_OUT_ALIGN_MASK_ADDR:
  770. SET_U16_LSB(idtcm->channel[2].output_mask, val);
  771. break;
  772. case TOD2_OUT_ALIGN_MASK_ADDR + 1:
  773. SET_U16_MSB(idtcm->channel[2].output_mask, val);
  774. break;
  775. case TOD3_OUT_ALIGN_MASK_ADDR:
  776. SET_U16_LSB(idtcm->channel[3].output_mask, val);
  777. break;
  778. case TOD3_OUT_ALIGN_MASK_ADDR + 1:
  779. SET_U16_MSB(idtcm->channel[3].output_mask, val);
  780. break;
  781. default:
  782. err = -EFAULT; /* Bad address */;
  783. break;
  784. }
  785. return err;
  786. }
  787. static int set_tod_ptp_pll(struct idtcm *idtcm, u8 index, u8 pll)
  788. {
  789. if (index >= MAX_TOD) {
  790. dev_err(&idtcm->client->dev, "ToD%d not supported\n", index);
  791. return -EINVAL;
  792. }
  793. if (pll >= MAX_PLL) {
  794. dev_err(&idtcm->client->dev, "Pll%d not supported\n", pll);
  795. return -EINVAL;
  796. }
  797. idtcm->channel[index].pll = pll;
  798. return 0;
  799. }
  800. static int check_and_set_masks(struct idtcm *idtcm,
  801. u16 regaddr,
  802. u8 val)
  803. {
  804. int err = 0;
  805. switch (regaddr) {
  806. case TOD_MASK_ADDR:
  807. if ((val & 0xf0) || !(val & 0x0f)) {
  808. dev_err(&idtcm->client->dev,
  809. "Invalid TOD mask 0x%hhx\n", val);
  810. err = -EINVAL;
  811. } else {
  812. idtcm->tod_mask = val;
  813. }
  814. break;
  815. case TOD0_PTP_PLL_ADDR:
  816. err = set_tod_ptp_pll(idtcm, 0, val);
  817. break;
  818. case TOD1_PTP_PLL_ADDR:
  819. err = set_tod_ptp_pll(idtcm, 1, val);
  820. break;
  821. case TOD2_PTP_PLL_ADDR:
  822. err = set_tod_ptp_pll(idtcm, 2, val);
  823. break;
  824. case TOD3_PTP_PLL_ADDR:
  825. err = set_tod_ptp_pll(idtcm, 3, val);
  826. break;
  827. default:
  828. err = set_pll_output_mask(idtcm, regaddr, val);
  829. break;
  830. }
  831. return err;
  832. }
  833. static void display_pll_and_masks(struct idtcm *idtcm)
  834. {
  835. u8 i;
  836. u8 mask;
  837. dev_dbg(&idtcm->client->dev, "tod_mask = 0x%02x\n", idtcm->tod_mask);
  838. for (i = 0; i < MAX_TOD; i++) {
  839. mask = 1 << i;
  840. if (mask & idtcm->tod_mask)
  841. dev_dbg(&idtcm->client->dev,
  842. "TOD%d pll = %d output_mask = 0x%04x\n",
  843. i, idtcm->channel[i].pll,
  844. idtcm->channel[i].output_mask);
  845. }
  846. }
  847. static int idtcm_load_firmware(struct idtcm *idtcm,
  848. struct device *dev)
  849. {
  850. char fname[128] = FW_FILENAME;
  851. const struct firmware *fw;
  852. struct idtcm_fwrc *rec;
  853. u32 regaddr;
  854. int err;
  855. s32 len;
  856. u8 val;
  857. u8 loaddr;
  858. if (firmware) /* module parameter */
  859. snprintf(fname, sizeof(fname), "%s", firmware);
  860. dev_dbg(&idtcm->client->dev, "requesting firmware '%s'\n", fname);
  861. err = request_firmware(&fw, fname, dev);
  862. if (err) {
  863. dev_err(&idtcm->client->dev,
  864. "Failed at line %d in func %s!\n",
  865. __LINE__,
  866. __func__);
  867. return err;
  868. }
  869. dev_dbg(&idtcm->client->dev, "firmware size %zu bytes\n", fw->size);
  870. rec = (struct idtcm_fwrc *) fw->data;
  871. if (fw->size > 0)
  872. idtcm_state_machine_reset(idtcm);
  873. for (len = fw->size; len > 0; len -= sizeof(*rec)) {
  874. if (rec->reserved) {
  875. dev_err(&idtcm->client->dev,
  876. "bad firmware, reserved field non-zero\n");
  877. err = -EINVAL;
  878. } else {
  879. regaddr = rec->hiaddr << 8;
  880. regaddr |= rec->loaddr;
  881. val = rec->value;
  882. loaddr = rec->loaddr;
  883. rec++;
  884. err = check_and_set_masks(idtcm, regaddr, val);
  885. }
  886. if (err != -EINVAL) {
  887. err = 0;
  888. /* Top (status registers) and bottom are read-only */
  889. if ((regaddr < GPIO_USER_CONTROL)
  890. || (regaddr >= SCRATCH))
  891. continue;
  892. /* Page size 128, last 4 bytes of page skipped */
  893. if (((loaddr > 0x7b) && (loaddr <= 0x7f))
  894. || loaddr > 0xfb)
  895. continue;
  896. err = idtcm_write(idtcm, regaddr, 0, &val, sizeof(val));
  897. }
  898. if (err)
  899. goto out;
  900. }
  901. display_pll_and_masks(idtcm);
  902. out:
  903. release_firmware(fw);
  904. return err;
  905. }
  906. static int idtcm_output_enable(struct idtcm_channel *channel,
  907. bool enable, unsigned int outn)
  908. {
  909. struct idtcm *idtcm = channel->idtcm;
  910. int err;
  911. u8 val;
  912. err = idtcm_read(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
  913. OUT_CTRL_1, &val, sizeof(val));
  914. if (err)
  915. return err;
  916. if (enable)
  917. val |= SQUELCH_DISABLE;
  918. else
  919. val &= ~SQUELCH_DISABLE;
  920. return idtcm_write(idtcm, OUTPUT_MODULE_FROM_INDEX(outn),
  921. OUT_CTRL_1, &val, sizeof(val));
  922. }
  923. static int idtcm_output_mask_enable(struct idtcm_channel *channel,
  924. bool enable)
  925. {
  926. u16 mask;
  927. int err;
  928. u8 outn;
  929. mask = channel->output_mask;
  930. outn = 0;
  931. while (mask) {
  932. if (mask & 0x1) {
  933. err = idtcm_output_enable(channel, enable, outn);
  934. if (err)
  935. return err;
  936. }
  937. mask >>= 0x1;
  938. outn++;
  939. }
  940. return 0;
  941. }
  942. static int idtcm_perout_enable(struct idtcm_channel *channel,
  943. bool enable,
  944. struct ptp_perout_request *perout)
  945. {
  946. unsigned int flags = perout->flags;
  947. if (flags == PEROUT_ENABLE_OUTPUT_MASK)
  948. return idtcm_output_mask_enable(channel, enable);
  949. /* Enable/disable individual output instead */
  950. return idtcm_output_enable(channel, enable, perout->index);
  951. }
  952. static int idtcm_set_pll_mode(struct idtcm_channel *channel,
  953. enum pll_mode pll_mode)
  954. {
  955. struct idtcm *idtcm = channel->idtcm;
  956. int err;
  957. u8 dpll_mode;
  958. err = idtcm_read(idtcm, channel->dpll_n, DPLL_MODE,
  959. &dpll_mode, sizeof(dpll_mode));
  960. if (err)
  961. return err;
  962. dpll_mode &= ~(PLL_MODE_MASK << PLL_MODE_SHIFT);
  963. dpll_mode |= (pll_mode << PLL_MODE_SHIFT);
  964. channel->pll_mode = pll_mode;
  965. err = idtcm_write(idtcm, channel->dpll_n, DPLL_MODE,
  966. &dpll_mode, sizeof(dpll_mode));
  967. if (err)
  968. return err;
  969. return 0;
  970. }
  971. /* PTP Hardware Clock interface */
  972. /**
  973. * @brief Maximum absolute value for write phase offset in picoseconds
  974. *
  975. * Destination signed register is 32-bit register in resolution of 50ps
  976. *
  977. * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
  978. */
  979. static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
  980. {
  981. struct idtcm *idtcm = channel->idtcm;
  982. int err;
  983. u8 i;
  984. u8 buf[4] = {0};
  985. s32 phase_50ps;
  986. s64 offset_ps;
  987. if (channel->pll_mode != PLL_MODE_WRITE_PHASE) {
  988. err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_PHASE);
  989. if (err)
  990. return err;
  991. channel->write_phase_ready = 0;
  992. ptp_schedule_worker(channel->ptp_clock,
  993. msecs_to_jiffies(WR_PHASE_SETUP_MS));
  994. }
  995. if (!channel->write_phase_ready)
  996. delta_ns = 0;
  997. offset_ps = (s64)delta_ns * 1000;
  998. /*
  999. * Check for 32-bit signed max * 50:
  1000. *
  1001. * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350
  1002. */
  1003. if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
  1004. offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
  1005. else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
  1006. offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
  1007. phase_50ps = DIV_ROUND_CLOSEST(div64_s64(offset_ps, 50), 1);
  1008. for (i = 0; i < 4; i++) {
  1009. buf[i] = phase_50ps & 0xff;
  1010. phase_50ps >>= 8;
  1011. }
  1012. err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
  1013. buf, sizeof(buf));
  1014. return err;
  1015. }
  1016. static int _idtcm_adjfine(struct idtcm_channel *channel, long scaled_ppm)
  1017. {
  1018. struct idtcm *idtcm = channel->idtcm;
  1019. u8 i;
  1020. bool neg_adj = 0;
  1021. int err;
  1022. u8 buf[6] = {0};
  1023. s64 fcw;
  1024. if (channel->pll_mode != PLL_MODE_WRITE_FREQUENCY) {
  1025. err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
  1026. if (err)
  1027. return err;
  1028. }
  1029. /*
  1030. * Frequency Control Word unit is: 1.11 * 10^-10 ppm
  1031. *
  1032. * adjfreq:
  1033. * ppb * 10^9
  1034. * FCW = ----------
  1035. * 111
  1036. *
  1037. * adjfine:
  1038. * ppm_16 * 5^12
  1039. * FCW = -------------
  1040. * 111 * 2^4
  1041. */
  1042. if (scaled_ppm < 0) {
  1043. neg_adj = 1;
  1044. scaled_ppm = -scaled_ppm;
  1045. }
  1046. /* 2 ^ -53 = 1.1102230246251565404236316680908e-16 */
  1047. fcw = scaled_ppm * 244140625ULL;
  1048. fcw = div_u64(fcw, 1776);
  1049. if (neg_adj)
  1050. fcw = -fcw;
  1051. for (i = 0; i < 6; i++) {
  1052. buf[i] = fcw & 0xff;
  1053. fcw >>= 8;
  1054. }
  1055. err = idtcm_write(idtcm, channel->dpll_freq, DPLL_WR_FREQ,
  1056. buf, sizeof(buf));
  1057. return err;
  1058. }
  1059. static int idtcm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
  1060. {
  1061. struct idtcm_channel *channel =
  1062. container_of(ptp, struct idtcm_channel, caps);
  1063. struct idtcm *idtcm = channel->idtcm;
  1064. int err;
  1065. mutex_lock(&idtcm->reg_lock);
  1066. err = _idtcm_gettime(channel, ts);
  1067. if (err)
  1068. dev_err(&idtcm->client->dev,
  1069. "Failed at line %d in func %s!\n",
  1070. __LINE__,
  1071. __func__);
  1072. mutex_unlock(&idtcm->reg_lock);
  1073. return err;
  1074. }
  1075. static int idtcm_settime(struct ptp_clock_info *ptp,
  1076. const struct timespec64 *ts)
  1077. {
  1078. struct idtcm_channel *channel =
  1079. container_of(ptp, struct idtcm_channel, caps);
  1080. struct idtcm *idtcm = channel->idtcm;
  1081. int err;
  1082. mutex_lock(&idtcm->reg_lock);
  1083. err = _idtcm_settime(channel, ts, HW_TOD_WR_TRIG_SEL_MSB);
  1084. if (err)
  1085. dev_err(&idtcm->client->dev,
  1086. "Failed at line %d in func %s!\n",
  1087. __LINE__,
  1088. __func__);
  1089. mutex_unlock(&idtcm->reg_lock);
  1090. return err;
  1091. }
  1092. static int idtcm_settime_v487(struct ptp_clock_info *ptp,
  1093. const struct timespec64 *ts)
  1094. {
  1095. struct idtcm_channel *channel =
  1096. container_of(ptp, struct idtcm_channel, caps);
  1097. struct idtcm *idtcm = channel->idtcm;
  1098. int err;
  1099. mutex_lock(&idtcm->reg_lock);
  1100. err = _idtcm_settime_v487(channel, ts, SCSR_TOD_WR_TYPE_SEL_ABSOLUTE);
  1101. if (err)
  1102. dev_err(&idtcm->client->dev,
  1103. "Failed at line %d in func %s!\n",
  1104. __LINE__,
  1105. __func__);
  1106. mutex_unlock(&idtcm->reg_lock);
  1107. return err;
  1108. }
  1109. static int idtcm_adjtime(struct ptp_clock_info *ptp, s64 delta)
  1110. {
  1111. struct idtcm_channel *channel =
  1112. container_of(ptp, struct idtcm_channel, caps);
  1113. struct idtcm *idtcm = channel->idtcm;
  1114. int err;
  1115. mutex_lock(&idtcm->reg_lock);
  1116. err = _idtcm_adjtime(channel, delta);
  1117. if (err)
  1118. dev_err(&idtcm->client->dev,
  1119. "Failed at line %d in func %s!\n",
  1120. __LINE__,
  1121. __func__);
  1122. mutex_unlock(&idtcm->reg_lock);
  1123. return err;
  1124. }
  1125. static int idtcm_adjtime_v487(struct ptp_clock_info *ptp, s64 delta)
  1126. {
  1127. struct idtcm_channel *channel =
  1128. container_of(ptp, struct idtcm_channel, caps);
  1129. struct idtcm *idtcm = channel->idtcm;
  1130. struct timespec64 ts;
  1131. enum scsr_tod_write_type_sel type;
  1132. int err;
  1133. if (abs(delta) < PHASE_PULL_IN_THRESHOLD_NS_V487) {
  1134. err = idtcm_do_phase_pull_in(channel, delta, 0);
  1135. if (err)
  1136. dev_err(&idtcm->client->dev,
  1137. "Failed at line %d in func %s!\n",
  1138. __LINE__,
  1139. __func__);
  1140. return err;
  1141. }
  1142. if (delta >= 0) {
  1143. ts = ns_to_timespec64(delta);
  1144. type = SCSR_TOD_WR_TYPE_SEL_DELTA_PLUS;
  1145. } else {
  1146. ts = ns_to_timespec64(-delta);
  1147. type = SCSR_TOD_WR_TYPE_SEL_DELTA_MINUS;
  1148. }
  1149. mutex_lock(&idtcm->reg_lock);
  1150. err = _idtcm_settime_v487(channel, &ts, type);
  1151. if (err)
  1152. dev_err(&idtcm->client->dev,
  1153. "Failed at line %d in func %s!\n",
  1154. __LINE__,
  1155. __func__);
  1156. mutex_unlock(&idtcm->reg_lock);
  1157. return err;
  1158. }
  1159. static int idtcm_adjphase(struct ptp_clock_info *ptp, s32 delta)
  1160. {
  1161. struct idtcm_channel *channel =
  1162. container_of(ptp, struct idtcm_channel, caps);
  1163. struct idtcm *idtcm = channel->idtcm;
  1164. int err;
  1165. mutex_lock(&idtcm->reg_lock);
  1166. err = _idtcm_adjphase(channel, delta);
  1167. if (err)
  1168. dev_err(&idtcm->client->dev,
  1169. "Failed at line %d in func %s!\n",
  1170. __LINE__,
  1171. __func__);
  1172. mutex_unlock(&idtcm->reg_lock);
  1173. return err;
  1174. }
  1175. static int idtcm_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
  1176. {
  1177. struct idtcm_channel *channel =
  1178. container_of(ptp, struct idtcm_channel, caps);
  1179. struct idtcm *idtcm = channel->idtcm;
  1180. int err;
  1181. mutex_lock(&idtcm->reg_lock);
  1182. err = _idtcm_adjfine(channel, scaled_ppm);
  1183. if (err)
  1184. dev_err(&idtcm->client->dev,
  1185. "Failed at line %d in func %s!\n",
  1186. __LINE__,
  1187. __func__);
  1188. mutex_unlock(&idtcm->reg_lock);
  1189. return err;
  1190. }
  1191. static int idtcm_enable(struct ptp_clock_info *ptp,
  1192. struct ptp_clock_request *rq, int on)
  1193. {
  1194. int err;
  1195. struct idtcm_channel *channel =
  1196. container_of(ptp, struct idtcm_channel, caps);
  1197. switch (rq->type) {
  1198. case PTP_CLK_REQ_PEROUT:
  1199. if (!on) {
  1200. err = idtcm_perout_enable(channel, false, &rq->perout);
  1201. if (err)
  1202. dev_err(&channel->idtcm->client->dev,
  1203. "Failed at line %d in func %s!\n",
  1204. __LINE__,
  1205. __func__);
  1206. return err;
  1207. }
  1208. /* Only accept a 1-PPS aligned to the second. */
  1209. if (rq->perout.start.nsec || rq->perout.period.sec != 1 ||
  1210. rq->perout.period.nsec)
  1211. return -ERANGE;
  1212. err = idtcm_perout_enable(channel, true, &rq->perout);
  1213. if (err)
  1214. dev_err(&channel->idtcm->client->dev,
  1215. "Failed at line %d in func %s!\n",
  1216. __LINE__,
  1217. __func__);
  1218. return err;
  1219. default:
  1220. break;
  1221. }
  1222. return -EOPNOTSUPP;
  1223. }
  1224. static int _enable_pll_tod_sync(struct idtcm *idtcm,
  1225. u8 pll,
  1226. u8 sync_src,
  1227. u8 qn,
  1228. u8 qn_plus_1)
  1229. {
  1230. int err;
  1231. u8 val;
  1232. u16 dpll;
  1233. u16 out0 = 0, out1 = 0;
  1234. if ((qn == 0) && (qn_plus_1 == 0))
  1235. return 0;
  1236. switch (pll) {
  1237. case 0:
  1238. dpll = DPLL_0;
  1239. if (qn)
  1240. out0 = OUTPUT_0;
  1241. if (qn_plus_1)
  1242. out1 = OUTPUT_1;
  1243. break;
  1244. case 1:
  1245. dpll = DPLL_1;
  1246. if (qn)
  1247. out0 = OUTPUT_2;
  1248. if (qn_plus_1)
  1249. out1 = OUTPUT_3;
  1250. break;
  1251. case 2:
  1252. dpll = DPLL_2;
  1253. if (qn)
  1254. out0 = OUTPUT_4;
  1255. if (qn_plus_1)
  1256. out1 = OUTPUT_5;
  1257. break;
  1258. case 3:
  1259. dpll = DPLL_3;
  1260. if (qn)
  1261. out0 = OUTPUT_6;
  1262. if (qn_plus_1)
  1263. out1 = OUTPUT_7;
  1264. break;
  1265. case 4:
  1266. dpll = DPLL_4;
  1267. if (qn)
  1268. out0 = OUTPUT_8;
  1269. break;
  1270. case 5:
  1271. dpll = DPLL_5;
  1272. if (qn)
  1273. out0 = OUTPUT_9;
  1274. if (qn_plus_1)
  1275. out1 = OUTPUT_8;
  1276. break;
  1277. case 6:
  1278. dpll = DPLL_6;
  1279. if (qn)
  1280. out0 = OUTPUT_10;
  1281. if (qn_plus_1)
  1282. out1 = OUTPUT_11;
  1283. break;
  1284. case 7:
  1285. dpll = DPLL_7;
  1286. if (qn)
  1287. out0 = OUTPUT_11;
  1288. break;
  1289. default:
  1290. return -EINVAL;
  1291. }
  1292. /*
  1293. * Enable OUTPUT OUT_SYNC.
  1294. */
  1295. if (out0) {
  1296. err = idtcm_read(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
  1297. if (err)
  1298. return err;
  1299. val &= ~OUT_SYNC_DISABLE;
  1300. err = idtcm_write(idtcm, out0, OUT_CTRL_1, &val, sizeof(val));
  1301. if (err)
  1302. return err;
  1303. }
  1304. if (out1) {
  1305. err = idtcm_read(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
  1306. if (err)
  1307. return err;
  1308. val &= ~OUT_SYNC_DISABLE;
  1309. err = idtcm_write(idtcm, out1, OUT_CTRL_1, &val, sizeof(val));
  1310. if (err)
  1311. return err;
  1312. }
  1313. /* enable dpll sync tod pps, must be set before dpll_mode */
  1314. err = idtcm_read(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
  1315. if (err)
  1316. return err;
  1317. val &= ~(TOD_SYNC_SOURCE_MASK << TOD_SYNC_SOURCE_SHIFT);
  1318. val |= (sync_src << TOD_SYNC_SOURCE_SHIFT);
  1319. val |= TOD_SYNC_EN;
  1320. return idtcm_write(idtcm, dpll, DPLL_TOD_SYNC_CFG, &val, sizeof(val));
  1321. }
  1322. static int idtcm_enable_tod_sync(struct idtcm_channel *channel)
  1323. {
  1324. struct idtcm *idtcm = channel->idtcm;
  1325. u8 pll;
  1326. u8 sync_src;
  1327. u8 qn;
  1328. u8 qn_plus_1;
  1329. u8 cfg;
  1330. int err = 0;
  1331. u16 output_mask = channel->output_mask;
  1332. u8 out8_mux = 0;
  1333. u8 out11_mux = 0;
  1334. u8 temp;
  1335. /*
  1336. * set tod_out_sync_enable to 0.
  1337. */
  1338. err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
  1339. if (err)
  1340. return err;
  1341. cfg &= ~TOD_OUT_SYNC_ENABLE;
  1342. err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
  1343. if (err)
  1344. return err;
  1345. switch (channel->tod_n) {
  1346. case TOD_0:
  1347. sync_src = 0;
  1348. break;
  1349. case TOD_1:
  1350. sync_src = 1;
  1351. break;
  1352. case TOD_2:
  1353. sync_src = 2;
  1354. break;
  1355. case TOD_3:
  1356. sync_src = 3;
  1357. break;
  1358. default:
  1359. return -EINVAL;
  1360. }
  1361. err = idtcm_read(idtcm, 0, HW_Q8_CTRL_SPARE,
  1362. &temp, sizeof(temp));
  1363. if (err)
  1364. return err;
  1365. if ((temp & Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
  1366. Q9_TO_Q8_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
  1367. out8_mux = 1;
  1368. err = idtcm_read(idtcm, 0, HW_Q11_CTRL_SPARE,
  1369. &temp, sizeof(temp));
  1370. if (err)
  1371. return err;
  1372. if ((temp & Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK) ==
  1373. Q10_TO_Q11_FANOUT_AND_CLOCK_SYNC_ENABLE_MASK)
  1374. out11_mux = 1;
  1375. for (pll = 0; pll < 8; pll++) {
  1376. qn = 0;
  1377. qn_plus_1 = 0;
  1378. if (pll < 4) {
  1379. /* First 4 pll has 2 outputs */
  1380. qn = output_mask & 0x1;
  1381. output_mask = output_mask >> 1;
  1382. qn_plus_1 = output_mask & 0x1;
  1383. output_mask = output_mask >> 1;
  1384. } else if (pll == 4) {
  1385. if (out8_mux == 0) {
  1386. qn = output_mask & 0x1;
  1387. output_mask = output_mask >> 1;
  1388. }
  1389. } else if (pll == 5) {
  1390. if (out8_mux) {
  1391. qn_plus_1 = output_mask & 0x1;
  1392. output_mask = output_mask >> 1;
  1393. }
  1394. qn = output_mask & 0x1;
  1395. output_mask = output_mask >> 1;
  1396. } else if (pll == 6) {
  1397. qn = output_mask & 0x1;
  1398. output_mask = output_mask >> 1;
  1399. if (out11_mux) {
  1400. qn_plus_1 = output_mask & 0x1;
  1401. output_mask = output_mask >> 1;
  1402. }
  1403. } else if (pll == 7) {
  1404. if (out11_mux == 0) {
  1405. qn = output_mask & 0x1;
  1406. output_mask = output_mask >> 1;
  1407. }
  1408. }
  1409. if ((qn != 0) || (qn_plus_1 != 0))
  1410. err = _enable_pll_tod_sync(idtcm, pll, sync_src, qn,
  1411. qn_plus_1);
  1412. if (err)
  1413. return err;
  1414. }
  1415. return err;
  1416. }
  1417. static int idtcm_enable_tod(struct idtcm_channel *channel)
  1418. {
  1419. struct idtcm *idtcm = channel->idtcm;
  1420. struct timespec64 ts = {0, 0};
  1421. u8 cfg;
  1422. int err;
  1423. /*
  1424. * Start the TOD clock ticking.
  1425. */
  1426. err = idtcm_read(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
  1427. if (err)
  1428. return err;
  1429. cfg |= TOD_ENABLE;
  1430. err = idtcm_write(idtcm, channel->tod_n, TOD_CFG, &cfg, sizeof(cfg));
  1431. if (err)
  1432. return err;
  1433. return _idtcm_settime(channel, &ts, HW_TOD_WR_TRIG_SEL_MSB);
  1434. }
  1435. static void idtcm_display_version_info(struct idtcm *idtcm)
  1436. {
  1437. u8 major;
  1438. u8 minor;
  1439. u8 hotfix;
  1440. u16 product_id;
  1441. u8 hw_rev_id;
  1442. u8 config_select;
  1443. char *fmt = "%d.%d.%d, Id: 0x%04x HW Rev: %d OTP Config Select: %d\n";
  1444. idtcm_read_major_release(idtcm, &major);
  1445. idtcm_read_minor_release(idtcm, &minor);
  1446. idtcm_read_hotfix_release(idtcm, &hotfix);
  1447. idtcm_read_product_id(idtcm, &product_id);
  1448. idtcm_read_hw_rev_id(idtcm, &hw_rev_id);
  1449. idtcm_read_otp_scsr_config_select(idtcm, &config_select);
  1450. snprintf(idtcm->version, sizeof(idtcm->version), "%u.%u.%u",
  1451. major, minor, hotfix);
  1452. dev_info(&idtcm->client->dev, fmt, major, minor, hotfix,
  1453. product_id, hw_rev_id, config_select);
  1454. }
  1455. static const struct ptp_clock_info idtcm_caps_v487 = {
  1456. .owner = THIS_MODULE,
  1457. .max_adj = 244000,
  1458. .n_per_out = 12,
  1459. .adjphase = &idtcm_adjphase,
  1460. .adjfine = &idtcm_adjfine,
  1461. .adjtime = &idtcm_adjtime_v487,
  1462. .gettime64 = &idtcm_gettime,
  1463. .settime64 = &idtcm_settime_v487,
  1464. .enable = &idtcm_enable,
  1465. .do_aux_work = &set_write_phase_ready,
  1466. };
  1467. static const struct ptp_clock_info idtcm_caps = {
  1468. .owner = THIS_MODULE,
  1469. .max_adj = 244000,
  1470. .n_per_out = 12,
  1471. .adjphase = &idtcm_adjphase,
  1472. .adjfine = &idtcm_adjfine,
  1473. .adjtime = &idtcm_adjtime,
  1474. .gettime64 = &idtcm_gettime,
  1475. .settime64 = &idtcm_settime,
  1476. .enable = &idtcm_enable,
  1477. .do_aux_work = &set_write_phase_ready,
  1478. };
  1479. static int configure_channel_pll(struct idtcm_channel *channel)
  1480. {
  1481. int err = 0;
  1482. switch (channel->pll) {
  1483. case 0:
  1484. channel->dpll_freq = DPLL_FREQ_0;
  1485. channel->dpll_n = DPLL_0;
  1486. channel->hw_dpll_n = HW_DPLL_0;
  1487. channel->dpll_phase = DPLL_PHASE_0;
  1488. channel->dpll_ctrl_n = DPLL_CTRL_0;
  1489. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_0;
  1490. break;
  1491. case 1:
  1492. channel->dpll_freq = DPLL_FREQ_1;
  1493. channel->dpll_n = DPLL_1;
  1494. channel->hw_dpll_n = HW_DPLL_1;
  1495. channel->dpll_phase = DPLL_PHASE_1;
  1496. channel->dpll_ctrl_n = DPLL_CTRL_1;
  1497. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_1;
  1498. break;
  1499. case 2:
  1500. channel->dpll_freq = DPLL_FREQ_2;
  1501. channel->dpll_n = DPLL_2;
  1502. channel->hw_dpll_n = HW_DPLL_2;
  1503. channel->dpll_phase = DPLL_PHASE_2;
  1504. channel->dpll_ctrl_n = DPLL_CTRL_2;
  1505. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_2;
  1506. break;
  1507. case 3:
  1508. channel->dpll_freq = DPLL_FREQ_3;
  1509. channel->dpll_n = DPLL_3;
  1510. channel->hw_dpll_n = HW_DPLL_3;
  1511. channel->dpll_phase = DPLL_PHASE_3;
  1512. channel->dpll_ctrl_n = DPLL_CTRL_3;
  1513. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_3;
  1514. break;
  1515. case 4:
  1516. channel->dpll_freq = DPLL_FREQ_4;
  1517. channel->dpll_n = DPLL_4;
  1518. channel->hw_dpll_n = HW_DPLL_4;
  1519. channel->dpll_phase = DPLL_PHASE_4;
  1520. channel->dpll_ctrl_n = DPLL_CTRL_4;
  1521. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_4;
  1522. break;
  1523. case 5:
  1524. channel->dpll_freq = DPLL_FREQ_5;
  1525. channel->dpll_n = DPLL_5;
  1526. channel->hw_dpll_n = HW_DPLL_5;
  1527. channel->dpll_phase = DPLL_PHASE_5;
  1528. channel->dpll_ctrl_n = DPLL_CTRL_5;
  1529. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_5;
  1530. break;
  1531. case 6:
  1532. channel->dpll_freq = DPLL_FREQ_6;
  1533. channel->dpll_n = DPLL_6;
  1534. channel->hw_dpll_n = HW_DPLL_6;
  1535. channel->dpll_phase = DPLL_PHASE_6;
  1536. channel->dpll_ctrl_n = DPLL_CTRL_6;
  1537. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_6;
  1538. break;
  1539. case 7:
  1540. channel->dpll_freq = DPLL_FREQ_7;
  1541. channel->dpll_n = DPLL_7;
  1542. channel->hw_dpll_n = HW_DPLL_7;
  1543. channel->dpll_phase = DPLL_PHASE_7;
  1544. channel->dpll_ctrl_n = DPLL_CTRL_7;
  1545. channel->dpll_phase_pull_in = DPLL_PHASE_PULL_IN_7;
  1546. break;
  1547. default:
  1548. err = -EINVAL;
  1549. }
  1550. return err;
  1551. }
  1552. static int idtcm_enable_channel(struct idtcm *idtcm, u32 index)
  1553. {
  1554. struct idtcm_channel *channel;
  1555. int err;
  1556. if (!(index < MAX_TOD))
  1557. return -EINVAL;
  1558. channel = &idtcm->channel[index];
  1559. /* Set pll addresses */
  1560. err = configure_channel_pll(channel);
  1561. if (err)
  1562. return err;
  1563. /* Set tod addresses */
  1564. switch (index) {
  1565. case 0:
  1566. channel->tod_read_primary = TOD_READ_PRIMARY_0;
  1567. channel->tod_write = TOD_WRITE_0;
  1568. channel->tod_n = TOD_0;
  1569. break;
  1570. case 1:
  1571. channel->tod_read_primary = TOD_READ_PRIMARY_1;
  1572. channel->tod_write = TOD_WRITE_1;
  1573. channel->tod_n = TOD_1;
  1574. break;
  1575. case 2:
  1576. channel->tod_read_primary = TOD_READ_PRIMARY_2;
  1577. channel->tod_write = TOD_WRITE_2;
  1578. channel->tod_n = TOD_2;
  1579. break;
  1580. case 3:
  1581. channel->tod_read_primary = TOD_READ_PRIMARY_3;
  1582. channel->tod_write = TOD_WRITE_3;
  1583. channel->tod_n = TOD_3;
  1584. break;
  1585. default:
  1586. return -EINVAL;
  1587. }
  1588. channel->idtcm = idtcm;
  1589. if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0)
  1590. channel->caps = idtcm_caps_v487;
  1591. else
  1592. channel->caps = idtcm_caps;
  1593. snprintf(channel->caps.name, sizeof(channel->caps.name),
  1594. "IDT CM TOD%u", index);
  1595. if (idtcm_strverscmp(idtcm->version, "4.8.7") >= 0) {
  1596. err = idtcm_enable_tod_sync(channel);
  1597. if (err) {
  1598. dev_err(&idtcm->client->dev,
  1599. "Failed at line %d in func %s!\n",
  1600. __LINE__,
  1601. __func__);
  1602. return err;
  1603. }
  1604. }
  1605. err = idtcm_set_pll_mode(channel, PLL_MODE_WRITE_FREQUENCY);
  1606. if (err) {
  1607. dev_err(&idtcm->client->dev,
  1608. "Failed at line %d in func %s!\n",
  1609. __LINE__,
  1610. __func__);
  1611. return err;
  1612. }
  1613. err = idtcm_enable_tod(channel);
  1614. if (err) {
  1615. dev_err(&idtcm->client->dev,
  1616. "Failed at line %d in func %s!\n",
  1617. __LINE__,
  1618. __func__);
  1619. return err;
  1620. }
  1621. channel->ptp_clock = ptp_clock_register(&channel->caps, NULL);
  1622. if (IS_ERR(channel->ptp_clock)) {
  1623. err = PTR_ERR(channel->ptp_clock);
  1624. channel->ptp_clock = NULL;
  1625. return err;
  1626. }
  1627. if (!channel->ptp_clock)
  1628. return -ENOTSUPP;
  1629. channel->write_phase_ready = 0;
  1630. dev_info(&idtcm->client->dev, "PLL%d registered as ptp%d\n",
  1631. index, channel->ptp_clock->index);
  1632. return 0;
  1633. }
  1634. static void ptp_clock_unregister_all(struct idtcm *idtcm)
  1635. {
  1636. u8 i;
  1637. struct idtcm_channel *channel;
  1638. for (i = 0; i < MAX_TOD; i++) {
  1639. channel = &idtcm->channel[i];
  1640. if (channel->ptp_clock)
  1641. ptp_clock_unregister(channel->ptp_clock);
  1642. }
  1643. }
  1644. static void set_default_masks(struct idtcm *idtcm)
  1645. {
  1646. idtcm->tod_mask = DEFAULT_TOD_MASK;
  1647. idtcm->channel[0].pll = DEFAULT_TOD0_PTP_PLL;
  1648. idtcm->channel[1].pll = DEFAULT_TOD1_PTP_PLL;
  1649. idtcm->channel[2].pll = DEFAULT_TOD2_PTP_PLL;
  1650. idtcm->channel[3].pll = DEFAULT_TOD3_PTP_PLL;
  1651. idtcm->channel[0].output_mask = DEFAULT_OUTPUT_MASK_PLL0;
  1652. idtcm->channel[1].output_mask = DEFAULT_OUTPUT_MASK_PLL1;
  1653. idtcm->channel[2].output_mask = DEFAULT_OUTPUT_MASK_PLL2;
  1654. idtcm->channel[3].output_mask = DEFAULT_OUTPUT_MASK_PLL3;
  1655. }
  1656. static int idtcm_probe(struct i2c_client *client,
  1657. const struct i2c_device_id *id)
  1658. {
  1659. struct idtcm *idtcm;
  1660. int err;
  1661. u8 i;
  1662. char *fmt = "Failed at %d in line %s with channel output %d!\n";
  1663. /* Unused for now */
  1664. (void)id;
  1665. idtcm = devm_kzalloc(&client->dev, sizeof(struct idtcm), GFP_KERNEL);
  1666. if (!idtcm)
  1667. return -ENOMEM;
  1668. idtcm->client = client;
  1669. idtcm->page_offset = 0xff;
  1670. idtcm->calculate_overhead_flag = 0;
  1671. set_default_masks(idtcm);
  1672. mutex_init(&idtcm->reg_lock);
  1673. mutex_lock(&idtcm->reg_lock);
  1674. idtcm_display_version_info(idtcm);
  1675. err = idtcm_load_firmware(idtcm, &client->dev);
  1676. if (err)
  1677. dev_warn(&idtcm->client->dev,
  1678. "loading firmware failed with %d\n", err);
  1679. if (idtcm->tod_mask) {
  1680. for (i = 0; i < MAX_TOD; i++) {
  1681. if (idtcm->tod_mask & (1 << i)) {
  1682. err = idtcm_enable_channel(idtcm, i);
  1683. if (err) {
  1684. dev_err(&idtcm->client->dev,
  1685. fmt,
  1686. __LINE__,
  1687. __func__,
  1688. i);
  1689. break;
  1690. }
  1691. }
  1692. }
  1693. } else {
  1694. dev_err(&idtcm->client->dev,
  1695. "no PLLs flagged as PHCs, nothing to do\n");
  1696. err = -ENODEV;
  1697. }
  1698. mutex_unlock(&idtcm->reg_lock);
  1699. if (err) {
  1700. ptp_clock_unregister_all(idtcm);
  1701. return err;
  1702. }
  1703. i2c_set_clientdata(client, idtcm);
  1704. return 0;
  1705. }
  1706. static int idtcm_remove(struct i2c_client *client)
  1707. {
  1708. struct idtcm *idtcm = i2c_get_clientdata(client);
  1709. ptp_clock_unregister_all(idtcm);
  1710. mutex_destroy(&idtcm->reg_lock);
  1711. return 0;
  1712. }
  1713. #ifdef CONFIG_OF
  1714. static const struct of_device_id idtcm_dt_id[] = {
  1715. { .compatible = "idt,8a34000" },
  1716. { .compatible = "idt,8a34001" },
  1717. { .compatible = "idt,8a34002" },
  1718. { .compatible = "idt,8a34003" },
  1719. { .compatible = "idt,8a34004" },
  1720. { .compatible = "idt,8a34005" },
  1721. { .compatible = "idt,8a34006" },
  1722. { .compatible = "idt,8a34007" },
  1723. { .compatible = "idt,8a34008" },
  1724. { .compatible = "idt,8a34009" },
  1725. { .compatible = "idt,8a34010" },
  1726. { .compatible = "idt,8a34011" },
  1727. { .compatible = "idt,8a34012" },
  1728. { .compatible = "idt,8a34013" },
  1729. { .compatible = "idt,8a34014" },
  1730. { .compatible = "idt,8a34015" },
  1731. { .compatible = "idt,8a34016" },
  1732. { .compatible = "idt,8a34017" },
  1733. { .compatible = "idt,8a34018" },
  1734. { .compatible = "idt,8a34019" },
  1735. { .compatible = "idt,8a34040" },
  1736. { .compatible = "idt,8a34041" },
  1737. { .compatible = "idt,8a34042" },
  1738. { .compatible = "idt,8a34043" },
  1739. { .compatible = "idt,8a34044" },
  1740. { .compatible = "idt,8a34045" },
  1741. { .compatible = "idt,8a34046" },
  1742. { .compatible = "idt,8a34047" },
  1743. { .compatible = "idt,8a34048" },
  1744. { .compatible = "idt,8a34049" },
  1745. {},
  1746. };
  1747. MODULE_DEVICE_TABLE(of, idtcm_dt_id);
  1748. #endif
  1749. static const struct i2c_device_id idtcm_i2c_id[] = {
  1750. { "8a34000" },
  1751. { "8a34001" },
  1752. { "8a34002" },
  1753. { "8a34003" },
  1754. { "8a34004" },
  1755. { "8a34005" },
  1756. { "8a34006" },
  1757. { "8a34007" },
  1758. { "8a34008" },
  1759. { "8a34009" },
  1760. { "8a34010" },
  1761. { "8a34011" },
  1762. { "8a34012" },
  1763. { "8a34013" },
  1764. { "8a34014" },
  1765. { "8a34015" },
  1766. { "8a34016" },
  1767. { "8a34017" },
  1768. { "8a34018" },
  1769. { "8a34019" },
  1770. { "8a34040" },
  1771. { "8a34041" },
  1772. { "8a34042" },
  1773. { "8a34043" },
  1774. { "8a34044" },
  1775. { "8a34045" },
  1776. { "8a34046" },
  1777. { "8a34047" },
  1778. { "8a34048" },
  1779. { "8a34049" },
  1780. {},
  1781. };
  1782. MODULE_DEVICE_TABLE(i2c, idtcm_i2c_id);
  1783. static struct i2c_driver idtcm_driver = {
  1784. .driver = {
  1785. .of_match_table = of_match_ptr(idtcm_dt_id),
  1786. .name = "idtcm",
  1787. },
  1788. .probe = idtcm_probe,
  1789. .remove = idtcm_remove,
  1790. .id_table = idtcm_i2c_id,
  1791. };
  1792. module_i2c_driver(idtcm_driver);