pm2301_charger.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) ST-Ericsson SA 2012
  4. *
  5. * PM2301 power supply interface
  6. */
  7. #ifndef PM2301_CHARGER_H
  8. #define PM2301_CHARGER_H
  9. /* Watchdog timeout constant */
  10. #define WD_TIMER 0x30 /* 4min */
  11. #define WD_KICK_INTERVAL (30 * HZ)
  12. #define PM2XXX_NUM_INT_REG 0x6
  13. /* Constant voltage/current */
  14. #define PM2XXX_CONST_CURR 0x0
  15. #define PM2XXX_CONST_VOLT 0x1
  16. /* Lowest charger voltage is 3.39V -> 0x4E */
  17. #define LOW_VOLT_REG 0x4E
  18. #define PM2XXX_BATT_CTRL_REG1 0x00
  19. #define PM2XXX_BATT_CTRL_REG2 0x01
  20. #define PM2XXX_BATT_CTRL_REG3 0x02
  21. #define PM2XXX_BATT_CTRL_REG4 0x03
  22. #define PM2XXX_BATT_CTRL_REG5 0x04
  23. #define PM2XXX_BATT_CTRL_REG6 0x05
  24. #define PM2XXX_BATT_CTRL_REG7 0x06
  25. #define PM2XXX_BATT_CTRL_REG8 0x07
  26. #define PM2XXX_NTC_CTRL_REG1 0x08
  27. #define PM2XXX_NTC_CTRL_REG2 0x09
  28. #define PM2XXX_BATT_CTRL_REG9 0x0A
  29. #define PM2XXX_BATT_STAT_REG1 0x0B
  30. #define PM2XXX_INP_VOLT_VPWR2 0x11
  31. #define PM2XXX_INP_DROP_VPWR2 0x13
  32. #define PM2XXX_INP_VOLT_VPWR1 0x15
  33. #define PM2XXX_INP_DROP_VPWR1 0x17
  34. #define PM2XXX_INP_MODE_VPWR 0x18
  35. #define PM2XXX_BATT_WD_KICK 0x70
  36. #define PM2XXX_DEV_VER_STAT 0x0C
  37. #define PM2XXX_THERM_WARN_CTRL_REG 0x20
  38. #define PM2XXX_BATT_DISC_REG 0x21
  39. #define PM2XXX_BATT_LOW_LEV_COMP_REG 0x22
  40. #define PM2XXX_BATT_LOW_LEV_VAL_REG 0x23
  41. #define PM2XXX_I2C_PAD_CTRL_REG 0x24
  42. #define PM2XXX_SW_CTRL_REG 0x26
  43. #define PM2XXX_LED_CTRL_REG 0x28
  44. #define PM2XXX_REG_INT1 0x40
  45. #define PM2XXX_MASK_REG_INT1 0x50
  46. #define PM2XXX_SRCE_REG_INT1 0x60
  47. #define PM2XXX_REG_INT2 0x41
  48. #define PM2XXX_MASK_REG_INT2 0x51
  49. #define PM2XXX_SRCE_REG_INT2 0x61
  50. #define PM2XXX_REG_INT3 0x42
  51. #define PM2XXX_MASK_REG_INT3 0x52
  52. #define PM2XXX_SRCE_REG_INT3 0x62
  53. #define PM2XXX_REG_INT4 0x43
  54. #define PM2XXX_MASK_REG_INT4 0x53
  55. #define PM2XXX_SRCE_REG_INT4 0x63
  56. #define PM2XXX_REG_INT5 0x44
  57. #define PM2XXX_MASK_REG_INT5 0x54
  58. #define PM2XXX_SRCE_REG_INT5 0x64
  59. #define PM2XXX_REG_INT6 0x45
  60. #define PM2XXX_MASK_REG_INT6 0x55
  61. #define PM2XXX_SRCE_REG_INT6 0x65
  62. #define VPWR_OVV 0x0
  63. #define VSYSTEM_OVV 0x1
  64. /* control Reg 1 */
  65. #define PM2XXX_CH_RESUME_EN 0x1
  66. #define PM2XXX_CH_RESUME_DIS 0x0
  67. /* control Reg 2 */
  68. #define PM2XXX_CH_AUTO_RESUME_EN 0X2
  69. #define PM2XXX_CH_AUTO_RESUME_DIS 0X0
  70. #define PM2XXX_CHARGER_ENA 0x4
  71. #define PM2XXX_CHARGER_DIS 0x0
  72. /* control Reg 3 */
  73. #define PM2XXX_CH_WD_CC_PHASE_OFF 0x0
  74. #define PM2XXX_CH_WD_CC_PHASE_5MIN 0x1
  75. #define PM2XXX_CH_WD_CC_PHASE_10MIN 0x2
  76. #define PM2XXX_CH_WD_CC_PHASE_30MIN 0x3
  77. #define PM2XXX_CH_WD_CC_PHASE_60MIN 0x4
  78. #define PM2XXX_CH_WD_CC_PHASE_120MIN 0x5
  79. #define PM2XXX_CH_WD_CC_PHASE_240MIN 0x6
  80. #define PM2XXX_CH_WD_CC_PHASE_360MIN 0x7
  81. #define PM2XXX_CH_WD_CV_PHASE_OFF (0x0<<3)
  82. #define PM2XXX_CH_WD_CV_PHASE_5MIN (0x1<<3)
  83. #define PM2XXX_CH_WD_CV_PHASE_10MIN (0x2<<3)
  84. #define PM2XXX_CH_WD_CV_PHASE_30MIN (0x3<<3)
  85. #define PM2XXX_CH_WD_CV_PHASE_60MIN (0x4<<3)
  86. #define PM2XXX_CH_WD_CV_PHASE_120MIN (0x5<<3)
  87. #define PM2XXX_CH_WD_CV_PHASE_240MIN (0x6<<3)
  88. #define PM2XXX_CH_WD_CV_PHASE_360MIN (0x7<<3)
  89. /* control Reg 4 */
  90. #define PM2XXX_CH_WD_PRECH_PHASE_OFF 0x0
  91. #define PM2XXX_CH_WD_PRECH_PHASE_1MIN 0x1
  92. #define PM2XXX_CH_WD_PRECH_PHASE_5MIN 0x2
  93. #define PM2XXX_CH_WD_PRECH_PHASE_10MIN 0x3
  94. #define PM2XXX_CH_WD_PRECH_PHASE_30MIN 0x4
  95. #define PM2XXX_CH_WD_PRECH_PHASE_60MIN 0x5
  96. #define PM2XXX_CH_WD_PRECH_PHASE_120MIN 0x6
  97. #define PM2XXX_CH_WD_PRECH_PHASE_240MIN 0x7
  98. /* control Reg 5 */
  99. #define PM2XXX_CH_WD_AUTO_TIMEOUT_NONE 0x0
  100. #define PM2XXX_CH_WD_AUTO_TIMEOUT_20MIN 0x1
  101. /* control Reg 6 */
  102. #define PM2XXX_DIR_CH_CC_CURRENT_MASK 0x0F
  103. #define PM2XXX_DIR_CH_CC_CURRENT_200MA 0x0
  104. #define PM2XXX_DIR_CH_CC_CURRENT_400MA 0x2
  105. #define PM2XXX_DIR_CH_CC_CURRENT_600MA 0x3
  106. #define PM2XXX_DIR_CH_CC_CURRENT_800MA 0x4
  107. #define PM2XXX_DIR_CH_CC_CURRENT_1000MA 0x5
  108. #define PM2XXX_DIR_CH_CC_CURRENT_1200MA 0x6
  109. #define PM2XXX_DIR_CH_CC_CURRENT_1400MA 0x7
  110. #define PM2XXX_DIR_CH_CC_CURRENT_1600MA 0x8
  111. #define PM2XXX_DIR_CH_CC_CURRENT_1800MA 0x9
  112. #define PM2XXX_DIR_CH_CC_CURRENT_2000MA 0xA
  113. #define PM2XXX_DIR_CH_CC_CURRENT_2200MA 0xB
  114. #define PM2XXX_DIR_CH_CC_CURRENT_2400MA 0xC
  115. #define PM2XXX_DIR_CH_CC_CURRENT_2600MA 0xD
  116. #define PM2XXX_DIR_CH_CC_CURRENT_2800MA 0xE
  117. #define PM2XXX_DIR_CH_CC_CURRENT_3000MA 0xF
  118. #define PM2XXX_CH_PRECH_CURRENT_MASK 0x30
  119. #define PM2XXX_CH_PRECH_CURRENT_25MA (0x0<<4)
  120. #define PM2XXX_CH_PRECH_CURRENT_50MA (0x1<<4)
  121. #define PM2XXX_CH_PRECH_CURRENT_75MA (0x2<<4)
  122. #define PM2XXX_CH_PRECH_CURRENT_100MA (0x3<<4)
  123. #define PM2XXX_CH_EOC_CURRENT_MASK 0xC0
  124. #define PM2XXX_CH_EOC_CURRENT_100MA (0x0<<6)
  125. #define PM2XXX_CH_EOC_CURRENT_150MA (0x1<<6)
  126. #define PM2XXX_CH_EOC_CURRENT_300MA (0x2<<6)
  127. #define PM2XXX_CH_EOC_CURRENT_400MA (0x3<<6)
  128. /* control Reg 7 */
  129. #define PM2XXX_CH_PRECH_VOL_2_5 0x0
  130. #define PM2XXX_CH_PRECH_VOL_2_7 0x1
  131. #define PM2XXX_CH_PRECH_VOL_2_9 0x2
  132. #define PM2XXX_CH_PRECH_VOL_3_1 0x3
  133. #define PM2XXX_CH_VRESUME_VOL_3_2 (0x0<<2)
  134. #define PM2XXX_CH_VRESUME_VOL_3_4 (0x1<<2)
  135. #define PM2XXX_CH_VRESUME_VOL_3_6 (0x2<<2)
  136. #define PM2XXX_CH_VRESUME_VOL_3_8 (0x3<<2)
  137. /* control Reg 8 */
  138. #define PM2XXX_CH_VOLT_MASK 0x3F
  139. #define PM2XXX_CH_VOLT_3_5 0x0
  140. #define PM2XXX_CH_VOLT_3_5225 0x1
  141. #define PM2XXX_CH_VOLT_3_6 0x4
  142. #define PM2XXX_CH_VOLT_3_7 0x8
  143. #define PM2XXX_CH_VOLT_4_0 0x14
  144. #define PM2XXX_CH_VOLT_4_175 0x1B
  145. #define PM2XXX_CH_VOLT_4_2 0x1C
  146. #define PM2XXX_CH_VOLT_4_275 0x1F
  147. #define PM2XXX_CH_VOLT_4_3 0x20
  148. /*NTC control register 1*/
  149. #define PM2XXX_BTEMP_HIGH_TH_45 0x0
  150. #define PM2XXX_BTEMP_HIGH_TH_50 0x1
  151. #define PM2XXX_BTEMP_HIGH_TH_55 0x2
  152. #define PM2XXX_BTEMP_HIGH_TH_60 0x3
  153. #define PM2XXX_BTEMP_HIGH_TH_65 0x4
  154. #define PM2XXX_BTEMP_LOW_TH_N5 (0x0<<3)
  155. #define PM2XXX_BTEMP_LOW_TH_0 (0x1<<3)
  156. #define PM2XXX_BTEMP_LOW_TH_5 (0x2<<3)
  157. #define PM2XXX_BTEMP_LOW_TH_10 (0x3<<3)
  158. /*NTC control register 2*/
  159. #define PM2XXX_NTC_BETA_COEFF_3477 0x0
  160. #define PM2XXX_NTC_BETA_COEFF_3964 0x1
  161. #define PM2XXX_NTC_RES_10K (0x0<<2)
  162. #define PM2XXX_NTC_RES_47K (0x1<<2)
  163. #define PM2XXX_NTC_RES_100K (0x2<<2)
  164. #define PM2XXX_NTC_RES_NO_NTC (0x3<<2)
  165. /* control Reg 9 */
  166. #define PM2XXX_CH_CC_MODEDROP_EN 1
  167. #define PM2XXX_CH_CC_MODEDROP_DIS 0
  168. #define PM2XXX_CH_CC_REDUCED_CURRENT_100MA (0x0<<1)
  169. #define PM2XXX_CH_CC_REDUCED_CURRENT_200MA (0x1<<1)
  170. #define PM2XXX_CH_CC_REDUCED_CURRENT_400MA (0x2<<1)
  171. #define PM2XXX_CH_CC_REDUCED_CURRENT_IDENT (0x3<<1)
  172. #define PM2XXX_CHARCHING_INFO_DIS (0<<3)
  173. #define PM2XXX_CHARCHING_INFO_EN (1<<3)
  174. #define PM2XXX_CH_150MV_DROP_300MV (0<<4)
  175. #define PM2XXX_CH_150MV_DROP_150MV (1<<4)
  176. /* charger status register */
  177. #define PM2XXX_CHG_STATUS_OFF 0x0
  178. #define PM2XXX_CHG_STATUS_ON 0x1
  179. #define PM2XXX_CHG_STATUS_FULL 0x2
  180. #define PM2XXX_CHG_STATUS_ERR 0x3
  181. #define PM2XXX_CHG_STATUS_WAIT 0x4
  182. #define PM2XXX_CHG_STATUS_NOBAT 0x5
  183. /* Input charger voltage VPWR2 */
  184. #define PM2XXX_VPWR2_OVV_6_0 0x0
  185. #define PM2XXX_VPWR2_OVV_6_3 0x1
  186. #define PM2XXX_VPWR2_OVV_10 0x2
  187. #define PM2XXX_VPWR2_OVV_NONE 0x3
  188. /* Input charger drop VPWR2 */
  189. #define PM2XXX_VPWR2_HW_OPT_EN (0x1<<4)
  190. #define PM2XXX_VPWR2_HW_OPT_DIS (0x0<<4)
  191. #define PM2XXX_VPWR2_VALID_EN (0x1<<3)
  192. #define PM2XXX_VPWR2_VALID_DIS (0x0<<3)
  193. #define PM2XXX_VPWR2_DROP_EN (0x1<<2)
  194. #define PM2XXX_VPWR2_DROP_DIS (0x0<<2)
  195. /* Input charger voltage VPWR1 */
  196. #define PM2XXX_VPWR1_OVV_6_0 0x0
  197. #define PM2XXX_VPWR1_OVV_6_3 0x1
  198. #define PM2XXX_VPWR1_OVV_10 0x2
  199. #define PM2XXX_VPWR1_OVV_NONE 0x3
  200. /* Input charger drop VPWR1 */
  201. #define PM2XXX_VPWR1_HW_OPT_EN (0x1<<4)
  202. #define PM2XXX_VPWR1_HW_OPT_DIS (0x0<<4)
  203. #define PM2XXX_VPWR1_VALID_EN (0x1<<3)
  204. #define PM2XXX_VPWR1_VALID_DIS (0x0<<3)
  205. #define PM2XXX_VPWR1_DROP_EN (0x1<<2)
  206. #define PM2XXX_VPWR1_DROP_DIS (0x0<<2)
  207. /* Battery low level comparator control register */
  208. #define PM2XXX_VBAT_LOW_MONITORING_DIS 0x0
  209. #define PM2XXX_VBAT_LOW_MONITORING_ENA 0x1
  210. /* Battery low level value control register */
  211. #define PM2XXX_VBAT_LOW_LEVEL_2_3 0x0
  212. #define PM2XXX_VBAT_LOW_LEVEL_2_4 0x1
  213. #define PM2XXX_VBAT_LOW_LEVEL_2_5 0x2
  214. #define PM2XXX_VBAT_LOW_LEVEL_2_6 0x3
  215. #define PM2XXX_VBAT_LOW_LEVEL_2_7 0x4
  216. #define PM2XXX_VBAT_LOW_LEVEL_2_8 0x5
  217. #define PM2XXX_VBAT_LOW_LEVEL_2_9 0x6
  218. #define PM2XXX_VBAT_LOW_LEVEL_3_0 0x7
  219. #define PM2XXX_VBAT_LOW_LEVEL_3_1 0x8
  220. #define PM2XXX_VBAT_LOW_LEVEL_3_2 0x9
  221. #define PM2XXX_VBAT_LOW_LEVEL_3_3 0xA
  222. #define PM2XXX_VBAT_LOW_LEVEL_3_4 0xB
  223. #define PM2XXX_VBAT_LOW_LEVEL_3_5 0xC
  224. #define PM2XXX_VBAT_LOW_LEVEL_3_6 0xD
  225. #define PM2XXX_VBAT_LOW_LEVEL_3_7 0xE
  226. #define PM2XXX_VBAT_LOW_LEVEL_3_8 0xF
  227. #define PM2XXX_VBAT_LOW_LEVEL_3_9 0x10
  228. #define PM2XXX_VBAT_LOW_LEVEL_4_0 0x11
  229. #define PM2XXX_VBAT_LOW_LEVEL_4_1 0x12
  230. #define PM2XXX_VBAT_LOW_LEVEL_4_2 0x13
  231. /* SW CTRL */
  232. #define PM2XXX_SWCTRL_HW 0x0
  233. #define PM2XXX_SWCTRL_SW 0x1
  234. /* LED Driver Control */
  235. #define PM2XXX_LED_CURRENT_MASK 0x0C
  236. #define PM2XXX_LED_CURRENT_2_5MA (0X0<<2)
  237. #define PM2XXX_LED_CURRENT_1MA (0X1<<2)
  238. #define PM2XXX_LED_CURRENT_5MA (0X2<<2)
  239. #define PM2XXX_LED_CURRENT_10MA (0X3<<2)
  240. #define PM2XXX_LED_SELECT_MASK 0x02
  241. #define PM2XXX_LED_SELECT_EN (0X0<<1)
  242. #define PM2XXX_LED_SELECT_DIS (0X1<<1)
  243. #define PM2XXX_ANTI_OVERSHOOT_MASK 0x01
  244. #define PM2XXX_ANTI_OVERSHOOT_DIS 0X0
  245. #define PM2XXX_ANTI_OVERSHOOT_EN 0X1
  246. enum pm2xxx_reg_int1 {
  247. PM2XXX_INT1_ITVBATDISCONNECT = 0x02,
  248. PM2XXX_INT1_ITVBATLOWR = 0x04,
  249. PM2XXX_INT1_ITVBATLOWF = 0x08,
  250. };
  251. enum pm2xxx_mask_reg_int1 {
  252. PM2XXX_INT1_M_ITVBATDISCONNECT = 0x02,
  253. PM2XXX_INT1_M_ITVBATLOWR = 0x04,
  254. PM2XXX_INT1_M_ITVBATLOWF = 0x08,
  255. };
  256. enum pm2xxx_source_reg_int1 {
  257. PM2XXX_INT1_S_ITVBATDISCONNECT = 0x02,
  258. PM2XXX_INT1_S_ITVBATLOWR = 0x04,
  259. PM2XXX_INT1_S_ITVBATLOWF = 0x08,
  260. };
  261. enum pm2xxx_reg_int2 {
  262. PM2XXX_INT2_ITVPWR2PLUG = 0x01,
  263. PM2XXX_INT2_ITVPWR2UNPLUG = 0x02,
  264. PM2XXX_INT2_ITVPWR1PLUG = 0x04,
  265. PM2XXX_INT2_ITVPWR1UNPLUG = 0x08,
  266. };
  267. enum pm2xxx_mask_reg_int2 {
  268. PM2XXX_INT2_M_ITVPWR2PLUG = 0x01,
  269. PM2XXX_INT2_M_ITVPWR2UNPLUG = 0x02,
  270. PM2XXX_INT2_M_ITVPWR1PLUG = 0x04,
  271. PM2XXX_INT2_M_ITVPWR1UNPLUG = 0x08,
  272. };
  273. enum pm2xxx_source_reg_int2 {
  274. PM2XXX_INT2_S_ITVPWR2PLUG = 0x03,
  275. PM2XXX_INT2_S_ITVPWR1PLUG = 0x0c,
  276. };
  277. enum pm2xxx_reg_int3 {
  278. PM2XXX_INT3_ITCHPRECHARGEWD = 0x01,
  279. PM2XXX_INT3_ITCHCCWD = 0x02,
  280. PM2XXX_INT3_ITCHCVWD = 0x04,
  281. PM2XXX_INT3_ITAUTOTIMEOUTWD = 0x08,
  282. };
  283. enum pm2xxx_mask_reg_int3 {
  284. PM2XXX_INT3_M_ITCHPRECHARGEWD = 0x01,
  285. PM2XXX_INT3_M_ITCHCCWD = 0x02,
  286. PM2XXX_INT3_M_ITCHCVWD = 0x04,
  287. PM2XXX_INT3_M_ITAUTOTIMEOUTWD = 0x08,
  288. };
  289. enum pm2xxx_source_reg_int3 {
  290. PM2XXX_INT3_S_ITCHPRECHARGEWD = 0x01,
  291. PM2XXX_INT3_S_ITCHCCWD = 0x02,
  292. PM2XXX_INT3_S_ITCHCVWD = 0x04,
  293. PM2XXX_INT3_S_ITAUTOTIMEOUTWD = 0x08,
  294. };
  295. enum pm2xxx_reg_int4 {
  296. PM2XXX_INT4_ITBATTEMPCOLD = 0x01,
  297. PM2XXX_INT4_ITBATTEMPHOT = 0x02,
  298. PM2XXX_INT4_ITVPWR2OVV = 0x04,
  299. PM2XXX_INT4_ITVPWR1OVV = 0x08,
  300. PM2XXX_INT4_ITCHARGINGON = 0x10,
  301. PM2XXX_INT4_ITVRESUME = 0x20,
  302. PM2XXX_INT4_ITBATTFULL = 0x40,
  303. PM2XXX_INT4_ITCVPHASE = 0x80,
  304. };
  305. enum pm2xxx_mask_reg_int4 {
  306. PM2XXX_INT4_M_ITBATTEMPCOLD = 0x01,
  307. PM2XXX_INT4_M_ITBATTEMPHOT = 0x02,
  308. PM2XXX_INT4_M_ITVPWR2OVV = 0x04,
  309. PM2XXX_INT4_M_ITVPWR1OVV = 0x08,
  310. PM2XXX_INT4_M_ITCHARGINGON = 0x10,
  311. PM2XXX_INT4_M_ITVRESUME = 0x20,
  312. PM2XXX_INT4_M_ITBATTFULL = 0x40,
  313. PM2XXX_INT4_M_ITCVPHASE = 0x80,
  314. };
  315. enum pm2xxx_source_reg_int4 {
  316. PM2XXX_INT4_S_ITBATTEMPCOLD = 0x01,
  317. PM2XXX_INT4_S_ITBATTEMPHOT = 0x02,
  318. PM2XXX_INT4_S_ITVPWR2OVV = 0x04,
  319. PM2XXX_INT4_S_ITVPWR1OVV = 0x08,
  320. PM2XXX_INT4_S_ITCHARGINGON = 0x10,
  321. PM2XXX_INT4_S_ITVRESUME = 0x20,
  322. PM2XXX_INT4_S_ITBATTFULL = 0x40,
  323. PM2XXX_INT4_S_ITCVPHASE = 0x80,
  324. };
  325. enum pm2xxx_reg_int5 {
  326. PM2XXX_INT5_ITTHERMALSHUTDOWNRISE = 0x01,
  327. PM2XXX_INT5_ITTHERMALSHUTDOWNFALL = 0x02,
  328. PM2XXX_INT5_ITTHERMALWARNINGRISE = 0x04,
  329. PM2XXX_INT5_ITTHERMALWARNINGFALL = 0x08,
  330. PM2XXX_INT5_ITVSYSTEMOVV = 0x10,
  331. };
  332. enum pm2xxx_mask_reg_int5 {
  333. PM2XXX_INT5_M_ITTHERMALSHUTDOWNRISE = 0x01,
  334. PM2XXX_INT5_M_ITTHERMALSHUTDOWNFALL = 0x02,
  335. PM2XXX_INT5_M_ITTHERMALWARNINGRISE = 0x04,
  336. PM2XXX_INT5_M_ITTHERMALWARNINGFALL = 0x08,
  337. PM2XXX_INT5_M_ITVSYSTEMOVV = 0x10,
  338. };
  339. enum pm2xxx_source_reg_int5 {
  340. PM2XXX_INT5_S_ITTHERMALSHUTDOWNRISE = 0x01,
  341. PM2XXX_INT5_S_ITTHERMALSHUTDOWNFALL = 0x02,
  342. PM2XXX_INT5_S_ITTHERMALWARNINGRISE = 0x04,
  343. PM2XXX_INT5_S_ITTHERMALWARNINGFALL = 0x08,
  344. PM2XXX_INT5_S_ITVSYSTEMOVV = 0x10,
  345. };
  346. enum pm2xxx_reg_int6 {
  347. PM2XXX_INT6_ITVPWR2DROP = 0x01,
  348. PM2XXX_INT6_ITVPWR1DROP = 0x02,
  349. PM2XXX_INT6_ITVPWR2VALIDRISE = 0x04,
  350. PM2XXX_INT6_ITVPWR2VALIDFALL = 0x08,
  351. PM2XXX_INT6_ITVPWR1VALIDRISE = 0x10,
  352. PM2XXX_INT6_ITVPWR1VALIDFALL = 0x20,
  353. };
  354. enum pm2xxx_mask_reg_int6 {
  355. PM2XXX_INT6_M_ITVPWR2DROP = 0x01,
  356. PM2XXX_INT6_M_ITVPWR1DROP = 0x02,
  357. PM2XXX_INT6_M_ITVPWR2VALIDRISE = 0x04,
  358. PM2XXX_INT6_M_ITVPWR2VALIDFALL = 0x08,
  359. PM2XXX_INT6_M_ITVPWR1VALIDRISE = 0x10,
  360. PM2XXX_INT6_M_ITVPWR1VALIDFALL = 0x20,
  361. };
  362. enum pm2xxx_source_reg_int6 {
  363. PM2XXX_INT6_S_ITVPWR2DROP = 0x01,
  364. PM2XXX_INT6_S_ITVPWR1DROP = 0x02,
  365. PM2XXX_INT6_S_ITVPWR2VALIDRISE = 0x04,
  366. PM2XXX_INT6_S_ITVPWR2VALIDFALL = 0x08,
  367. PM2XXX_INT6_S_ITVPWR1VALIDRISE = 0x10,
  368. PM2XXX_INT6_S_ITVPWR1VALIDFALL = 0x20,
  369. };
  370. struct pm2xxx_charger_info {
  371. int charger_connected;
  372. int charger_online;
  373. int cv_active;
  374. bool wd_expired;
  375. };
  376. struct pm2xxx_charger_event_flags {
  377. bool mainextchnotok;
  378. bool main_thermal_prot;
  379. bool ovv;
  380. bool chgwdexp;
  381. };
  382. struct pm2xxx_interrupts {
  383. u8 reg[PM2XXX_NUM_INT_REG];
  384. int (*handler[PM2XXX_NUM_INT_REG])(void *, int);
  385. };
  386. struct pm2xxx_config {
  387. struct i2c_client *pm2xxx_i2c;
  388. struct i2c_device_id *pm2xxx_id;
  389. };
  390. struct pm2xxx_irq {
  391. char *name;
  392. irqreturn_t (*isr)(int irq, void *data);
  393. };
  394. struct pm2xxx_charger {
  395. struct device *dev;
  396. u8 chip_id;
  397. bool vddadc_en_ac;
  398. struct pm2xxx_config config;
  399. bool ac_conn;
  400. unsigned int gpio_irq;
  401. int vbat;
  402. int old_vbat;
  403. int failure_case;
  404. int failure_input_ovv;
  405. unsigned int lpn_pin;
  406. struct pm2xxx_interrupts *pm2_int;
  407. struct regulator *regu;
  408. struct pm2xxx_bm_data *bat;
  409. struct mutex lock;
  410. struct ab8500 *parent;
  411. struct pm2xxx_charger_info ac;
  412. struct pm2xxx_charger_platform_data *pdata;
  413. struct workqueue_struct *charger_wq;
  414. struct delayed_work check_vbat_work;
  415. struct work_struct ac_work;
  416. struct work_struct check_main_thermal_prot_work;
  417. struct delayed_work check_hw_failure_work;
  418. struct ux500_charger ac_chg;
  419. struct power_supply_desc ac_chg_desc;
  420. struct pm2xxx_charger_event_flags flags;
  421. };
  422. #endif /* PM2301_CHARGER_H */