oxnas-restart.c 8.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0)
  2. /*
  3. * oxnas SoC reset driver
  4. * based on:
  5. * Microsemi MIPS SoC reset driver
  6. * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
  7. *
  8. * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
  9. * Copyright (c) 2017 Microsemi Corporation
  10. * Copyright (c) 2020 Daniel Golle <daniel@makrotopia.org>
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/io.h>
  14. #include <linux/notifier.h>
  15. #include <linux/mfd/syscon.h>
  16. #include <linux/of_address.h>
  17. #include <linux/of_device.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reboot.h>
  20. #include <linux/regmap.h>
  21. /* bit numbers of reset control register */
  22. #define OX820_SYS_CTRL_RST_SCU 0
  23. #define OX820_SYS_CTRL_RST_COPRO 1
  24. #define OX820_SYS_CTRL_RST_ARM0 2
  25. #define OX820_SYS_CTRL_RST_ARM1 3
  26. #define OX820_SYS_CTRL_RST_USBHS 4
  27. #define OX820_SYS_CTRL_RST_USBHSPHYA 5
  28. #define OX820_SYS_CTRL_RST_MACA 6
  29. #define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA
  30. #define OX820_SYS_CTRL_RST_PCIEA 7
  31. #define OX820_SYS_CTRL_RST_SGDMA 8
  32. #define OX820_SYS_CTRL_RST_CIPHER 9
  33. #define OX820_SYS_CTRL_RST_DDR 10
  34. #define OX820_SYS_CTRL_RST_SATA 11
  35. #define OX820_SYS_CTRL_RST_SATA_LINK 12
  36. #define OX820_SYS_CTRL_RST_SATA_PHY 13
  37. #define OX820_SYS_CTRL_RST_PCIEPHY 14
  38. #define OX820_SYS_CTRL_RST_STATIC 15
  39. #define OX820_SYS_CTRL_RST_GPIO 16
  40. #define OX820_SYS_CTRL_RST_UART1 17
  41. #define OX820_SYS_CTRL_RST_UART2 18
  42. #define OX820_SYS_CTRL_RST_MISC 19
  43. #define OX820_SYS_CTRL_RST_I2S 20
  44. #define OX820_SYS_CTRL_RST_SD 21
  45. #define OX820_SYS_CTRL_RST_MACB 22
  46. #define OX820_SYS_CTRL_RST_PCIEB 23
  47. #define OX820_SYS_CTRL_RST_VIDEO 24
  48. #define OX820_SYS_CTRL_RST_DDR_PHY 25
  49. #define OX820_SYS_CTRL_RST_USBHSPHYB 26
  50. #define OX820_SYS_CTRL_RST_USBDEV 27
  51. #define OX820_SYS_CTRL_RST_ARMDBG 29
  52. #define OX820_SYS_CTRL_RST_PLLA 30
  53. #define OX820_SYS_CTRL_RST_PLLB 31
  54. /* bit numbers of clock control register */
  55. #define OX820_SYS_CTRL_CLK_COPRO 0
  56. #define OX820_SYS_CTRL_CLK_DMA 1
  57. #define OX820_SYS_CTRL_CLK_CIPHER 2
  58. #define OX820_SYS_CTRL_CLK_SD 3
  59. #define OX820_SYS_CTRL_CLK_SATA 4
  60. #define OX820_SYS_CTRL_CLK_I2S 5
  61. #define OX820_SYS_CTRL_CLK_USBHS 6
  62. #define OX820_SYS_CTRL_CLK_MACA 7
  63. #define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA
  64. #define OX820_SYS_CTRL_CLK_PCIEA 8
  65. #define OX820_SYS_CTRL_CLK_STATIC 9
  66. #define OX820_SYS_CTRL_CLK_MACB 10
  67. #define OX820_SYS_CTRL_CLK_PCIEB 11
  68. #define OX820_SYS_CTRL_CLK_REF600 12
  69. #define OX820_SYS_CTRL_CLK_USBDEV 13
  70. #define OX820_SYS_CTRL_CLK_DDR 14
  71. #define OX820_SYS_CTRL_CLK_DDRPHY 15
  72. #define OX820_SYS_CTRL_CLK_DDRCK 16
  73. /* Regmap offsets */
  74. #define OX820_CLK_SET_REGOFFSET 0x2c
  75. #define OX820_CLK_CLR_REGOFFSET 0x30
  76. #define OX820_RST_SET_REGOFFSET 0x34
  77. #define OX820_RST_CLR_REGOFFSET 0x38
  78. #define OX820_SECONDARY_SEL_REGOFFSET 0x14
  79. #define OX820_TERTIARY_SEL_REGOFFSET 0x8c
  80. #define OX820_QUATERNARY_SEL_REGOFFSET 0x94
  81. #define OX820_DEBUG_SEL_REGOFFSET 0x9c
  82. #define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4
  83. #define OX820_PULLUP_SEL_REGOFFSET 0xac
  84. #define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014
  85. #define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c
  86. #define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094
  87. #define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c
  88. #define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
  89. #define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac
  90. struct oxnas_restart_context {
  91. struct regmap *sys_ctrl;
  92. struct notifier_block restart_handler;
  93. };
  94. static int ox820_restart_handle(struct notifier_block *this,
  95. unsigned long mode, void *cmd)
  96. {
  97. struct oxnas_restart_context *ctx = container_of(this, struct
  98. oxnas_restart_context,
  99. restart_handler);
  100. u32 value;
  101. /*
  102. * Assert reset to cores as per power on defaults
  103. * Don't touch the DDR interface as things will come to an impromptu
  104. * stop NB Possibly should be asserting reset for PLLB, but there are
  105. * timing concerns here according to the docs
  106. */
  107. value = BIT(OX820_SYS_CTRL_RST_COPRO) |
  108. BIT(OX820_SYS_CTRL_RST_USBHS) |
  109. BIT(OX820_SYS_CTRL_RST_USBHSPHYA) |
  110. BIT(OX820_SYS_CTRL_RST_MACA) |
  111. BIT(OX820_SYS_CTRL_RST_PCIEA) |
  112. BIT(OX820_SYS_CTRL_RST_SGDMA) |
  113. BIT(OX820_SYS_CTRL_RST_CIPHER) |
  114. BIT(OX820_SYS_CTRL_RST_SATA) |
  115. BIT(OX820_SYS_CTRL_RST_SATA_LINK) |
  116. BIT(OX820_SYS_CTRL_RST_SATA_PHY) |
  117. BIT(OX820_SYS_CTRL_RST_PCIEPHY) |
  118. BIT(OX820_SYS_CTRL_RST_STATIC) |
  119. BIT(OX820_SYS_CTRL_RST_UART1) |
  120. BIT(OX820_SYS_CTRL_RST_UART2) |
  121. BIT(OX820_SYS_CTRL_RST_MISC) |
  122. BIT(OX820_SYS_CTRL_RST_I2S) |
  123. BIT(OX820_SYS_CTRL_RST_SD) |
  124. BIT(OX820_SYS_CTRL_RST_MACB) |
  125. BIT(OX820_SYS_CTRL_RST_PCIEB) |
  126. BIT(OX820_SYS_CTRL_RST_VIDEO) |
  127. BIT(OX820_SYS_CTRL_RST_USBHSPHYB) |
  128. BIT(OX820_SYS_CTRL_RST_USBDEV);
  129. regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
  130. /* Release reset to cores as per power on defaults */
  131. regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET,
  132. BIT(OX820_SYS_CTRL_RST_GPIO));
  133. /*
  134. * Disable clocks to cores as per power-on defaults - must leave DDR
  135. * related clocks enabled otherwise we'll stop rather abruptly.
  136. */
  137. value = BIT(OX820_SYS_CTRL_CLK_COPRO) |
  138. BIT(OX820_SYS_CTRL_CLK_DMA) |
  139. BIT(OX820_SYS_CTRL_CLK_CIPHER) |
  140. BIT(OX820_SYS_CTRL_CLK_SD) |
  141. BIT(OX820_SYS_CTRL_CLK_SATA) |
  142. BIT(OX820_SYS_CTRL_CLK_I2S) |
  143. BIT(OX820_SYS_CTRL_CLK_USBHS) |
  144. BIT(OX820_SYS_CTRL_CLK_MAC) |
  145. BIT(OX820_SYS_CTRL_CLK_PCIEA) |
  146. BIT(OX820_SYS_CTRL_CLK_STATIC) |
  147. BIT(OX820_SYS_CTRL_CLK_MACB) |
  148. BIT(OX820_SYS_CTRL_CLK_PCIEB) |
  149. BIT(OX820_SYS_CTRL_CLK_REF600) |
  150. BIT(OX820_SYS_CTRL_CLK_USBDEV);
  151. regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);
  152. /* Enable clocks to cores as per power-on defaults */
  153. /* Set sys-control pin mux'ing as per power-on defaults */
  154. regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);
  155. regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);
  156. regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);
  157. regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);
  158. regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);
  159. regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);
  160. regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);
  161. regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);
  162. regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);
  163. regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);
  164. regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
  165. regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);
  166. /*
  167. * No need to save any state, as the ROM loader can determine whether
  168. * reset is due to power cycling or programatic action, just hit the
  169. * (self-clearing) CPU reset bit of the block reset register
  170. */
  171. value =
  172. BIT(OX820_SYS_CTRL_RST_SCU) |
  173. BIT(OX820_SYS_CTRL_RST_ARM0) |
  174. BIT(OX820_SYS_CTRL_RST_ARM1);
  175. regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
  176. pr_emerg("Unable to restart system\n");
  177. return NOTIFY_DONE;
  178. }
  179. static int ox820_restart_probe(struct platform_device *pdev)
  180. {
  181. struct oxnas_restart_context *ctx;
  182. struct regmap *sys_ctrl;
  183. struct device *dev = &pdev->dev;
  184. int err = 0;
  185. sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);
  186. if (IS_ERR(sys_ctrl))
  187. return PTR_ERR(sys_ctrl);
  188. ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
  189. if (!ctx)
  190. return -ENOMEM;
  191. ctx->sys_ctrl = sys_ctrl;
  192. ctx->restart_handler.notifier_call = ox820_restart_handle;
  193. ctx->restart_handler.priority = 192;
  194. err = register_restart_handler(&ctx->restart_handler);
  195. if (err)
  196. dev_err(dev, "can't register restart notifier (err=%d)\n", err);
  197. return err;
  198. }
  199. static const struct of_device_id ox820_restart_of_match[] = {
  200. { .compatible = "oxsemi,ox820-sys-ctrl" },
  201. {}
  202. };
  203. static struct platform_driver ox820_restart_driver = {
  204. .probe = ox820_restart_probe,
  205. .driver = {
  206. .name = "ox820-chip-reset",
  207. .of_match_table = ox820_restart_of_match,
  208. },
  209. };
  210. builtin_platform_driver(ox820_restart_driver);