ocelot-reset.c 3.3 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi MIPS SoC reset driver
  4. *
  5. * License: Dual MIT/GPL
  6. * Copyright (c) 2017 Microsemi Corporation
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/io.h>
  10. #include <linux/notifier.h>
  11. #include <linux/mfd/syscon.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reboot.h>
  16. #include <linux/regmap.h>
  17. struct reset_props {
  18. const char *syscon;
  19. u32 protect_reg;
  20. u32 vcore_protect;
  21. u32 if_si_owner_bit;
  22. };
  23. struct ocelot_reset_context {
  24. void __iomem *base;
  25. struct regmap *cpu_ctrl;
  26. const struct reset_props *props;
  27. struct notifier_block restart_handler;
  28. };
  29. #define SOFT_CHIP_RST BIT(0)
  30. #define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
  31. #define IF_SI_OWNER_MASK GENMASK(1, 0)
  32. #define IF_SI_OWNER_SISL 0
  33. #define IF_SI_OWNER_SIBM 1
  34. #define IF_SI_OWNER_SIMC 2
  35. static int ocelot_restart_handle(struct notifier_block *this,
  36. unsigned long mode, void *cmd)
  37. {
  38. struct ocelot_reset_context *ctx = container_of(this, struct
  39. ocelot_reset_context,
  40. restart_handler);
  41. u32 if_si_owner_bit = ctx->props->if_si_owner_bit;
  42. /* Make sure the core is not protected from reset */
  43. regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
  44. ctx->props->vcore_protect, 0);
  45. /* Make the SI back to boot mode */
  46. regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
  47. IF_SI_OWNER_MASK << if_si_owner_bit,
  48. IF_SI_OWNER_SIBM << if_si_owner_bit);
  49. pr_emerg("Resetting SoC\n");
  50. writel(SOFT_CHIP_RST, ctx->base);
  51. pr_emerg("Unable to restart system\n");
  52. return NOTIFY_DONE;
  53. }
  54. static int ocelot_reset_probe(struct platform_device *pdev)
  55. {
  56. struct ocelot_reset_context *ctx;
  57. struct resource *res;
  58. struct device *dev = &pdev->dev;
  59. int err;
  60. ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
  61. if (!ctx)
  62. return -ENOMEM;
  63. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  64. ctx->base = devm_ioremap_resource(dev, res);
  65. if (IS_ERR(ctx->base))
  66. return PTR_ERR(ctx->base);
  67. ctx->props = device_get_match_data(dev);
  68. ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon);
  69. if (IS_ERR(ctx->cpu_ctrl)) {
  70. dev_err(dev, "No syscon map: %s\n", ctx->props->syscon);
  71. return PTR_ERR(ctx->cpu_ctrl);
  72. }
  73. ctx->restart_handler.notifier_call = ocelot_restart_handle;
  74. ctx->restart_handler.priority = 192;
  75. err = register_restart_handler(&ctx->restart_handler);
  76. if (err)
  77. dev_err(dev, "can't register restart notifier (err=%d)\n", err);
  78. return err;
  79. }
  80. static const struct reset_props reset_props_ocelot = {
  81. .syscon = "mscc,ocelot-cpu-syscon",
  82. .protect_reg = 0x20,
  83. .vcore_protect = BIT(2),
  84. .if_si_owner_bit = 4,
  85. };
  86. static const struct reset_props reset_props_sparx5 = {
  87. .syscon = "microchip,sparx5-cpu-syscon",
  88. .protect_reg = 0x84,
  89. .vcore_protect = BIT(10),
  90. .if_si_owner_bit = 6,
  91. };
  92. static const struct of_device_id ocelot_reset_of_match[] = {
  93. {
  94. .compatible = "mscc,ocelot-chip-reset",
  95. .data = &reset_props_ocelot
  96. }, {
  97. .compatible = "microchip,sparx5-chip-reset",
  98. .data = &reset_props_sparx5
  99. },
  100. { /*sentinel*/ }
  101. };
  102. static struct platform_driver ocelot_reset_driver = {
  103. .probe = ocelot_reset_probe,
  104. .driver = {
  105. .name = "ocelot-chip-reset",
  106. .of_match_table = ocelot_reset_of_match,
  107. },
  108. };
  109. builtin_platform_driver(ocelot_reset_driver);