at91-sama5d2_shdwc.c 10 KB

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  1. /*
  2. * Atmel SAMA5D2-Compatible Shutdown Controller (SHDWC) driver.
  3. * Found on some SoCs as the sama5d2 (obviously).
  4. *
  5. * Copyright (C) 2015 Atmel Corporation,
  6. * Nicolas Ferre <nicolas.ferre@atmel.com>
  7. *
  8. * Evolved from driver at91-poweroff.c.
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. *
  14. * TODO:
  15. * - addition to status of other wake-up inputs [1 - 15]
  16. * - Analog Comparator wake-up alarm
  17. * - Serial RX wake-up alarm
  18. * - low power debouncer
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/clk/at91_pmc.h>
  22. #include <linux/io.h>
  23. #include <linux/module.h>
  24. #include <linux/of.h>
  25. #include <linux/of_address.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/printk.h>
  28. #include <soc/at91/at91sam9_ddrsdr.h>
  29. #define SLOW_CLOCK_FREQ 32768
  30. #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
  31. #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */
  32. #define AT91_SHDW_KEY (0xa5UL << 24) /* KEY Password */
  33. #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
  34. #define AT91_SHDW_WKUPDBC_SHIFT 24
  35. #define AT91_SHDW_WKUPDBC_MASK GENMASK(26, 24)
  36. #define AT91_SHDW_WKUPDBC(x) (((x) << AT91_SHDW_WKUPDBC_SHIFT) \
  37. & AT91_SHDW_WKUPDBC_MASK)
  38. #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
  39. #define AT91_SHDW_WKUPIS_SHIFT 16
  40. #define AT91_SHDW_WKUPIS_MASK GENMASK(31, 16)
  41. #define AT91_SHDW_WKUPIS(x) ((1 << (x)) << AT91_SHDW_WKUPIS_SHIFT \
  42. & AT91_SHDW_WKUPIS_MASK)
  43. #define AT91_SHDW_WUIR 0x0c /* Shutdown Wake-up Inputs Register */
  44. #define AT91_SHDW_WKUPEN_MASK GENMASK(15, 0)
  45. #define AT91_SHDW_WKUPEN(x) ((1 << (x)) & AT91_SHDW_WKUPEN_MASK)
  46. #define AT91_SHDW_WKUPT_SHIFT 16
  47. #define AT91_SHDW_WKUPT_MASK GENMASK(31, 16)
  48. #define AT91_SHDW_WKUPT(x) ((1 << (x)) << AT91_SHDW_WKUPT_SHIFT \
  49. & AT91_SHDW_WKUPT_MASK)
  50. #define SHDW_WK_PIN(reg, cfg) ((reg) & AT91_SHDW_WKUPIS((cfg)->wkup_pin_input))
  51. #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1)
  52. #define SHDW_RTTWK(reg, cfg) (((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1)
  53. #define SHDW_RTCWKEN(cfg) (1 << ((cfg)->mr_rtcwk_shift))
  54. #define SHDW_RTTWKEN(cfg) (1 << ((cfg)->mr_rttwk_shift))
  55. #define DBC_PERIOD_US(x) DIV_ROUND_UP_ULL((1000000 * (x)), \
  56. SLOW_CLOCK_FREQ)
  57. #define SHDW_CFG_NOT_USED (32)
  58. struct shdwc_reg_config {
  59. u8 wkup_pin_input;
  60. u8 mr_rtcwk_shift;
  61. u8 mr_rttwk_shift;
  62. u8 sr_rtcwk_shift;
  63. u8 sr_rttwk_shift;
  64. };
  65. struct pmc_reg_config {
  66. u8 mckr;
  67. };
  68. struct reg_config {
  69. struct shdwc_reg_config shdwc;
  70. struct pmc_reg_config pmc;
  71. };
  72. struct shdwc {
  73. const struct reg_config *rcfg;
  74. struct clk *sclk;
  75. void __iomem *shdwc_base;
  76. void __iomem *mpddrc_base;
  77. void __iomem *pmc_base;
  78. };
  79. /*
  80. * Hold configuration here, cannot be more than one instance of the driver
  81. * since pm_power_off itself is global.
  82. */
  83. static struct shdwc *at91_shdwc;
  84. static const unsigned long long sdwc_dbc_period[] = {
  85. 0, 3, 32, 512, 4096, 32768,
  86. };
  87. static void __init at91_wakeup_status(struct platform_device *pdev)
  88. {
  89. struct shdwc *shdw = platform_get_drvdata(pdev);
  90. const struct reg_config *rcfg = shdw->rcfg;
  91. u32 reg;
  92. char *reason = "unknown";
  93. reg = readl(shdw->shdwc_base + AT91_SHDW_SR);
  94. dev_dbg(&pdev->dev, "%s: status = %#x\n", __func__, reg);
  95. /* Simple power-on, just bail out */
  96. if (!reg)
  97. return;
  98. if (SHDW_WK_PIN(reg, &rcfg->shdwc))
  99. reason = "WKUP pin";
  100. else if (SHDW_RTCWK(reg, &rcfg->shdwc))
  101. reason = "RTC";
  102. else if (SHDW_RTTWK(reg, &rcfg->shdwc))
  103. reason = "RTT";
  104. pr_info("AT91: Wake-Up source: %s\n", reason);
  105. }
  106. static void at91_poweroff(void)
  107. {
  108. asm volatile(
  109. /* Align to cache lines */
  110. ".balign 32\n\t"
  111. /* Ensure AT91_SHDW_CR is in the TLB by reading it */
  112. " ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  113. /* Power down SDRAM0 */
  114. " tst %0, #0\n\t"
  115. " beq 1f\n\t"
  116. " str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
  117. /* Switch the master clock source to slow clock. */
  118. "1: ldr r6, [%4, %5]\n\t"
  119. " bic r6, r6, #" __stringify(AT91_PMC_CSS) "\n\t"
  120. " str r6, [%4, %5]\n\t"
  121. /* Wait for clock switch. */
  122. "2: ldr r6, [%4, #" __stringify(AT91_PMC_SR) "]\n\t"
  123. " tst r6, #" __stringify(AT91_PMC_MCKRDY) "\n\t"
  124. " beq 2b\n\t"
  125. /* Shutdown CPU */
  126. " str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  127. " b .\n\t"
  128. :
  129. : "r" (at91_shdwc->mpddrc_base),
  130. "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
  131. "r" (at91_shdwc->shdwc_base),
  132. "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW),
  133. "r" (at91_shdwc->pmc_base),
  134. "r" (at91_shdwc->rcfg->pmc.mckr)
  135. : "r6");
  136. }
  137. static u32 at91_shdwc_debouncer_value(struct platform_device *pdev,
  138. u32 in_period_us)
  139. {
  140. int i;
  141. int max_idx = ARRAY_SIZE(sdwc_dbc_period) - 1;
  142. unsigned long long period_us;
  143. unsigned long long max_period_us = DBC_PERIOD_US(sdwc_dbc_period[max_idx]);
  144. if (in_period_us > max_period_us) {
  145. dev_warn(&pdev->dev,
  146. "debouncer period %u too big, reduced to %llu us\n",
  147. in_period_us, max_period_us);
  148. return max_idx;
  149. }
  150. for (i = max_idx - 1; i > 0; i--) {
  151. period_us = DBC_PERIOD_US(sdwc_dbc_period[i]);
  152. dev_dbg(&pdev->dev, "%s: ref[%d] = %llu\n",
  153. __func__, i, period_us);
  154. if (in_period_us > period_us)
  155. break;
  156. }
  157. return i + 1;
  158. }
  159. static u32 at91_shdwc_get_wakeup_input(struct platform_device *pdev,
  160. struct device_node *np)
  161. {
  162. struct device_node *cnp;
  163. u32 wk_input_mask;
  164. u32 wuir = 0;
  165. u32 wk_input;
  166. for_each_child_of_node(np, cnp) {
  167. if (of_property_read_u32(cnp, "reg", &wk_input)) {
  168. dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
  169. cnp);
  170. continue;
  171. }
  172. wk_input_mask = 1 << wk_input;
  173. if (!(wk_input_mask & AT91_SHDW_WKUPEN_MASK)) {
  174. dev_warn(&pdev->dev,
  175. "wake-up input %d out of bounds ignore\n",
  176. wk_input);
  177. continue;
  178. }
  179. wuir |= wk_input_mask;
  180. if (of_property_read_bool(cnp, "atmel,wakeup-active-high"))
  181. wuir |= AT91_SHDW_WKUPT(wk_input);
  182. dev_dbg(&pdev->dev, "%s: (child %d) wuir = %#x\n",
  183. __func__, wk_input, wuir);
  184. }
  185. return wuir;
  186. }
  187. static void at91_shdwc_dt_configure(struct platform_device *pdev)
  188. {
  189. struct shdwc *shdw = platform_get_drvdata(pdev);
  190. const struct reg_config *rcfg = shdw->rcfg;
  191. struct device_node *np = pdev->dev.of_node;
  192. u32 mode = 0, tmp, input;
  193. if (!np) {
  194. dev_err(&pdev->dev, "device node not found\n");
  195. return;
  196. }
  197. if (!of_property_read_u32(np, "debounce-delay-us", &tmp))
  198. mode |= AT91_SHDW_WKUPDBC(at91_shdwc_debouncer_value(pdev, tmp));
  199. if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
  200. mode |= SHDW_RTCWKEN(&rcfg->shdwc);
  201. if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
  202. mode |= SHDW_RTTWKEN(&rcfg->shdwc);
  203. dev_dbg(&pdev->dev, "%s: mode = %#x\n", __func__, mode);
  204. writel(mode, shdw->shdwc_base + AT91_SHDW_MR);
  205. input = at91_shdwc_get_wakeup_input(pdev, np);
  206. writel(input, shdw->shdwc_base + AT91_SHDW_WUIR);
  207. }
  208. static const struct reg_config sama5d2_reg_config = {
  209. .shdwc = {
  210. .wkup_pin_input = 0,
  211. .mr_rtcwk_shift = 17,
  212. .mr_rttwk_shift = SHDW_CFG_NOT_USED,
  213. .sr_rtcwk_shift = 5,
  214. .sr_rttwk_shift = SHDW_CFG_NOT_USED,
  215. },
  216. .pmc = {
  217. .mckr = 0x30,
  218. },
  219. };
  220. static const struct reg_config sam9x60_reg_config = {
  221. .shdwc = {
  222. .wkup_pin_input = 0,
  223. .mr_rtcwk_shift = 17,
  224. .mr_rttwk_shift = 16,
  225. .sr_rtcwk_shift = 5,
  226. .sr_rttwk_shift = 4,
  227. },
  228. .pmc = {
  229. .mckr = 0x28,
  230. },
  231. };
  232. static const struct of_device_id at91_shdwc_of_match[] = {
  233. {
  234. .compatible = "atmel,sama5d2-shdwc",
  235. .data = &sama5d2_reg_config,
  236. },
  237. {
  238. .compatible = "microchip,sam9x60-shdwc",
  239. .data = &sam9x60_reg_config,
  240. }, {
  241. /*sentinel*/
  242. }
  243. };
  244. MODULE_DEVICE_TABLE(of, at91_shdwc_of_match);
  245. static const struct of_device_id at91_pmc_ids[] = {
  246. { .compatible = "atmel,sama5d2-pmc" },
  247. { .compatible = "microchip,sam9x60-pmc" },
  248. { /* Sentinel. */ }
  249. };
  250. static int __init at91_shdwc_probe(struct platform_device *pdev)
  251. {
  252. struct resource *res;
  253. const struct of_device_id *match;
  254. struct device_node *np;
  255. u32 ddr_type;
  256. int ret;
  257. if (!pdev->dev.of_node)
  258. return -ENODEV;
  259. if (at91_shdwc)
  260. return -EBUSY;
  261. at91_shdwc = devm_kzalloc(&pdev->dev, sizeof(*at91_shdwc), GFP_KERNEL);
  262. if (!at91_shdwc)
  263. return -ENOMEM;
  264. platform_set_drvdata(pdev, at91_shdwc);
  265. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  266. at91_shdwc->shdwc_base = devm_ioremap_resource(&pdev->dev, res);
  267. if (IS_ERR(at91_shdwc->shdwc_base)) {
  268. dev_err(&pdev->dev, "Could not map reset controller address\n");
  269. return PTR_ERR(at91_shdwc->shdwc_base);
  270. }
  271. match = of_match_node(at91_shdwc_of_match, pdev->dev.of_node);
  272. at91_shdwc->rcfg = match->data;
  273. at91_shdwc->sclk = devm_clk_get(&pdev->dev, NULL);
  274. if (IS_ERR(at91_shdwc->sclk))
  275. return PTR_ERR(at91_shdwc->sclk);
  276. ret = clk_prepare_enable(at91_shdwc->sclk);
  277. if (ret) {
  278. dev_err(&pdev->dev, "Could not enable slow clock\n");
  279. return ret;
  280. }
  281. at91_wakeup_status(pdev);
  282. at91_shdwc_dt_configure(pdev);
  283. np = of_find_matching_node(NULL, at91_pmc_ids);
  284. if (!np) {
  285. ret = -ENODEV;
  286. goto clk_disable;
  287. }
  288. at91_shdwc->pmc_base = of_iomap(np, 0);
  289. of_node_put(np);
  290. if (!at91_shdwc->pmc_base) {
  291. ret = -ENOMEM;
  292. goto clk_disable;
  293. }
  294. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
  295. if (!np) {
  296. ret = -ENODEV;
  297. goto unmap;
  298. }
  299. at91_shdwc->mpddrc_base = of_iomap(np, 0);
  300. of_node_put(np);
  301. if (!at91_shdwc->mpddrc_base) {
  302. ret = -ENOMEM;
  303. goto unmap;
  304. }
  305. pm_power_off = at91_poweroff;
  306. ddr_type = readl(at91_shdwc->mpddrc_base + AT91_DDRSDRC_MDR) &
  307. AT91_DDRSDRC_MD;
  308. if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
  309. ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
  310. iounmap(at91_shdwc->mpddrc_base);
  311. at91_shdwc->mpddrc_base = NULL;
  312. }
  313. return 0;
  314. unmap:
  315. iounmap(at91_shdwc->pmc_base);
  316. clk_disable:
  317. clk_disable_unprepare(at91_shdwc->sclk);
  318. return ret;
  319. }
  320. static int __exit at91_shdwc_remove(struct platform_device *pdev)
  321. {
  322. struct shdwc *shdw = platform_get_drvdata(pdev);
  323. if (pm_power_off == at91_poweroff)
  324. pm_power_off = NULL;
  325. /* Reset values to disable wake-up features */
  326. writel(0, shdw->shdwc_base + AT91_SHDW_MR);
  327. writel(0, shdw->shdwc_base + AT91_SHDW_WUIR);
  328. if (shdw->mpddrc_base)
  329. iounmap(shdw->mpddrc_base);
  330. iounmap(shdw->pmc_base);
  331. clk_disable_unprepare(shdw->sclk);
  332. return 0;
  333. }
  334. static struct platform_driver at91_shdwc_driver = {
  335. .remove = __exit_p(at91_shdwc_remove),
  336. .driver = {
  337. .name = "at91-shdwc",
  338. .of_match_table = at91_shdwc_of_match,
  339. },
  340. };
  341. module_platform_driver_probe(at91_shdwc_driver, at91_shdwc_probe);
  342. MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
  343. MODULE_DESCRIPTION("Atmel shutdown controller driver");
  344. MODULE_LICENSE("GPL v2");