pmc_atom.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel Atom SOC Power Management Controller Driver
  4. * Copyright (c) 2014, Intel Corporation.
  5. */
  6. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  7. #include <linux/debugfs.h>
  8. #include <linux/device.h>
  9. #include <linux/dmi.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/platform_data/x86/clk-pmc-atom.h>
  13. #include <linux/platform_data/x86/pmc_atom.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pci.h>
  16. #include <linux/seq_file.h>
  17. struct pmc_bit_map {
  18. const char *name;
  19. u32 bit_mask;
  20. };
  21. struct pmc_reg_map {
  22. const struct pmc_bit_map *d3_sts_0;
  23. const struct pmc_bit_map *d3_sts_1;
  24. const struct pmc_bit_map *func_dis;
  25. const struct pmc_bit_map *func_dis_2;
  26. const struct pmc_bit_map *pss;
  27. };
  28. struct pmc_data {
  29. const struct pmc_reg_map *map;
  30. const struct pmc_clk *clks;
  31. };
  32. struct pmc_dev {
  33. u32 base_addr;
  34. void __iomem *regmap;
  35. const struct pmc_reg_map *map;
  36. #ifdef CONFIG_DEBUG_FS
  37. struct dentry *dbgfs_dir;
  38. #endif /* CONFIG_DEBUG_FS */
  39. bool init;
  40. };
  41. static struct pmc_dev pmc_device;
  42. static u32 acpi_base_addr;
  43. static const struct pmc_clk byt_clks[] = {
  44. {
  45. .name = "xtal",
  46. .freq = 25000000,
  47. .parent_name = NULL,
  48. },
  49. {
  50. .name = "pll",
  51. .freq = 19200000,
  52. .parent_name = "xtal",
  53. },
  54. {},
  55. };
  56. static const struct pmc_clk cht_clks[] = {
  57. {
  58. .name = "xtal",
  59. .freq = 19200000,
  60. .parent_name = NULL,
  61. },
  62. {},
  63. };
  64. static const struct pmc_bit_map d3_sts_0_map[] = {
  65. {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
  66. {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
  67. {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
  68. {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
  69. {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
  70. {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
  71. {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
  72. {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
  73. {"SCC_EMMC", BIT_SCC_EMMC},
  74. {"SCC_SDIO", BIT_SCC_SDIO},
  75. {"SCC_SDCARD", BIT_SCC_SDCARD},
  76. {"SCC_MIPI", BIT_SCC_MIPI},
  77. {"HDA", BIT_HDA},
  78. {"LPE", BIT_LPE},
  79. {"OTG", BIT_OTG},
  80. {"USH", BIT_USH},
  81. {"GBE", BIT_GBE},
  82. {"SATA", BIT_SATA},
  83. {"USB_EHCI", BIT_USB_EHCI},
  84. {"SEC", BIT_SEC},
  85. {"PCIE_PORT0", BIT_PCIE_PORT0},
  86. {"PCIE_PORT1", BIT_PCIE_PORT1},
  87. {"PCIE_PORT2", BIT_PCIE_PORT2},
  88. {"PCIE_PORT3", BIT_PCIE_PORT3},
  89. {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
  90. {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
  91. {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
  92. {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
  93. {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
  94. {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
  95. {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
  96. {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
  97. {},
  98. };
  99. static struct pmc_bit_map byt_d3_sts_1_map[] = {
  100. {"SMB", BIT_SMB},
  101. {"OTG_SS_PHY", BIT_OTG_SS_PHY},
  102. {"USH_SS_PHY", BIT_USH_SS_PHY},
  103. {"DFX", BIT_DFX},
  104. {},
  105. };
  106. static struct pmc_bit_map cht_d3_sts_1_map[] = {
  107. {"SMB", BIT_SMB},
  108. {"GMM", BIT_STS_GMM},
  109. {"ISH", BIT_STS_ISH},
  110. {},
  111. };
  112. static struct pmc_bit_map cht_func_dis_2_map[] = {
  113. {"SMB", BIT_SMB},
  114. {"GMM", BIT_FD_GMM},
  115. {"ISH", BIT_FD_ISH},
  116. {},
  117. };
  118. static const struct pmc_bit_map byt_pss_map[] = {
  119. {"GBE", PMC_PSS_BIT_GBE},
  120. {"SATA", PMC_PSS_BIT_SATA},
  121. {"HDA", PMC_PSS_BIT_HDA},
  122. {"SEC", PMC_PSS_BIT_SEC},
  123. {"PCIE", PMC_PSS_BIT_PCIE},
  124. {"LPSS", PMC_PSS_BIT_LPSS},
  125. {"LPE", PMC_PSS_BIT_LPE},
  126. {"DFX", PMC_PSS_BIT_DFX},
  127. {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
  128. {"USH_SUS", PMC_PSS_BIT_USH_SUS},
  129. {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
  130. {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
  131. {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
  132. {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
  133. {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
  134. {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
  135. {"USB", PMC_PSS_BIT_USB},
  136. {"USB_SUS", PMC_PSS_BIT_USB_SUS},
  137. {},
  138. };
  139. static const struct pmc_bit_map cht_pss_map[] = {
  140. {"SATA", PMC_PSS_BIT_SATA},
  141. {"HDA", PMC_PSS_BIT_HDA},
  142. {"SEC", PMC_PSS_BIT_SEC},
  143. {"PCIE", PMC_PSS_BIT_PCIE},
  144. {"LPSS", PMC_PSS_BIT_LPSS},
  145. {"LPE", PMC_PSS_BIT_LPE},
  146. {"UFS", PMC_PSS_BIT_CHT_UFS},
  147. {"UXD", PMC_PSS_BIT_CHT_UXD},
  148. {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
  149. {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
  150. {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
  151. {"GMM", PMC_PSS_BIT_CHT_GMM},
  152. {"ISH", PMC_PSS_BIT_CHT_ISH},
  153. {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
  154. {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
  155. {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
  156. {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
  157. {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
  158. {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
  159. {},
  160. };
  161. static const struct pmc_reg_map byt_reg_map = {
  162. .d3_sts_0 = d3_sts_0_map,
  163. .d3_sts_1 = byt_d3_sts_1_map,
  164. .func_dis = d3_sts_0_map,
  165. .func_dis_2 = byt_d3_sts_1_map,
  166. .pss = byt_pss_map,
  167. };
  168. static const struct pmc_reg_map cht_reg_map = {
  169. .d3_sts_0 = d3_sts_0_map,
  170. .d3_sts_1 = cht_d3_sts_1_map,
  171. .func_dis = d3_sts_0_map,
  172. .func_dis_2 = cht_func_dis_2_map,
  173. .pss = cht_pss_map,
  174. };
  175. static const struct pmc_data byt_data = {
  176. .map = &byt_reg_map,
  177. .clks = byt_clks,
  178. };
  179. static const struct pmc_data cht_data = {
  180. .map = &cht_reg_map,
  181. .clks = cht_clks,
  182. };
  183. static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
  184. {
  185. return readl(pmc->regmap + reg_offset);
  186. }
  187. static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
  188. {
  189. writel(val, pmc->regmap + reg_offset);
  190. }
  191. int pmc_atom_read(int offset, u32 *value)
  192. {
  193. struct pmc_dev *pmc = &pmc_device;
  194. if (!pmc->init)
  195. return -ENODEV;
  196. *value = pmc_reg_read(pmc, offset);
  197. return 0;
  198. }
  199. EXPORT_SYMBOL_GPL(pmc_atom_read);
  200. int pmc_atom_write(int offset, u32 value)
  201. {
  202. struct pmc_dev *pmc = &pmc_device;
  203. if (!pmc->init)
  204. return -ENODEV;
  205. pmc_reg_write(pmc, offset, value);
  206. return 0;
  207. }
  208. EXPORT_SYMBOL_GPL(pmc_atom_write);
  209. static void pmc_power_off(void)
  210. {
  211. u16 pm1_cnt_port;
  212. u32 pm1_cnt_value;
  213. pr_info("Preparing to enter system sleep state S5\n");
  214. pm1_cnt_port = acpi_base_addr + PM1_CNT;
  215. pm1_cnt_value = inl(pm1_cnt_port);
  216. pm1_cnt_value &= SLEEP_TYPE_MASK;
  217. pm1_cnt_value |= SLEEP_TYPE_S5;
  218. pm1_cnt_value |= SLEEP_ENABLE;
  219. outl(pm1_cnt_value, pm1_cnt_port);
  220. }
  221. static void pmc_hw_reg_setup(struct pmc_dev *pmc)
  222. {
  223. /*
  224. * Disable PMC S0IX_WAKE_EN events coming from:
  225. * - LPC clock run
  226. * - GPIO_SUS ored dedicated IRQs
  227. * - GPIO_SCORE ored dedicated IRQs
  228. * - GPIO_SUS shared IRQ
  229. * - GPIO_SCORE shared IRQ
  230. */
  231. pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
  232. }
  233. #ifdef CONFIG_DEBUG_FS
  234. static void pmc_dev_state_print(struct seq_file *s, int reg_index,
  235. u32 sts, const struct pmc_bit_map *sts_map,
  236. u32 fd, const struct pmc_bit_map *fd_map)
  237. {
  238. int offset = PMC_REG_BIT_WIDTH * reg_index;
  239. int index;
  240. for (index = 0; sts_map[index].name; index++) {
  241. seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
  242. offset + index, sts_map[index].name,
  243. fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
  244. sts_map[index].bit_mask & sts ? "D3" : "D0");
  245. }
  246. }
  247. static int pmc_dev_state_show(struct seq_file *s, void *unused)
  248. {
  249. struct pmc_dev *pmc = s->private;
  250. const struct pmc_reg_map *m = pmc->map;
  251. u32 func_dis, func_dis_2;
  252. u32 d3_sts_0, d3_sts_1;
  253. func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
  254. func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
  255. d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
  256. d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
  257. /* Low part */
  258. pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
  259. /* High part */
  260. pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
  261. return 0;
  262. }
  263. DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
  264. static int pmc_pss_state_show(struct seq_file *s, void *unused)
  265. {
  266. struct pmc_dev *pmc = s->private;
  267. const struct pmc_bit_map *map = pmc->map->pss;
  268. u32 pss = pmc_reg_read(pmc, PMC_PSS);
  269. int index;
  270. for (index = 0; map[index].name; index++) {
  271. seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
  272. index, map[index].name,
  273. map[index].bit_mask & pss ? "Off" : "On");
  274. }
  275. return 0;
  276. }
  277. DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
  278. static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
  279. {
  280. struct pmc_dev *pmc = s->private;
  281. u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
  282. s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
  283. s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
  284. s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
  285. s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
  286. s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
  287. seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
  288. seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
  289. seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
  290. seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
  291. seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
  292. return 0;
  293. }
  294. DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
  295. static void pmc_dbgfs_register(struct pmc_dev *pmc)
  296. {
  297. struct dentry *dir;
  298. dir = debugfs_create_dir("pmc_atom", NULL);
  299. pmc->dbgfs_dir = dir;
  300. debugfs_create_file("dev_state", S_IFREG | S_IRUGO, dir, pmc,
  301. &pmc_dev_state_fops);
  302. debugfs_create_file("pss_state", S_IFREG | S_IRUGO, dir, pmc,
  303. &pmc_pss_state_fops);
  304. debugfs_create_file("sleep_state", S_IFREG | S_IRUGO, dir, pmc,
  305. &pmc_sleep_tmr_fops);
  306. }
  307. #else
  308. static void pmc_dbgfs_register(struct pmc_dev *pmc)
  309. {
  310. }
  311. #endif /* CONFIG_DEBUG_FS */
  312. /*
  313. * Some systems need one or more of their pmc_plt_clks to be
  314. * marked as critical.
  315. */
  316. static const struct dmi_system_id critclk_systems[] = {
  317. {
  318. /* pmc_plt_clk0 is used for an external HSIC USB HUB */
  319. .ident = "MPL CEC1x",
  320. .matches = {
  321. DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
  322. DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
  323. },
  324. },
  325. {
  326. /* pmc_plt_clk0 - 3 are used for the 4 ethernet controllers */
  327. .ident = "Lex 3I380D",
  328. .matches = {
  329. DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
  330. DMI_MATCH(DMI_PRODUCT_NAME, "3I380D"),
  331. },
  332. },
  333. {
  334. /* pmc_plt_clk* - are used for ethernet controllers */
  335. .ident = "Lex 2I385SW",
  336. .matches = {
  337. DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
  338. DMI_MATCH(DMI_PRODUCT_NAME, "2I385SW"),
  339. },
  340. },
  341. {
  342. /* pmc_plt_clk* - are used for ethernet controllers */
  343. .ident = "Beckhoff Baytrail",
  344. .matches = {
  345. DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
  346. DMI_MATCH(DMI_PRODUCT_FAMILY, "CBxx63"),
  347. },
  348. },
  349. {
  350. .ident = "SIMATIC IPC227E",
  351. .matches = {
  352. DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
  353. DMI_MATCH(DMI_PRODUCT_VERSION, "6ES7647-8B"),
  354. },
  355. },
  356. {
  357. .ident = "SIMATIC IPC277E",
  358. .matches = {
  359. DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
  360. DMI_MATCH(DMI_PRODUCT_VERSION, "6AV7882-0"),
  361. },
  362. },
  363. {
  364. .ident = "CONNECT X300",
  365. .matches = {
  366. DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
  367. DMI_MATCH(DMI_PRODUCT_VERSION, "A5E45074588"),
  368. },
  369. },
  370. { /*sentinel*/ }
  371. };
  372. static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
  373. const struct pmc_data *pmc_data)
  374. {
  375. struct platform_device *clkdev;
  376. struct pmc_clk_data *clk_data;
  377. const struct dmi_system_id *d = dmi_first_match(critclk_systems);
  378. clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
  379. if (!clk_data)
  380. return -ENOMEM;
  381. clk_data->base = pmc_regmap; /* offset is added by client */
  382. clk_data->clks = pmc_data->clks;
  383. if (d) {
  384. clk_data->critical = true;
  385. pr_info("%s critclks quirk enabled\n", d->ident);
  386. }
  387. clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
  388. PLATFORM_DEVID_NONE,
  389. clk_data, sizeof(*clk_data));
  390. if (IS_ERR(clkdev)) {
  391. kfree(clk_data);
  392. return PTR_ERR(clkdev);
  393. }
  394. kfree(clk_data);
  395. return 0;
  396. }
  397. static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
  398. {
  399. struct pmc_dev *pmc = &pmc_device;
  400. const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
  401. const struct pmc_reg_map *map = data->map;
  402. int ret;
  403. /* Obtain ACPI base address */
  404. pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
  405. acpi_base_addr &= ACPI_BASE_ADDR_MASK;
  406. /* Install power off function */
  407. if (acpi_base_addr != 0 && pm_power_off == NULL)
  408. pm_power_off = pmc_power_off;
  409. pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
  410. pmc->base_addr &= PMC_BASE_ADDR_MASK;
  411. pmc->regmap = ioremap(pmc->base_addr, PMC_MMIO_REG_LEN);
  412. if (!pmc->regmap) {
  413. dev_err(&pdev->dev, "error: ioremap failed\n");
  414. return -ENOMEM;
  415. }
  416. pmc->map = map;
  417. /* PMC hardware registers setup */
  418. pmc_hw_reg_setup(pmc);
  419. pmc_dbgfs_register(pmc);
  420. /* Register platform clocks - PMC_PLT_CLK [0..5] */
  421. ret = pmc_setup_clks(pdev, pmc->regmap, data);
  422. if (ret)
  423. dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
  424. ret);
  425. pmc->init = true;
  426. return ret;
  427. }
  428. /*
  429. * Data for PCI driver interface
  430. *
  431. * used by pci_match_id() call below.
  432. */
  433. static const struct pci_device_id pmc_pci_ids[] = {
  434. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
  435. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
  436. { 0, },
  437. };
  438. static int __init pmc_atom_init(void)
  439. {
  440. struct pci_dev *pdev = NULL;
  441. const struct pci_device_id *ent;
  442. /* We look for our device - PCU PMC
  443. * we assume that there is max. one device.
  444. *
  445. * We can't use plain pci_driver mechanism,
  446. * as the device is really a multiple function device,
  447. * main driver that binds to the pci_device is lpc_ich
  448. * and have to find & bind to the device this way.
  449. */
  450. for_each_pci_dev(pdev) {
  451. ent = pci_match_id(pmc_pci_ids, pdev);
  452. if (ent)
  453. return pmc_setup_dev(pdev, ent);
  454. }
  455. /* Device not found. */
  456. return -ENODEV;
  457. }
  458. device_initcall(pmc_atom_init);
  459. /*
  460. MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
  461. MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
  462. MODULE_LICENSE("GPL v2");
  463. */