intel_turbo_max_3.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Turbo Boost Max Technology 3.0 legacy (non HWP) enumeration driver
  4. * Copyright (c) 2017, Intel Corporation.
  5. * All rights reserved.
  6. *
  7. * Author: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
  8. */
  9. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10. #include <linux/cpufeature.h>
  11. #include <linux/cpuhotplug.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/topology.h>
  15. #include <linux/workqueue.h>
  16. #include <asm/cpu_device_id.h>
  17. #include <asm/intel-family.h>
  18. #define MSR_OC_MAILBOX 0x150
  19. #define MSR_OC_MAILBOX_CMD_OFFSET 32
  20. #define MSR_OC_MAILBOX_RSP_OFFSET 32
  21. #define MSR_OC_MAILBOX_BUSY_BIT 63
  22. #define OC_MAILBOX_FC_CONTROL_CMD 0x1C
  23. /*
  24. * Typical latency to get mail box response is ~3us, It takes +3 us to
  25. * process reading mailbox after issuing mailbox write on a Broadwell 3.4 GHz
  26. * system. So for most of the time, the first mailbox read should have the
  27. * response, but to avoid some boundary cases retry twice.
  28. */
  29. #define OC_MAILBOX_RETRY_COUNT 2
  30. static int get_oc_core_priority(unsigned int cpu)
  31. {
  32. u64 value, cmd = OC_MAILBOX_FC_CONTROL_CMD;
  33. int ret, i;
  34. /* Issue favored core read command */
  35. value = cmd << MSR_OC_MAILBOX_CMD_OFFSET;
  36. /* Set the busy bit to indicate OS is trying to issue command */
  37. value |= BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT);
  38. ret = wrmsrl_safe(MSR_OC_MAILBOX, value);
  39. if (ret) {
  40. pr_debug("cpu %d OC mailbox write failed\n", cpu);
  41. return ret;
  42. }
  43. for (i = 0; i < OC_MAILBOX_RETRY_COUNT; ++i) {
  44. ret = rdmsrl_safe(MSR_OC_MAILBOX, &value);
  45. if (ret) {
  46. pr_debug("cpu %d OC mailbox read failed\n", cpu);
  47. break;
  48. }
  49. if (value & BIT_ULL(MSR_OC_MAILBOX_BUSY_BIT)) {
  50. pr_debug("cpu %d OC mailbox still processing\n", cpu);
  51. ret = -EBUSY;
  52. continue;
  53. }
  54. if ((value >> MSR_OC_MAILBOX_RSP_OFFSET) & 0xff) {
  55. pr_debug("cpu %d OC mailbox cmd failed\n", cpu);
  56. ret = -ENXIO;
  57. break;
  58. }
  59. ret = value & 0xff;
  60. pr_debug("cpu %d max_ratio %d\n", cpu, ret);
  61. break;
  62. }
  63. return ret;
  64. }
  65. /*
  66. * The work item is needed to avoid CPU hotplug locking issues. The function
  67. * itmt_legacy_set_priority() is called from CPU online callback, so can't
  68. * call sched_set_itmt_support() from there as this function will aquire
  69. * hotplug locks in its path.
  70. */
  71. static void itmt_legacy_work_fn(struct work_struct *work)
  72. {
  73. sched_set_itmt_support();
  74. }
  75. static DECLARE_WORK(sched_itmt_work, itmt_legacy_work_fn);
  76. static int itmt_legacy_cpu_online(unsigned int cpu)
  77. {
  78. static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
  79. int priority;
  80. priority = get_oc_core_priority(cpu);
  81. if (priority < 0)
  82. return 0;
  83. sched_set_itmt_core_prio(priority, cpu);
  84. /* Enable ITMT feature when a core with different priority is found */
  85. if (max_highest_perf <= min_highest_perf) {
  86. if (priority > max_highest_perf)
  87. max_highest_perf = priority;
  88. if (priority < min_highest_perf)
  89. min_highest_perf = priority;
  90. if (max_highest_perf > min_highest_perf)
  91. schedule_work(&sched_itmt_work);
  92. }
  93. return 0;
  94. }
  95. static const struct x86_cpu_id itmt_legacy_cpu_ids[] = {
  96. X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, NULL),
  97. X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL),
  98. {}
  99. };
  100. static int __init itmt_legacy_init(void)
  101. {
  102. const struct x86_cpu_id *id;
  103. int ret;
  104. id = x86_match_cpu(itmt_legacy_cpu_ids);
  105. if (!id)
  106. return -ENODEV;
  107. ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
  108. "platform/x86/turbo_max_3:online",
  109. itmt_legacy_cpu_online, NULL);
  110. if (ret < 0)
  111. return ret;
  112. return 0;
  113. }
  114. late_initcall(itmt_legacy_init)