intel_scu_ipc.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for the Intel SCU IPC mechanism
  4. *
  5. * (C) Copyright 2008-2010,2015 Intel Corporation
  6. * Author: Sreedhara DS (sreedhara.ds@intel.com)
  7. *
  8. * SCU running in ARC processor communicates with other entity running in IA
  9. * core through IPC mechanism which in turn messaging between IA core ad SCU.
  10. * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
  11. * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
  12. * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
  13. * along with other APIs.
  14. */
  15. #include <linux/delay.h>
  16. #include <linux/device.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/io.h>
  21. #include <linux/module.h>
  22. #include <linux/slab.h>
  23. #include <asm/intel_scu_ipc.h>
  24. /* IPC defines the following message types */
  25. #define IPCMSG_PCNTRL 0xff /* Power controller unit read/write */
  26. /* Command id associated with message IPCMSG_PCNTRL */
  27. #define IPC_CMD_PCNTRL_W 0 /* Register write */
  28. #define IPC_CMD_PCNTRL_R 1 /* Register read */
  29. #define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
  30. /*
  31. * IPC register summary
  32. *
  33. * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
  34. * To read or write information to the SCU, driver writes to IPC-1 memory
  35. * mapped registers. The following is the IPC mechanism
  36. *
  37. * 1. IA core cDMI interface claims this transaction and converts it to a
  38. * Transaction Layer Packet (TLP) message which is sent across the cDMI.
  39. *
  40. * 2. South Complex cDMI block receives this message and writes it to
  41. * the IPC-1 register block, causing an interrupt to the SCU
  42. *
  43. * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
  44. * message handler is called within firmware.
  45. */
  46. #define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
  47. #define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
  48. #define IPC_IOC 0x100 /* IPC command register IOC bit */
  49. struct intel_scu_ipc_dev {
  50. struct device dev;
  51. struct resource mem;
  52. struct module *owner;
  53. int irq;
  54. void __iomem *ipc_base;
  55. struct completion cmd_complete;
  56. };
  57. #define IPC_STATUS 0x04
  58. #define IPC_STATUS_IRQ BIT(2)
  59. #define IPC_STATUS_ERR BIT(1)
  60. #define IPC_STATUS_BUSY BIT(0)
  61. /*
  62. * IPC Write/Read Buffers:
  63. * 16 byte buffer for sending and receiving data to and from SCU.
  64. */
  65. #define IPC_WRITE_BUFFER 0x80
  66. #define IPC_READ_BUFFER 0x90
  67. /* Timeout in jiffies */
  68. #define IPC_TIMEOUT (3 * HZ)
  69. static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
  70. static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
  71. static struct class intel_scu_ipc_class = {
  72. .name = "intel_scu_ipc",
  73. .owner = THIS_MODULE,
  74. };
  75. /**
  76. * intel_scu_ipc_dev_get() - Get SCU IPC instance
  77. *
  78. * The recommended new API takes SCU IPC instance as parameter and this
  79. * function can be called by driver to get the instance. This also makes
  80. * sure the driver providing the IPC functionality cannot be unloaded
  81. * while the caller has the instance.
  82. *
  83. * Call intel_scu_ipc_dev_put() to release the instance.
  84. *
  85. * Returns %NULL if SCU IPC is not currently available.
  86. */
  87. struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
  88. {
  89. struct intel_scu_ipc_dev *scu = NULL;
  90. mutex_lock(&ipclock);
  91. if (ipcdev) {
  92. get_device(&ipcdev->dev);
  93. /*
  94. * Prevent the IPC provider from being unloaded while it
  95. * is being used.
  96. */
  97. if (!try_module_get(ipcdev->owner))
  98. put_device(&ipcdev->dev);
  99. else
  100. scu = ipcdev;
  101. }
  102. mutex_unlock(&ipclock);
  103. return scu;
  104. }
  105. EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
  106. /**
  107. * intel_scu_ipc_dev_put() - Put SCU IPC instance
  108. * @scu: SCU IPC instance
  109. *
  110. * This function releases the SCU IPC instance retrieved from
  111. * intel_scu_ipc_dev_get() and allows the driver providing IPC to be
  112. * unloaded.
  113. */
  114. void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
  115. {
  116. if (scu) {
  117. module_put(scu->owner);
  118. put_device(&scu->dev);
  119. }
  120. }
  121. EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
  122. struct intel_scu_ipc_devres {
  123. struct intel_scu_ipc_dev *scu;
  124. };
  125. static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
  126. {
  127. struct intel_scu_ipc_devres *dr = res;
  128. struct intel_scu_ipc_dev *scu = dr->scu;
  129. intel_scu_ipc_dev_put(scu);
  130. }
  131. /**
  132. * devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
  133. * @dev: Device requesting the SCU IPC device
  134. *
  135. * The recommended new API takes SCU IPC instance as parameter and this
  136. * function can be called by driver to get the instance. This also makes
  137. * sure the driver providing the IPC functionality cannot be unloaded
  138. * while the caller has the instance.
  139. *
  140. * Returns %NULL if SCU IPC is not currently available.
  141. */
  142. struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
  143. {
  144. struct intel_scu_ipc_devres *dr;
  145. struct intel_scu_ipc_dev *scu;
  146. dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
  147. if (!dr)
  148. return NULL;
  149. scu = intel_scu_ipc_dev_get();
  150. if (!scu) {
  151. devres_free(dr);
  152. return NULL;
  153. }
  154. dr->scu = scu;
  155. devres_add(dev, dr);
  156. return scu;
  157. }
  158. EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
  159. /*
  160. * Send ipc command
  161. * Command Register (Write Only):
  162. * A write to this register results in an interrupt to the SCU core processor
  163. * Format:
  164. * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
  165. */
  166. static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
  167. {
  168. reinit_completion(&scu->cmd_complete);
  169. writel(cmd | IPC_IOC, scu->ipc_base);
  170. }
  171. /*
  172. * Write ipc data
  173. * IPC Write Buffer (Write Only):
  174. * 16-byte buffer for sending data associated with IPC command to
  175. * SCU. Size of the data is specified in the IPC_COMMAND_REG register
  176. */
  177. static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
  178. {
  179. writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
  180. }
  181. /*
  182. * Status Register (Read Only):
  183. * Driver will read this register to get the ready/busy status of the IPC
  184. * block and error status of the IPC command that was just processed by SCU
  185. * Format:
  186. * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
  187. */
  188. static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
  189. {
  190. return __raw_readl(scu->ipc_base + IPC_STATUS);
  191. }
  192. /* Read ipc byte data */
  193. static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
  194. {
  195. return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
  196. }
  197. /* Read ipc u32 data */
  198. static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
  199. {
  200. return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
  201. }
  202. /* Wait till scu status is busy */
  203. static inline int busy_loop(struct intel_scu_ipc_dev *scu)
  204. {
  205. unsigned long end = jiffies + IPC_TIMEOUT;
  206. do {
  207. u32 status;
  208. status = ipc_read_status(scu);
  209. if (!(status & IPC_STATUS_BUSY))
  210. return (status & IPC_STATUS_ERR) ? -EIO : 0;
  211. usleep_range(50, 100);
  212. } while (time_before(jiffies, end));
  213. return -ETIMEDOUT;
  214. }
  215. /* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
  216. static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
  217. {
  218. int status;
  219. if (!wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT))
  220. return -ETIMEDOUT;
  221. status = ipc_read_status(scu);
  222. if (status & IPC_STATUS_ERR)
  223. return -EIO;
  224. return 0;
  225. }
  226. static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
  227. {
  228. return scu->irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
  229. }
  230. /* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
  231. static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
  232. u32 count, u32 op, u32 id)
  233. {
  234. int nc;
  235. u32 offset = 0;
  236. int err;
  237. u8 cbuf[IPC_WWBUF_SIZE];
  238. u32 *wbuf = (u32 *)&cbuf;
  239. memset(cbuf, 0, sizeof(cbuf));
  240. mutex_lock(&ipclock);
  241. if (!scu)
  242. scu = ipcdev;
  243. if (!scu) {
  244. mutex_unlock(&ipclock);
  245. return -ENODEV;
  246. }
  247. for (nc = 0; nc < count; nc++, offset += 2) {
  248. cbuf[offset] = addr[nc];
  249. cbuf[offset + 1] = addr[nc] >> 8;
  250. }
  251. if (id == IPC_CMD_PCNTRL_R) {
  252. for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
  253. ipc_data_writel(scu, wbuf[nc], offset);
  254. ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
  255. } else if (id == IPC_CMD_PCNTRL_W) {
  256. for (nc = 0; nc < count; nc++, offset += 1)
  257. cbuf[offset] = data[nc];
  258. for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
  259. ipc_data_writel(scu, wbuf[nc], offset);
  260. ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
  261. } else if (id == IPC_CMD_PCNTRL_M) {
  262. cbuf[offset] = data[0];
  263. cbuf[offset + 1] = data[1];
  264. ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
  265. ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
  266. }
  267. err = intel_scu_ipc_check_status(scu);
  268. if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
  269. /* Workaround: values are read as 0 without memcpy_fromio */
  270. memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
  271. for (nc = 0; nc < count; nc++)
  272. data[nc] = ipc_data_readb(scu, nc);
  273. }
  274. mutex_unlock(&ipclock);
  275. return err;
  276. }
  277. /**
  278. * intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
  279. * @scu: Optional SCU IPC instance
  280. * @addr: Register on SCU
  281. * @data: Return pointer for read byte
  282. *
  283. * Read a single register. Returns %0 on success or an error code. All
  284. * locking between SCU accesses is handled for the caller.
  285. *
  286. * This function may sleep.
  287. */
  288. int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
  289. {
  290. return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
  291. }
  292. EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
  293. /**
  294. * intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
  295. * @scu: Optional SCU IPC instance
  296. * @addr: Register on SCU
  297. * @data: Byte to write
  298. *
  299. * Write a single register. Returns %0 on success or an error code. All
  300. * locking between SCU accesses is handled for the caller.
  301. *
  302. * This function may sleep.
  303. */
  304. int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
  305. {
  306. return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
  307. }
  308. EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
  309. /**
  310. * intel_scu_ipc_dev_readv() - Read a set of registers
  311. * @scu: Optional SCU IPC instance
  312. * @addr: Register list
  313. * @data: Bytes to return
  314. * @len: Length of array
  315. *
  316. * Read registers. Returns %0 on success or an error code. All locking
  317. * between SCU accesses is handled for the caller.
  318. *
  319. * The largest array length permitted by the hardware is 5 items.
  320. *
  321. * This function may sleep.
  322. */
  323. int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
  324. size_t len)
  325. {
  326. return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
  327. }
  328. EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
  329. /**
  330. * intel_scu_ipc_dev_writev() - Write a set of registers
  331. * @scu: Optional SCU IPC instance
  332. * @addr: Register list
  333. * @data: Bytes to write
  334. * @len: Length of array
  335. *
  336. * Write registers. Returns %0 on success or an error code. All locking
  337. * between SCU accesses is handled for the caller.
  338. *
  339. * The largest array length permitted by the hardware is 5 items.
  340. *
  341. * This function may sleep.
  342. */
  343. int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
  344. size_t len)
  345. {
  346. return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
  347. }
  348. EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
  349. /**
  350. * intel_scu_ipc_dev_update() - Update a register
  351. * @scu: Optional SCU IPC instance
  352. * @addr: Register address
  353. * @data: Bits to update
  354. * @mask: Mask of bits to update
  355. *
  356. * Read-modify-write power control unit register. The first data argument
  357. * must be register value and second is mask value mask is a bitmap that
  358. * indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
  359. * modify this bit. returns %0 on success or an error code.
  360. *
  361. * This function may sleep. Locking between SCU accesses is handled
  362. * for the caller.
  363. */
  364. int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
  365. u8 mask)
  366. {
  367. u8 tmp[2] = { data, mask };
  368. return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
  369. }
  370. EXPORT_SYMBOL(intel_scu_ipc_dev_update);
  371. /**
  372. * intel_scu_ipc_dev_simple_command() - Send a simple command
  373. * @scu: Optional SCU IPC instance
  374. * @cmd: Command
  375. * @sub: Sub type
  376. *
  377. * Issue a simple command to the SCU. Do not use this interface if you must
  378. * then access data as any data values may be overwritten by another SCU
  379. * access by the time this function returns.
  380. *
  381. * This function may sleep. Locking for SCU accesses is handled for the
  382. * caller.
  383. */
  384. int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
  385. int sub)
  386. {
  387. u32 cmdval;
  388. int err;
  389. mutex_lock(&ipclock);
  390. if (!scu)
  391. scu = ipcdev;
  392. if (!scu) {
  393. mutex_unlock(&ipclock);
  394. return -ENODEV;
  395. }
  396. scu = ipcdev;
  397. cmdval = sub << 12 | cmd;
  398. ipc_command(scu, cmdval);
  399. err = intel_scu_ipc_check_status(scu);
  400. mutex_unlock(&ipclock);
  401. if (err)
  402. dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
  403. return err;
  404. }
  405. EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
  406. /**
  407. * intel_scu_ipc_command_with_size() - Command with data
  408. * @scu: Optional SCU IPC instance
  409. * @cmd: Command
  410. * @sub: Sub type
  411. * @in: Input data
  412. * @inlen: Input length in bytes
  413. * @size: Input size written to the IPC command register in whatever
  414. * units (dword, byte) the particular firmware requires. Normally
  415. * should be the same as @inlen.
  416. * @out: Output data
  417. * @outlen: Output length in bytes
  418. *
  419. * Issue a command to the SCU which involves data transfers. Do the
  420. * data copies under the lock but leave it for the caller to interpret.
  421. */
  422. int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
  423. int sub, const void *in, size_t inlen,
  424. size_t size, void *out, size_t outlen)
  425. {
  426. size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
  427. size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
  428. u32 cmdval, inbuf[4] = {};
  429. int i, err;
  430. if (inbuflen > 4 || outbuflen > 4)
  431. return -EINVAL;
  432. mutex_lock(&ipclock);
  433. if (!scu)
  434. scu = ipcdev;
  435. if (!scu) {
  436. mutex_unlock(&ipclock);
  437. return -ENODEV;
  438. }
  439. memcpy(inbuf, in, inlen);
  440. for (i = 0; i < inbuflen; i++)
  441. ipc_data_writel(scu, inbuf[i], 4 * i);
  442. cmdval = (size << 16) | (sub << 12) | cmd;
  443. ipc_command(scu, cmdval);
  444. err = intel_scu_ipc_check_status(scu);
  445. if (!err) {
  446. u32 outbuf[4] = {};
  447. for (i = 0; i < outbuflen; i++)
  448. outbuf[i] = ipc_data_readl(scu, 4 * i);
  449. memcpy(out, outbuf, outlen);
  450. }
  451. mutex_unlock(&ipclock);
  452. if (err)
  453. dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
  454. return err;
  455. }
  456. EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
  457. /*
  458. * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
  459. * When ioc bit is set to 1, caller api must wait for interrupt handler called
  460. * which in turn unlocks the caller api. Currently this is not used
  461. *
  462. * This is edge triggered so we need take no action to clear anything
  463. */
  464. static irqreturn_t ioc(int irq, void *dev_id)
  465. {
  466. struct intel_scu_ipc_dev *scu = dev_id;
  467. int status = ipc_read_status(scu);
  468. writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
  469. complete(&scu->cmd_complete);
  470. return IRQ_HANDLED;
  471. }
  472. static void intel_scu_ipc_release(struct device *dev)
  473. {
  474. struct intel_scu_ipc_dev *scu;
  475. scu = container_of(dev, struct intel_scu_ipc_dev, dev);
  476. if (scu->irq > 0)
  477. free_irq(scu->irq, scu);
  478. iounmap(scu->ipc_base);
  479. release_mem_region(scu->mem.start, resource_size(&scu->mem));
  480. kfree(scu);
  481. }
  482. /**
  483. * __intel_scu_ipc_register() - Register SCU IPC device
  484. * @parent: Parent device
  485. * @scu_data: Data used to configure SCU IPC
  486. * @owner: Module registering the SCU IPC device
  487. *
  488. * Call this function to register SCU IPC mechanism under @parent.
  489. * Returns pointer to the new SCU IPC device or ERR_PTR() in case of
  490. * failure. The caller may use the returned instance if it needs to do
  491. * SCU IPC calls itself.
  492. */
  493. struct intel_scu_ipc_dev *
  494. __intel_scu_ipc_register(struct device *parent,
  495. const struct intel_scu_ipc_data *scu_data,
  496. struct module *owner)
  497. {
  498. int err;
  499. struct intel_scu_ipc_dev *scu;
  500. void __iomem *ipc_base;
  501. mutex_lock(&ipclock);
  502. /* We support only one IPC */
  503. if (ipcdev) {
  504. err = -EBUSY;
  505. goto err_unlock;
  506. }
  507. scu = kzalloc(sizeof(*scu), GFP_KERNEL);
  508. if (!scu) {
  509. err = -ENOMEM;
  510. goto err_unlock;
  511. }
  512. scu->owner = owner;
  513. scu->dev.parent = parent;
  514. scu->dev.class = &intel_scu_ipc_class;
  515. scu->dev.release = intel_scu_ipc_release;
  516. dev_set_name(&scu->dev, "intel_scu_ipc");
  517. if (!request_mem_region(scu_data->mem.start, resource_size(&scu_data->mem),
  518. "intel_scu_ipc")) {
  519. err = -EBUSY;
  520. goto err_free;
  521. }
  522. ipc_base = ioremap(scu_data->mem.start, resource_size(&scu_data->mem));
  523. if (!ipc_base) {
  524. err = -ENOMEM;
  525. goto err_release;
  526. }
  527. scu->ipc_base = ipc_base;
  528. scu->mem = scu_data->mem;
  529. scu->irq = scu_data->irq;
  530. init_completion(&scu->cmd_complete);
  531. if (scu->irq > 0) {
  532. err = request_irq(scu->irq, ioc, 0, "intel_scu_ipc", scu);
  533. if (err)
  534. goto err_unmap;
  535. }
  536. /*
  537. * After this point intel_scu_ipc_release() takes care of
  538. * releasing the SCU IPC resources once refcount drops to zero.
  539. */
  540. err = device_register(&scu->dev);
  541. if (err) {
  542. put_device(&scu->dev);
  543. goto err_unlock;
  544. }
  545. /* Assign device at last */
  546. ipcdev = scu;
  547. mutex_unlock(&ipclock);
  548. return scu;
  549. err_unmap:
  550. iounmap(ipc_base);
  551. err_release:
  552. release_mem_region(scu_data->mem.start, resource_size(&scu_data->mem));
  553. err_free:
  554. kfree(scu);
  555. err_unlock:
  556. mutex_unlock(&ipclock);
  557. return ERR_PTR(err);
  558. }
  559. EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
  560. /**
  561. * intel_scu_ipc_unregister() - Unregister SCU IPC
  562. * @scu: SCU IPC handle
  563. *
  564. * This unregisters the SCU IPC device and releases the acquired
  565. * resources once the refcount goes to zero.
  566. */
  567. void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
  568. {
  569. mutex_lock(&ipclock);
  570. if (!WARN_ON(!ipcdev)) {
  571. ipcdev = NULL;
  572. device_unregister(&scu->dev);
  573. }
  574. mutex_unlock(&ipclock);
  575. }
  576. EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
  577. static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
  578. {
  579. struct intel_scu_ipc_devres *dr = res;
  580. struct intel_scu_ipc_dev *scu = dr->scu;
  581. intel_scu_ipc_unregister(scu);
  582. }
  583. /**
  584. * __devm_intel_scu_ipc_register() - Register managed SCU IPC device
  585. * @parent: Parent device
  586. * @scu_data: Data used to configure SCU IPC
  587. * @owner: Module registering the SCU IPC device
  588. *
  589. * Call this function to register managed SCU IPC mechanism under
  590. * @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
  591. * case of failure. The caller may use the returned instance if it needs
  592. * to do SCU IPC calls itself.
  593. */
  594. struct intel_scu_ipc_dev *
  595. __devm_intel_scu_ipc_register(struct device *parent,
  596. const struct intel_scu_ipc_data *scu_data,
  597. struct module *owner)
  598. {
  599. struct intel_scu_ipc_devres *dr;
  600. struct intel_scu_ipc_dev *scu;
  601. dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
  602. if (!dr)
  603. return NULL;
  604. scu = __intel_scu_ipc_register(parent, scu_data, owner);
  605. if (IS_ERR(scu)) {
  606. devres_free(dr);
  607. return scu;
  608. }
  609. dr->scu = scu;
  610. devres_add(parent, dr);
  611. return scu;
  612. }
  613. EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
  614. static int __init intel_scu_ipc_init(void)
  615. {
  616. return class_register(&intel_scu_ipc_class);
  617. }
  618. subsys_initcall(intel_scu_ipc_init);
  619. static void __exit intel_scu_ipc_exit(void)
  620. {
  621. class_unregister(&intel_scu_ipc_class);
  622. }
  623. module_exit(intel_scu_ipc_exit);