intel_punit_ipc.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for the Intel P-Unit Mailbox IPC mechanism
  4. *
  5. * (C) Copyright 2015 Intel Corporation
  6. *
  7. * The heart of the P-Unit is the Foxton microcontroller and its firmware,
  8. * which provide mailbox interface for power management usage.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/delay.h>
  12. #include <linux/device.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <asm/intel_punit_ipc.h>
  19. /* IPC Mailbox registers */
  20. #define OFFSET_DATA_LOW 0x0
  21. #define OFFSET_DATA_HIGH 0x4
  22. /* bit field of interface register */
  23. #define CMD_RUN BIT(31)
  24. #define CMD_ERRCODE_MASK GENMASK(7, 0)
  25. #define CMD_PARA1_SHIFT 8
  26. #define CMD_PARA2_SHIFT 16
  27. #define CMD_TIMEOUT_SECONDS 1
  28. enum {
  29. BASE_DATA = 0,
  30. BASE_IFACE,
  31. BASE_MAX,
  32. };
  33. typedef struct {
  34. struct device *dev;
  35. struct mutex lock;
  36. int irq;
  37. struct completion cmd_complete;
  38. /* base of interface and data registers */
  39. void __iomem *base[RESERVED_IPC][BASE_MAX];
  40. IPC_TYPE type;
  41. } IPC_DEV;
  42. static IPC_DEV *punit_ipcdev;
  43. static inline u32 ipc_read_status(IPC_DEV *ipcdev, IPC_TYPE type)
  44. {
  45. return readl(ipcdev->base[type][BASE_IFACE]);
  46. }
  47. static inline void ipc_write_cmd(IPC_DEV *ipcdev, IPC_TYPE type, u32 cmd)
  48. {
  49. writel(cmd, ipcdev->base[type][BASE_IFACE]);
  50. }
  51. static inline u32 ipc_read_data_low(IPC_DEV *ipcdev, IPC_TYPE type)
  52. {
  53. return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
  54. }
  55. static inline u32 ipc_read_data_high(IPC_DEV *ipcdev, IPC_TYPE type)
  56. {
  57. return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
  58. }
  59. static inline void ipc_write_data_low(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
  60. {
  61. writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW);
  62. }
  63. static inline void ipc_write_data_high(IPC_DEV *ipcdev, IPC_TYPE type, u32 data)
  64. {
  65. writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH);
  66. }
  67. static const char *ipc_err_string(int error)
  68. {
  69. if (error == IPC_PUNIT_ERR_SUCCESS)
  70. return "no error";
  71. else if (error == IPC_PUNIT_ERR_INVALID_CMD)
  72. return "invalid command";
  73. else if (error == IPC_PUNIT_ERR_INVALID_PARAMETER)
  74. return "invalid parameter";
  75. else if (error == IPC_PUNIT_ERR_CMD_TIMEOUT)
  76. return "command timeout";
  77. else if (error == IPC_PUNIT_ERR_CMD_LOCKED)
  78. return "command locked";
  79. else if (error == IPC_PUNIT_ERR_INVALID_VR_ID)
  80. return "invalid vr id";
  81. else if (error == IPC_PUNIT_ERR_VR_ERR)
  82. return "vr error";
  83. else
  84. return "unknown error";
  85. }
  86. static int intel_punit_ipc_check_status(IPC_DEV *ipcdev, IPC_TYPE type)
  87. {
  88. int loops = CMD_TIMEOUT_SECONDS * USEC_PER_SEC;
  89. int errcode;
  90. int status;
  91. if (ipcdev->irq) {
  92. if (!wait_for_completion_timeout(&ipcdev->cmd_complete,
  93. CMD_TIMEOUT_SECONDS * HZ)) {
  94. dev_err(ipcdev->dev, "IPC timed out\n");
  95. return -ETIMEDOUT;
  96. }
  97. } else {
  98. while ((ipc_read_status(ipcdev, type) & CMD_RUN) && --loops)
  99. udelay(1);
  100. if (!loops) {
  101. dev_err(ipcdev->dev, "IPC timed out\n");
  102. return -ETIMEDOUT;
  103. }
  104. }
  105. status = ipc_read_status(ipcdev, type);
  106. errcode = status & CMD_ERRCODE_MASK;
  107. if (errcode) {
  108. dev_err(ipcdev->dev, "IPC failed: %s, IPC_STS=0x%x\n",
  109. ipc_err_string(errcode), status);
  110. return -EIO;
  111. }
  112. return 0;
  113. }
  114. /**
  115. * intel_punit_ipc_simple_command() - Simple IPC command
  116. * @cmd: IPC command code.
  117. * @para1: First 8bit parameter, set 0 if not used.
  118. * @para2: Second 8bit parameter, set 0 if not used.
  119. *
  120. * Send a IPC command to P-Unit when there is no data transaction
  121. *
  122. * Return: IPC error code or 0 on success.
  123. */
  124. int intel_punit_ipc_simple_command(int cmd, int para1, int para2)
  125. {
  126. IPC_DEV *ipcdev = punit_ipcdev;
  127. IPC_TYPE type;
  128. u32 val;
  129. int ret;
  130. mutex_lock(&ipcdev->lock);
  131. reinit_completion(&ipcdev->cmd_complete);
  132. type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
  133. val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
  134. val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
  135. ipc_write_cmd(ipcdev, type, val);
  136. ret = intel_punit_ipc_check_status(ipcdev, type);
  137. mutex_unlock(&ipcdev->lock);
  138. return ret;
  139. }
  140. EXPORT_SYMBOL(intel_punit_ipc_simple_command);
  141. /**
  142. * intel_punit_ipc_command() - IPC command with data and pointers
  143. * @cmd: IPC command code.
  144. * @para1: First 8bit parameter, set 0 if not used.
  145. * @para2: Second 8bit parameter, set 0 if not used.
  146. * @in: Input data, 32bit for BIOS cmd, two 32bit for GTD and ISPD.
  147. * @out: Output data.
  148. *
  149. * Send a IPC command to P-Unit with data transaction
  150. *
  151. * Return: IPC error code or 0 on success.
  152. */
  153. int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out)
  154. {
  155. IPC_DEV *ipcdev = punit_ipcdev;
  156. IPC_TYPE type;
  157. u32 val;
  158. int ret;
  159. mutex_lock(&ipcdev->lock);
  160. reinit_completion(&ipcdev->cmd_complete);
  161. type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET;
  162. if (in) {
  163. ipc_write_data_low(ipcdev, type, *in);
  164. if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
  165. ipc_write_data_high(ipcdev, type, *++in);
  166. }
  167. val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK;
  168. val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT;
  169. ipc_write_cmd(ipcdev, type, val);
  170. ret = intel_punit_ipc_check_status(ipcdev, type);
  171. if (ret)
  172. goto out;
  173. if (out) {
  174. *out = ipc_read_data_low(ipcdev, type);
  175. if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC)
  176. *++out = ipc_read_data_high(ipcdev, type);
  177. }
  178. out:
  179. mutex_unlock(&ipcdev->lock);
  180. return ret;
  181. }
  182. EXPORT_SYMBOL_GPL(intel_punit_ipc_command);
  183. static irqreturn_t intel_punit_ioc(int irq, void *dev_id)
  184. {
  185. IPC_DEV *ipcdev = dev_id;
  186. complete(&ipcdev->cmd_complete);
  187. return IRQ_HANDLED;
  188. }
  189. static int intel_punit_get_bars(struct platform_device *pdev)
  190. {
  191. void __iomem *addr;
  192. /*
  193. * The following resources are required
  194. * - BIOS_IPC BASE_DATA
  195. * - BIOS_IPC BASE_IFACE
  196. */
  197. addr = devm_platform_ioremap_resource(pdev, 0);
  198. if (IS_ERR(addr))
  199. return PTR_ERR(addr);
  200. punit_ipcdev->base[BIOS_IPC][BASE_DATA] = addr;
  201. addr = devm_platform_ioremap_resource(pdev, 1);
  202. if (IS_ERR(addr))
  203. return PTR_ERR(addr);
  204. punit_ipcdev->base[BIOS_IPC][BASE_IFACE] = addr;
  205. /*
  206. * The following resources are optional
  207. * - ISPDRIVER_IPC BASE_DATA
  208. * - ISPDRIVER_IPC BASE_IFACE
  209. * - GTDRIVER_IPC BASE_DATA
  210. * - GTDRIVER_IPC BASE_IFACE
  211. */
  212. addr = devm_platform_ioremap_resource(pdev, 2);
  213. if (!IS_ERR(addr))
  214. punit_ipcdev->base[ISPDRIVER_IPC][BASE_DATA] = addr;
  215. addr = devm_platform_ioremap_resource(pdev, 3);
  216. if (!IS_ERR(addr))
  217. punit_ipcdev->base[ISPDRIVER_IPC][BASE_IFACE] = addr;
  218. addr = devm_platform_ioremap_resource(pdev, 4);
  219. if (!IS_ERR(addr))
  220. punit_ipcdev->base[GTDRIVER_IPC][BASE_DATA] = addr;
  221. addr = devm_platform_ioremap_resource(pdev, 5);
  222. if (!IS_ERR(addr))
  223. punit_ipcdev->base[GTDRIVER_IPC][BASE_IFACE] = addr;
  224. return 0;
  225. }
  226. static int intel_punit_ipc_probe(struct platform_device *pdev)
  227. {
  228. int irq, ret;
  229. punit_ipcdev = devm_kzalloc(&pdev->dev,
  230. sizeof(*punit_ipcdev), GFP_KERNEL);
  231. if (!punit_ipcdev)
  232. return -ENOMEM;
  233. platform_set_drvdata(pdev, punit_ipcdev);
  234. irq = platform_get_irq_optional(pdev, 0);
  235. if (irq < 0) {
  236. dev_warn(&pdev->dev, "Invalid IRQ, using polling mode\n");
  237. } else {
  238. ret = devm_request_irq(&pdev->dev, irq, intel_punit_ioc,
  239. IRQF_NO_SUSPEND, "intel_punit_ipc",
  240. &punit_ipcdev);
  241. if (ret) {
  242. dev_err(&pdev->dev, "Failed to request irq: %d\n", irq);
  243. return ret;
  244. }
  245. punit_ipcdev->irq = irq;
  246. }
  247. ret = intel_punit_get_bars(pdev);
  248. if (ret)
  249. return ret;
  250. punit_ipcdev->dev = &pdev->dev;
  251. mutex_init(&punit_ipcdev->lock);
  252. init_completion(&punit_ipcdev->cmd_complete);
  253. return 0;
  254. }
  255. static int intel_punit_ipc_remove(struct platform_device *pdev)
  256. {
  257. return 0;
  258. }
  259. static const struct acpi_device_id punit_ipc_acpi_ids[] = {
  260. { "INT34D4", 0 },
  261. { }
  262. };
  263. MODULE_DEVICE_TABLE(acpi, punit_ipc_acpi_ids);
  264. static struct platform_driver intel_punit_ipc_driver = {
  265. .probe = intel_punit_ipc_probe,
  266. .remove = intel_punit_ipc_remove,
  267. .driver = {
  268. .name = "intel_punit_ipc",
  269. .acpi_match_table = punit_ipc_acpi_ids,
  270. },
  271. };
  272. static int __init intel_punit_ipc_init(void)
  273. {
  274. return platform_driver_register(&intel_punit_ipc_driver);
  275. }
  276. static void __exit intel_punit_ipc_exit(void)
  277. {
  278. platform_driver_unregister(&intel_punit_ipc_driver);
  279. }
  280. MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
  281. MODULE_DESCRIPTION("Intel P-Unit IPC driver");
  282. MODULE_LICENSE("GPL v2");
  283. /* Some modules are dependent on this, so init earlier */
  284. fs_initcall(intel_punit_ipc_init);
  285. module_exit(intel_punit_ipc_exit);