intel_pmc_core.h 9.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Intel Core SoC Power Management Controller Header File
  4. *
  5. * Copyright (c) 2016, Intel Corporation.
  6. * All Rights Reserved.
  7. *
  8. * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
  9. * Vishwanath Somayaji <vishwanath.somayaji@intel.com>
  10. */
  11. #ifndef PMC_CORE_H
  12. #define PMC_CORE_H
  13. #include <linux/bits.h>
  14. #define PMC_BASE_ADDR_DEFAULT 0xFE000000
  15. /* Sunrise Point Power Management Controller PCI Device ID */
  16. #define SPT_PMC_PCI_DEVICE_ID 0x9d21
  17. #define SPT_PMC_BASE_ADDR_OFFSET 0x48
  18. #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
  19. #define SPT_PMC_PM_CFG_OFFSET 0x18
  20. #define SPT_PMC_PM_STS_OFFSET 0x1c
  21. #define SPT_PMC_MTPMC_OFFSET 0x20
  22. #define SPT_PMC_MFPMC_OFFSET 0x38
  23. #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
  24. #define SPT_PMC_VRIC1_OFFSET 0x31c
  25. #define SPT_PMC_MPHY_CORE_STS_0 0x1143
  26. #define SPT_PMC_MPHY_CORE_STS_1 0x1142
  27. #define SPT_PMC_MPHY_COM_STS_0 0x1155
  28. #define SPT_PMC_MMIO_REG_LEN 0x1000
  29. #define SPT_PMC_SLP_S0_RES_COUNTER_STEP 0x68
  30. #define PMC_BASE_ADDR_MASK ~(SPT_PMC_MMIO_REG_LEN - 1)
  31. #define MTPMC_MASK 0xffff0000
  32. #define PPFEAR_MAX_NUM_ENTRIES 12
  33. #define SPT_PPFEAR_NUM_ENTRIES 5
  34. #define SPT_PMC_READ_DISABLE_BIT 0x16
  35. #define SPT_PMC_MSG_FULL_STS_BIT 0x18
  36. #define NUM_RETRIES 100
  37. #define SPT_NUM_IP_IGN_ALLOWED 17
  38. #define SPT_PMC_LTR_CUR_PLT 0x350
  39. #define SPT_PMC_LTR_CUR_ASLT 0x354
  40. #define SPT_PMC_LTR_SPA 0x360
  41. #define SPT_PMC_LTR_SPB 0x364
  42. #define SPT_PMC_LTR_SATA 0x368
  43. #define SPT_PMC_LTR_GBE 0x36C
  44. #define SPT_PMC_LTR_XHCI 0x370
  45. #define SPT_PMC_LTR_RESERVED 0x374
  46. #define SPT_PMC_LTR_ME 0x378
  47. #define SPT_PMC_LTR_EVA 0x37C
  48. #define SPT_PMC_LTR_SPC 0x380
  49. #define SPT_PMC_LTR_AZ 0x384
  50. #define SPT_PMC_LTR_LPSS 0x38C
  51. #define SPT_PMC_LTR_CAM 0x390
  52. #define SPT_PMC_LTR_SPD 0x394
  53. #define SPT_PMC_LTR_SPE 0x398
  54. #define SPT_PMC_LTR_ESPI 0x39C
  55. #define SPT_PMC_LTR_SCC 0x3A0
  56. #define SPT_PMC_LTR_ISH 0x3A4
  57. /* Sunrise Point: PGD PFET Enable Ack Status Registers */
  58. enum ppfear_regs {
  59. SPT_PMC_XRAM_PPFEAR0A = 0x590,
  60. SPT_PMC_XRAM_PPFEAR0B,
  61. SPT_PMC_XRAM_PPFEAR0C,
  62. SPT_PMC_XRAM_PPFEAR0D,
  63. SPT_PMC_XRAM_PPFEAR1A,
  64. };
  65. #define SPT_PMC_BIT_PMC BIT(0)
  66. #define SPT_PMC_BIT_OPI BIT(1)
  67. #define SPT_PMC_BIT_SPI BIT(2)
  68. #define SPT_PMC_BIT_XHCI BIT(3)
  69. #define SPT_PMC_BIT_SPA BIT(4)
  70. #define SPT_PMC_BIT_SPB BIT(5)
  71. #define SPT_PMC_BIT_SPC BIT(6)
  72. #define SPT_PMC_BIT_GBE BIT(7)
  73. #define SPT_PMC_BIT_SATA BIT(0)
  74. #define SPT_PMC_BIT_HDA_PGD0 BIT(1)
  75. #define SPT_PMC_BIT_HDA_PGD1 BIT(2)
  76. #define SPT_PMC_BIT_HDA_PGD2 BIT(3)
  77. #define SPT_PMC_BIT_HDA_PGD3 BIT(4)
  78. #define SPT_PMC_BIT_RSVD_0B BIT(5)
  79. #define SPT_PMC_BIT_LPSS BIT(6)
  80. #define SPT_PMC_BIT_LPC BIT(7)
  81. #define SPT_PMC_BIT_SMB BIT(0)
  82. #define SPT_PMC_BIT_ISH BIT(1)
  83. #define SPT_PMC_BIT_P2SB BIT(2)
  84. #define SPT_PMC_BIT_DFX BIT(3)
  85. #define SPT_PMC_BIT_SCC BIT(4)
  86. #define SPT_PMC_BIT_RSVD_0C BIT(5)
  87. #define SPT_PMC_BIT_FUSE BIT(6)
  88. #define SPT_PMC_BIT_CAMREA BIT(7)
  89. #define SPT_PMC_BIT_RSVD_0D BIT(0)
  90. #define SPT_PMC_BIT_USB3_OTG BIT(1)
  91. #define SPT_PMC_BIT_EXI BIT(2)
  92. #define SPT_PMC_BIT_CSE BIT(3)
  93. #define SPT_PMC_BIT_CSME_KVM BIT(4)
  94. #define SPT_PMC_BIT_CSME_PMT BIT(5)
  95. #define SPT_PMC_BIT_CSME_CLINK BIT(6)
  96. #define SPT_PMC_BIT_CSME_PTIO BIT(7)
  97. #define SPT_PMC_BIT_CSME_USBR BIT(0)
  98. #define SPT_PMC_BIT_CSME_SUSRAM BIT(1)
  99. #define SPT_PMC_BIT_CSME_SMT BIT(2)
  100. #define SPT_PMC_BIT_RSVD_1A BIT(3)
  101. #define SPT_PMC_BIT_CSME_SMS2 BIT(4)
  102. #define SPT_PMC_BIT_CSME_SMS1 BIT(5)
  103. #define SPT_PMC_BIT_CSME_RTC BIT(6)
  104. #define SPT_PMC_BIT_CSME_PSF BIT(7)
  105. #define SPT_PMC_BIT_MPHY_LANE0 BIT(0)
  106. #define SPT_PMC_BIT_MPHY_LANE1 BIT(1)
  107. #define SPT_PMC_BIT_MPHY_LANE2 BIT(2)
  108. #define SPT_PMC_BIT_MPHY_LANE3 BIT(3)
  109. #define SPT_PMC_BIT_MPHY_LANE4 BIT(4)
  110. #define SPT_PMC_BIT_MPHY_LANE5 BIT(5)
  111. #define SPT_PMC_BIT_MPHY_LANE6 BIT(6)
  112. #define SPT_PMC_BIT_MPHY_LANE7 BIT(7)
  113. #define SPT_PMC_BIT_MPHY_LANE8 BIT(0)
  114. #define SPT_PMC_BIT_MPHY_LANE9 BIT(1)
  115. #define SPT_PMC_BIT_MPHY_LANE10 BIT(2)
  116. #define SPT_PMC_BIT_MPHY_LANE11 BIT(3)
  117. #define SPT_PMC_BIT_MPHY_LANE12 BIT(4)
  118. #define SPT_PMC_BIT_MPHY_LANE13 BIT(5)
  119. #define SPT_PMC_BIT_MPHY_LANE14 BIT(6)
  120. #define SPT_PMC_BIT_MPHY_LANE15 BIT(7)
  121. #define SPT_PMC_BIT_MPHY_CMN_LANE0 BIT(0)
  122. #define SPT_PMC_BIT_MPHY_CMN_LANE1 BIT(1)
  123. #define SPT_PMC_BIT_MPHY_CMN_LANE2 BIT(2)
  124. #define SPT_PMC_BIT_MPHY_CMN_LANE3 BIT(3)
  125. #define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
  126. #define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
  127. /* Cannonlake Power Management Controller register offsets */
  128. #define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
  129. #define CNP_PMC_PM_CFG_OFFSET 0x1818
  130. #define CNP_PMC_SLP_S0_RES_COUNTER_OFFSET 0x193C
  131. #define CNP_PMC_LTR_IGNORE_OFFSET 0x1B0C
  132. /* Cannonlake: PGD PFET Enable Ack Status Register(s) start */
  133. #define CNP_PMC_HOST_PPFEAR0A 0x1D90
  134. #define CNP_PMC_LATCH_SLPS0_EVENTS BIT(31)
  135. #define CNP_PMC_MMIO_REG_LEN 0x2000
  136. #define CNP_PPFEAR_NUM_ENTRIES 8
  137. #define CNP_PMC_READ_DISABLE_BIT 22
  138. #define CNP_NUM_IP_IGN_ALLOWED 19
  139. #define CNP_PMC_LTR_CUR_PLT 0x1B50
  140. #define CNP_PMC_LTR_CUR_ASLT 0x1B54
  141. #define CNP_PMC_LTR_SPA 0x1B60
  142. #define CNP_PMC_LTR_SPB 0x1B64
  143. #define CNP_PMC_LTR_SATA 0x1B68
  144. #define CNP_PMC_LTR_GBE 0x1B6C
  145. #define CNP_PMC_LTR_XHCI 0x1B70
  146. #define CNP_PMC_LTR_RESERVED 0x1B74
  147. #define CNP_PMC_LTR_ME 0x1B78
  148. #define CNP_PMC_LTR_EVA 0x1B7C
  149. #define CNP_PMC_LTR_SPC 0x1B80
  150. #define CNP_PMC_LTR_AZ 0x1B84
  151. #define CNP_PMC_LTR_LPSS 0x1B8C
  152. #define CNP_PMC_LTR_CAM 0x1B90
  153. #define CNP_PMC_LTR_SPD 0x1B94
  154. #define CNP_PMC_LTR_SPE 0x1B98
  155. #define CNP_PMC_LTR_ESPI 0x1B9C
  156. #define CNP_PMC_LTR_SCC 0x1BA0
  157. #define CNP_PMC_LTR_ISH 0x1BA4
  158. #define CNP_PMC_LTR_CNV 0x1BF0
  159. #define CNP_PMC_LTR_EMMC 0x1BF4
  160. #define CNP_PMC_LTR_UFSX2 0x1BF8
  161. #define LTR_DECODED_VAL GENMASK(9, 0)
  162. #define LTR_DECODED_SCALE GENMASK(12, 10)
  163. #define LTR_REQ_SNOOP BIT(15)
  164. #define LTR_REQ_NONSNOOP BIT(31)
  165. #define ICL_PPFEAR_NUM_ENTRIES 9
  166. #define ICL_NUM_IP_IGN_ALLOWED 20
  167. #define ICL_PMC_LTR_WIGIG 0x1BFC
  168. #define ICL_PMC_SLP_S0_RES_COUNTER_STEP 0x64
  169. #define TGL_NUM_IP_IGN_ALLOWED 22
  170. #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A
  171. /*
  172. * Tigerlake Power Management Controller register offsets
  173. */
  174. #define TGL_LPM_EN_OFFSET 0x1C78
  175. #define TGL_LPM_RESIDENCY_OFFSET 0x1C80
  176. /* Tigerlake Low Power Mode debug registers */
  177. #define TGL_LPM_STATUS_OFFSET 0x1C3C
  178. #define TGL_LPM_LIVE_STATUS_OFFSET 0x1C5C
  179. const char *tgl_lpm_modes[] = {
  180. "S0i2.0",
  181. "S0i2.1",
  182. "S0i2.2",
  183. "S0i3.0",
  184. "S0i3.1",
  185. "S0i3.2",
  186. "S0i3.3",
  187. "S0i3.4",
  188. NULL
  189. };
  190. struct pmc_bit_map {
  191. const char *name;
  192. u32 bit_mask;
  193. };
  194. /**
  195. * struct pmc_reg_map - Structure used to define parameter unique to a
  196. PCH family
  197. * @pfear_sts: Maps name of IP block to PPFEAR* bit
  198. * @mphy_sts: Maps name of MPHY lane to MPHY status lane status bit
  199. * @pll_sts: Maps name of PLL to corresponding bit status
  200. * @slps0_dbg_maps: Array of SLP_S0_DBG* registers containing debug info
  201. * @ltr_show_sts: Maps PCH IP Names to their MMIO register offsets
  202. * @slp_s0_offset: PWRMBASE offset to read SLP_S0 residency
  203. * @ltr_ignore_offset: PWRMBASE offset to read/write LTR ignore bit
  204. * @regmap_length: Length of memory to map from PWRMBASE address to access
  205. * @ppfear0_offset: PWRMBASE offset to to read PPFEAR*
  206. * @ppfear_buckets: Number of 8 bits blocks to read all IP blocks from
  207. * PPFEAR
  208. * @pm_cfg_offset: PWRMBASE offset to PM_CFG register
  209. * @pm_read_disable_bit: Bit index to read PMC_READ_DISABLE
  210. * @slps0_dbg_offset: PWRMBASE offset to SLP_S0_DEBUG_REG*
  211. *
  212. * Each PCH has unique set of register offsets and bit indexes. This structure
  213. * captures them to have a common implementation.
  214. */
  215. struct pmc_reg_map {
  216. const struct pmc_bit_map **pfear_sts;
  217. const struct pmc_bit_map *mphy_sts;
  218. const struct pmc_bit_map *pll_sts;
  219. const struct pmc_bit_map **slps0_dbg_maps;
  220. const struct pmc_bit_map *ltr_show_sts;
  221. const struct pmc_bit_map *msr_sts;
  222. const struct pmc_bit_map **lpm_sts;
  223. const u32 slp_s0_offset;
  224. const int slp_s0_res_counter_step;
  225. const u32 ltr_ignore_offset;
  226. const int regmap_length;
  227. const u32 ppfear0_offset;
  228. const int ppfear_buckets;
  229. const u32 pm_cfg_offset;
  230. const int pm_read_disable_bit;
  231. const u32 slps0_dbg_offset;
  232. const u32 ltr_ignore_max;
  233. const u32 pm_vric1_offset;
  234. /* Low Power Mode registers */
  235. const char **lpm_modes;
  236. const u32 lpm_en_offset;
  237. const u32 lpm_residency_offset;
  238. const u32 lpm_status_offset;
  239. const u32 lpm_live_status_offset;
  240. };
  241. /**
  242. * struct pmc_dev - pmc device structure
  243. * @base_addr: contains pmc base address
  244. * @regbase: pointer to io-remapped memory location
  245. * @map: pointer to pmc_reg_map struct that contains platform
  246. * specific attributes
  247. * @dbgfs_dir: path to debugfs interface
  248. * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
  249. * used to read MPHY PG and PLL status are available
  250. * @mutex_lock: mutex to complete one transcation
  251. * @check_counters: On resume, check if counters are getting incremented
  252. * @pc10_counter: PC10 residency counter
  253. * @s0ix_counter: S0ix residency (step adjusted)
  254. *
  255. * pmc_dev contains info about power management controller device.
  256. */
  257. struct pmc_dev {
  258. u32 base_addr;
  259. void __iomem *regbase;
  260. const struct pmc_reg_map *map;
  261. struct dentry *dbgfs_dir;
  262. int pmc_xram_read_bit;
  263. struct mutex lock; /* generic mutex lock for PMC Core */
  264. bool check_counters; /* Check for counter increments on resume */
  265. u64 pc10_counter;
  266. u64 s0ix_counter;
  267. };
  268. #endif /* PMC_CORE_H */