pinctrl-zx296718.c 33 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 Sanechips Technology Co., Ltd.
  4. * Copyright 2017 Linaro Ltd.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/of.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_device.h>
  10. #include <linux/pinctrl/pinctrl.h>
  11. #include <linux/platform_device.h>
  12. #include "pinctrl-zx.h"
  13. #define TOP_REG0 0x00
  14. #define TOP_REG1 0x04
  15. #define TOP_REG2 0x08
  16. #define TOP_REG3 0x0c
  17. #define TOP_REG4 0x10
  18. #define TOP_REG5 0x14
  19. #define TOP_REG6 0x18
  20. #define TOP_REG7 0x1c
  21. #define TOP_REG8 0x20
  22. /*
  23. * The pin numbering starts from AON pins with reserved ones included,
  24. * so that register data like offset and bit position for AON pins can
  25. * be calculated from pin number.
  26. */
  27. enum zx296718_pin {
  28. /* aon_pmm_reg_0 */
  29. I2C3_SCL = 0,
  30. I2C3_SDA = 1,
  31. AON_RESERVED0 = 2,
  32. AON_RESERVED1 = 3,
  33. SEC_EN = 4,
  34. UART0_RXD = 5,
  35. UART0_TXD = 6,
  36. IR_IN = 7,
  37. SPI0_CLK = 8,
  38. SPI0_CS = 9,
  39. SPI0_TXD = 10,
  40. SPI0_RXD = 11,
  41. KEY_COL0 = 12,
  42. KEY_COL1 = 13,
  43. KEY_COL2 = 14,
  44. KEY_ROW0 = 15,
  45. /* aon_pmm_reg_1 */
  46. KEY_ROW1 = 16,
  47. KEY_ROW2 = 17,
  48. HDMI_SCL = 18,
  49. HDMI_SDA = 19,
  50. JTAG_TCK = 20,
  51. JTAG_TRSTN = 21,
  52. JTAG_TMS = 22,
  53. JTAG_TDI = 23,
  54. JTAG_TDO = 24,
  55. I2C0_SCL = 25,
  56. I2C0_SDA = 26,
  57. I2C1_SCL = 27,
  58. I2C1_SDA = 28,
  59. AON_RESERVED2 = 29,
  60. AON_RESERVED3 = 30,
  61. AON_RESERVED4 = 31,
  62. /* aon_pmm_reg_2 */
  63. SPI1_CLK = 32,
  64. SPI1_CS = 33,
  65. SPI1_TXD = 34,
  66. SPI1_RXD = 35,
  67. AON_RESERVED5 = 36,
  68. AON_RESERVED6 = 37,
  69. AUDIO_DET = 38,
  70. SPDIF_OUT = 39,
  71. HDMI_CEC = 40,
  72. HDMI_HPD = 41,
  73. GMAC_25M_OUT = 42,
  74. BOOT_SEL0 = 43,
  75. BOOT_SEL1 = 44,
  76. BOOT_SEL2 = 45,
  77. DEEP_SLEEP_OUT_N = 46,
  78. AON_RESERVED7 = 47,
  79. /* top_pmm_reg_0 */
  80. GMII_GTX_CLK = 48,
  81. GMII_TX_CLK = 49,
  82. GMII_TXD0 = 50,
  83. GMII_TXD1 = 51,
  84. GMII_TXD2 = 52,
  85. GMII_TXD3 = 53,
  86. GMII_TXD4 = 54,
  87. GMII_TXD5 = 55,
  88. GMII_TXD6 = 56,
  89. GMII_TXD7 = 57,
  90. GMII_TX_ER = 58,
  91. GMII_TX_EN = 59,
  92. GMII_RX_CLK = 60,
  93. GMII_RXD0 = 61,
  94. GMII_RXD1 = 62,
  95. GMII_RXD2 = 63,
  96. /* top_pmm_reg_1 */
  97. GMII_RXD3 = 64,
  98. GMII_RXD4 = 65,
  99. GMII_RXD5 = 66,
  100. GMII_RXD6 = 67,
  101. GMII_RXD7 = 68,
  102. GMII_RX_ER = 69,
  103. GMII_RX_DV = 70,
  104. GMII_COL = 71,
  105. GMII_CRS = 72,
  106. GMII_MDC = 73,
  107. GMII_MDIO = 74,
  108. SDIO1_CLK = 75,
  109. SDIO1_CMD = 76,
  110. SDIO1_DATA0 = 77,
  111. SDIO1_DATA1 = 78,
  112. SDIO1_DATA2 = 79,
  113. /* top_pmm_reg_2 */
  114. SDIO1_DATA3 = 80,
  115. SDIO1_CD = 81,
  116. SDIO1_WP = 82,
  117. USIM1_CD = 83,
  118. USIM1_CLK = 84,
  119. USIM1_RST = 85,
  120. /* top_pmm_reg_3 */
  121. USIM1_DATA = 86,
  122. SDIO0_CLK = 87,
  123. SDIO0_CMD = 88,
  124. SDIO0_DATA0 = 89,
  125. SDIO0_DATA1 = 90,
  126. SDIO0_DATA2 = 91,
  127. SDIO0_DATA3 = 92,
  128. SDIO0_CD = 93,
  129. SDIO0_WP = 94,
  130. /* top_pmm_reg_4 */
  131. TSI0_DATA0 = 95,
  132. SPINOR_CLK = 96,
  133. TSI2_DATA = 97,
  134. TSI2_CLK = 98,
  135. TSI2_SYNC = 99,
  136. TSI2_VALID = 100,
  137. SPINOR_CS = 101,
  138. SPINOR_DQ0 = 102,
  139. SPINOR_DQ1 = 103,
  140. SPINOR_DQ2 = 104,
  141. SPINOR_DQ3 = 105,
  142. VGA_HS = 106,
  143. VGA_VS = 107,
  144. TSI3_DATA = 108,
  145. /* top_pmm_reg_5 */
  146. TSI3_CLK = 109,
  147. TSI3_SYNC = 110,
  148. TSI3_VALID = 111,
  149. I2S1_WS = 112,
  150. I2S1_BCLK = 113,
  151. I2S1_MCLK = 114,
  152. I2S1_DIN0 = 115,
  153. I2S1_DOUT0 = 116,
  154. SPI3_CLK = 117,
  155. SPI3_CS = 118,
  156. SPI3_TXD = 119,
  157. NAND_LDO_MS18_SEL = 120,
  158. /* top_pmm_reg_6 */
  159. SPI3_RXD = 121,
  160. I2S0_MCLK = 122,
  161. I2S0_BCLK = 123,
  162. I2S0_WS = 124,
  163. I2S0_DIN0 = 125,
  164. I2S0_DOUT0 = 126,
  165. I2C5_SCL = 127,
  166. I2C5_SDA = 128,
  167. SPI2_CLK = 129,
  168. SPI2_CS = 130,
  169. SPI2_TXD = 131,
  170. /* top_pmm_reg_7 */
  171. SPI2_RXD = 132,
  172. NAND_WP_N = 133,
  173. NAND_PAGE_SIZE0 = 134,
  174. NAND_PAGE_SIZE1 = 135,
  175. NAND_ADDR_CYCLE = 136,
  176. NAND_RB0 = 137,
  177. NAND_RB1 = 138,
  178. NAND_RB2 = 139,
  179. NAND_RB3 = 140,
  180. /* top_pmm_reg_8 */
  181. GMAC_125M_IN = 141,
  182. GMAC_50M_OUT = 142,
  183. SPINOR_SSCLK_LOOPBACK = 143,
  184. SPINOR_SDIO1CLK_LOOPBACK = 144,
  185. };
  186. static const struct pinctrl_pin_desc zx296718_pins[] = {
  187. /* aon_pmm_reg_0 */
  188. AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0,
  189. AON_MUX(0x0, "ANMI"), /* anmi */
  190. AON_MUX(0x1, "AGPIO"), /* agpio29 */
  191. AON_MUX(0x2, "nonAON"), /* pin0 */
  192. AON_MUX(0x3, "EXT_INT"), /* int4 */
  193. TOP_MUX(0x0, "I2C3"), /* scl */
  194. TOP_MUX(0x1, "SPI2"), /* txd */
  195. TOP_MUX(0x2, "I2S1")), /* din0 */
  196. AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9,
  197. AON_MUX(0x0, "WD"), /* rst_b */
  198. AON_MUX(0x1, "AGPIO"), /* agpio30 */
  199. AON_MUX(0x2, "nonAON"), /* pin1 */
  200. AON_MUX(0x3, "EXT_INT"), /* int5 */
  201. TOP_MUX(0x0, "I2C3"), /* sda */
  202. TOP_MUX(0x1, "SPI2"), /* rxd */
  203. TOP_MUX(0x2, "I2S0")), /* mclk */
  204. ZX_RESERVED(AON_RESERVED0),
  205. ZX_RESERVED(AON_RESERVED1),
  206. AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0,
  207. AON_MUX(0x0, "SEC"), /* en */
  208. AON_MUX(0x1, "AGPIO"), /* agpio28 */
  209. AON_MUX(0x2, "nonAON"), /* pin3 */
  210. AON_MUX(0x3, "EXT_INT"), /* int7 */
  211. TOP_MUX(0x0, "I2C2"), /* sda */
  212. TOP_MUX(0x1, "SPI2")), /* cs */
  213. AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9,
  214. AON_MUX(0x0, "UART0"), /* rxd */
  215. AON_MUX(0x1, "AGPIO"), /* agpio20 */
  216. AON_MUX(0x2, "nonAON")), /* pin34 */
  217. AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18,
  218. AON_MUX(0x0, "UART0"), /* txd */
  219. AON_MUX(0x1, "AGPIO"), /* agpio21 */
  220. AON_MUX(0x2, "nonAON")), /* pin32 */
  221. AON_PIN(IR_IN, 0, 0, 0, 0x64, 0,
  222. AON_MUX(0x0, "IR"), /* in */
  223. AON_MUX(0x1, "AGPIO"), /* agpio0 */
  224. AON_MUX(0x2, "nonAON")), /* pin27 */
  225. AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9,
  226. AON_MUX(0x0, "EXT_INT"), /* int0 */
  227. AON_MUX(0x1, "AGPIO"), /* agpio23 */
  228. AON_MUX(0x2, "nonAON"), /* pin5 */
  229. AON_MUX(0x3, "PCU"), /* test6 */
  230. TOP_MUX(0x0, "SPI0"), /* clk */
  231. TOP_MUX(0x1, "ISP")), /* flash_trig */
  232. AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18,
  233. AON_MUX(0x0, "EXT_INT"), /* int1 */
  234. AON_MUX(0x1, "AGPIO"), /* agpio24 */
  235. AON_MUX(0x2, "nonAON"), /* pin6 */
  236. AON_MUX(0x3, "PCU"), /* test0 */
  237. TOP_MUX(0x0, "SPI0"), /* cs */
  238. TOP_MUX(0x1, "ISP")), /* prelight_trig */
  239. AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0,
  240. AON_MUX(0x0, "EXT_INT"), /* int2 */
  241. AON_MUX(0x1, "AGPIO"), /* agpio25 */
  242. AON_MUX(0x2, "nonAON"), /* pin7 */
  243. AON_MUX(0x3, "PCU"), /* test1 */
  244. TOP_MUX(0x0, "SPI0"), /* txd */
  245. TOP_MUX(0x1, "ISP")), /* shutter_trig */
  246. AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9,
  247. AON_MUX(0x0, "EXT_INT"), /* int3 */
  248. AON_MUX(0x1, "AGPIO"), /* agpio26 */
  249. AON_MUX(0x2, "nonAON"), /* pin8 */
  250. AON_MUX(0x3, "PCU"), /* test2 */
  251. TOP_MUX(0x0, "SPI0"), /* rxd */
  252. TOP_MUX(0x1, "ISP")), /* shutter_open */
  253. AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18,
  254. AON_MUX(0x0, "KEY"), /* col0 */
  255. AON_MUX(0x1, "AGPIO"), /* agpio5 */
  256. AON_MUX(0x2, "nonAON"), /* pin9 */
  257. AON_MUX(0x3, "PCU"), /* test3 */
  258. TOP_MUX(0x0, "UART3"), /* rxd */
  259. TOP_MUX(0x1, "I2S0")), /* din1 */
  260. AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0,
  261. AON_MUX(0x0, "KEY"), /* col1 */
  262. AON_MUX(0x1, "AGPIO"), /* agpio6 */
  263. AON_MUX(0x2, "nonAON"), /* pin10 */
  264. TOP_MUX(0x0, "UART3"), /* txd */
  265. TOP_MUX(0x1, "I2S0"), /* din2 */
  266. TOP_MUX(0x2, "VGA")), /* scl */
  267. AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9,
  268. AON_MUX(0x0, "KEY"), /* col2 */
  269. AON_MUX(0x1, "AGPIO"), /* agpio7 */
  270. AON_MUX(0x2, "nonAON"), /* pin11 */
  271. TOP_MUX(0x0, "PWM"), /* out1 */
  272. TOP_MUX(0x1, "I2S0"), /* din3 */
  273. TOP_MUX(0x2, "VGA")), /* sda */
  274. AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18,
  275. AON_MUX(0x0, "KEY"), /* row0 */
  276. AON_MUX(0x1, "AGPIO"), /* agpio8 */
  277. AON_MUX(0x2, "nonAON"), /* pin33 */
  278. AON_MUX(0x3, "WD")), /* rst_b */
  279. /* aon_pmm_reg_1 */
  280. AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0,
  281. AON_MUX(0x0, "KEY"), /* row1 */
  282. AON_MUX(0x1, "AGPIO"), /* agpio9 */
  283. AON_MUX(0x2, "nonAON"), /* pin12 */
  284. TOP_MUX(0x0, "LCD"), /* port0 lcd_te */
  285. TOP_MUX(0x1, "I2S0"), /* dout2 */
  286. TOP_MUX(0x2, "PWM"), /* out2 */
  287. TOP_MUX(0x3, "VGA")), /* hs1 */
  288. AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9,
  289. AON_MUX(0x0, "KEY"), /* row2 */
  290. AON_MUX(0x1, "AGPIO"), /* agpio10 */
  291. AON_MUX(0x2, "nonAON"), /* pin13 */
  292. TOP_MUX(0x0, "LCD"), /* port1 lcd_te */
  293. TOP_MUX(0x1, "I2S0"), /* dout3 */
  294. TOP_MUX(0x2, "PWM"), /* out3 */
  295. TOP_MUX(0x3, "VGA")), /* vs1 */
  296. AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18,
  297. AON_MUX(0x0, "PCU"), /* test7 */
  298. AON_MUX(0x1, "AGPIO"), /* agpio3 */
  299. AON_MUX(0x2, "nonAON"), /* pin14 */
  300. TOP_MUX(0x0, "HDMI"), /* scl */
  301. TOP_MUX(0x1, "UART3")), /* rxd */
  302. AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0,
  303. AON_MUX(0x0, "PCU"), /* test8 */
  304. AON_MUX(0x1, "AGPIO"), /* agpio4 */
  305. AON_MUX(0x2, "nonAON"), /* pin15 */
  306. TOP_MUX(0x0, "HDMI"), /* sda */
  307. TOP_MUX(0x1, "UART3")), /* txd */
  308. AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18,
  309. AON_MUX(0x0, "JTAG"), /* tck */
  310. AON_MUX(0x1, "AGPIO"), /* agpio11 */
  311. AON_MUX(0x2, "nonAON"), /* pin22 */
  312. AON_MUX(0x3, "EXT_INT"), /* int4 */
  313. TOP_MUX(0x0, "SPI4"), /* clk */
  314. TOP_MUX(0x1, "UART1")), /* rxd */
  315. AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0,
  316. AON_MUX(0x0, "JTAG"), /* trstn */
  317. AON_MUX(0x1, "AGPIO"), /* agpio12 */
  318. AON_MUX(0x2, "nonAON"), /* pin23 */
  319. AON_MUX(0x3, "EXT_INT"), /* int5 */
  320. TOP_MUX(0x0, "SPI4"), /* cs */
  321. TOP_MUX(0x1, "UART1")), /* txd */
  322. AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9,
  323. AON_MUX(0x0, "JTAG"), /* tms */
  324. AON_MUX(0x1, "AGPIO"), /* agpio13 */
  325. AON_MUX(0x2, "nonAON"), /* pin24 */
  326. AON_MUX(0x3, "EXT_INT"), /* int6 */
  327. TOP_MUX(0x0, "SPI4"), /* txd */
  328. TOP_MUX(0x1, "UART2")), /* rxd */
  329. AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18,
  330. AON_MUX(0x0, "JTAG"), /* tdi */
  331. AON_MUX(0x1, "AGPIO"), /* agpio14 */
  332. AON_MUX(0x2, "nonAON"), /* pin25 */
  333. AON_MUX(0x3, "EXT_INT"), /* int7 */
  334. TOP_MUX(0x0, "SPI4"), /* rxd */
  335. TOP_MUX(0x1, "UART2")), /* txd */
  336. AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0,
  337. AON_MUX(0x0, "JTAG"), /* tdo */
  338. AON_MUX(0x1, "AGPIO"), /* agpio15 */
  339. AON_MUX(0x2, "nonAON")), /* pin26 */
  340. AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9,
  341. AON_MUX(0x0, "I2C0"), /* scl */
  342. AON_MUX(0x1, "AGPIO"), /* agpio16 */
  343. AON_MUX(0x2, "nonAON")), /* pin28 */
  344. AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18,
  345. AON_MUX(0x0, "I2C0"), /* sda */
  346. AON_MUX(0x1, "AGPIO"), /* agpio17 */
  347. AON_MUX(0x2, "nonAON")), /* pin29 */
  348. AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0,
  349. AON_MUX(0x0, "I2C1"), /* scl */
  350. AON_MUX(0x1, "AGPIO"), /* agpio18 */
  351. AON_MUX(0x2, "nonAON"), /* pin30 */
  352. TOP_MUX(0x0, "LCD")), /* port0 lcd_te */
  353. AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9,
  354. AON_MUX(0x0, "I2C1"), /* sda */
  355. AON_MUX(0x1, "AGPIO"), /* agpio19 */
  356. AON_MUX(0x2, "nonAON"), /* pin31 */
  357. TOP_MUX(0x0, "LCD")), /* port1 lcd_te */
  358. ZX_RESERVED(AON_RESERVED2),
  359. ZX_RESERVED(AON_RESERVED3),
  360. ZX_RESERVED(AON_RESERVED4),
  361. /* aon_pmm_reg_2 */
  362. AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9,
  363. AON_MUX(0x0, "EXT_INT"), /* int0 */
  364. AON_MUX(0x1, "PCU"), /* test12 */
  365. AON_MUX(0x2, "nonAON"), /* pin39 */
  366. TOP_MUX(0x0, "SPI1"), /* clk */
  367. TOP_MUX(0x1, "PCM"), /* clk */
  368. TOP_MUX(0x2, "BGPIO"), /* gpio35 */
  369. TOP_MUX(0x3, "I2C4"), /* scl */
  370. TOP_MUX(0x4, "I2S1"), /* mclk */
  371. TOP_MUX(0x5, "ISP")), /* flash_trig */
  372. AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18,
  373. AON_MUX(0x0, "EXT_INT"), /* int1 */
  374. AON_MUX(0x1, "PCU"), /* test13 */
  375. AON_MUX(0x2, "nonAON"), /* pin40 */
  376. TOP_MUX(0x0, "SPI1"), /* cs */
  377. TOP_MUX(0x1, "PCM"), /* fs */
  378. TOP_MUX(0x2, "BGPIO"), /* gpio36 */
  379. TOP_MUX(0x3, "I2C4"), /* sda */
  380. TOP_MUX(0x4, "I2S1"), /* bclk */
  381. TOP_MUX(0x5, "ISP")), /* prelight_trig */
  382. AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0,
  383. AON_MUX(0x0, "EXT_INT"), /* int2 */
  384. AON_MUX(0x1, "PCU"), /* test14 */
  385. AON_MUX(0x2, "nonAON"), /* pin41 */
  386. TOP_MUX(0x0, "SPI1"), /* txd */
  387. TOP_MUX(0x1, "PCM"), /* txd */
  388. TOP_MUX(0x2, "BGPIO"), /* gpio37 */
  389. TOP_MUX(0x3, "UART5"), /* rxd */
  390. TOP_MUX(0x4, "I2S1"), /* ws */
  391. TOP_MUX(0x5, "ISP")), /* shutter_trig */
  392. AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9,
  393. AON_MUX(0x0, "EXT_INT"), /* int3 */
  394. AON_MUX(0x1, "PCU"), /* test15 */
  395. AON_MUX(0x2, "nonAON"), /* pin42 */
  396. TOP_MUX(0x0, "SPI1"), /* rxd */
  397. TOP_MUX(0x1, "PCM"), /* rxd */
  398. TOP_MUX(0x2, "BGPIO"), /* gpio38 */
  399. TOP_MUX(0x3, "UART5"), /* txd */
  400. TOP_MUX(0x4, "I2S1"), /* dout0 */
  401. TOP_MUX(0x5, "ISP")), /* shutter_open */
  402. ZX_RESERVED(AON_RESERVED5),
  403. ZX_RESERVED(AON_RESERVED6),
  404. AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18,
  405. AON_MUX(0x0, "PCU"), /* test4 */
  406. AON_MUX(0x1, "AGPIO"), /* agpio27 */
  407. AON_MUX(0x2, "nonAON"), /* pin2 */
  408. AON_MUX(0x3, "EXT_INT"), /* int16 */
  409. TOP_MUX(0x0, "AUDIO"), /* detect */
  410. TOP_MUX(0x1, "I2C2"), /* scl */
  411. TOP_MUX(0x2, "SPI2")), /* clk */
  412. AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9,
  413. AON_MUX(0x0, "PCU"), /* test5 */
  414. AON_MUX(0x1, "AGPIO"), /* agpio22 */
  415. AON_MUX(0x2, "nonAON"), /* pin4 */
  416. TOP_MUX(0x0, "SPDIF"), /* out */
  417. TOP_MUX(0x1, "PWM"), /* out0 */
  418. TOP_MUX(0x2, "ISP")), /* fl_trig */
  419. AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9,
  420. AON_MUX(0x0, "PCU"), /* test9 */
  421. AON_MUX(0x1, "AGPIO"), /* agpio1 */
  422. AON_MUX(0x2, "nonAON")), /* pin16 */
  423. AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18,
  424. AON_MUX(0x0, "PCU"), /* test10 */
  425. AON_MUX(0x1, "AGPIO"), /* agpio2 */
  426. AON_MUX(0x2, "nonAON")), /* pin17 */
  427. AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0,
  428. AON_MUX(0x0, "PCU"), /* test11 */
  429. AON_MUX(0x1, "AGPIO"), /* agpio31 */
  430. AON_MUX(0x2, "nonAON")), /* pin43 */
  431. AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9,
  432. AON_MUX(0x0, "BOOT"), /* sel0 */
  433. AON_MUX(0x1, "AGPIO"), /* agpio18 */
  434. AON_MUX(0x2, "nonAON")), /* pin18 */
  435. AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18,
  436. AON_MUX(0x0, "BOOT"), /* sel1 */
  437. AON_MUX(0x1, "AGPIO"), /* agpio19 */
  438. AON_MUX(0x2, "nonAON")), /* pin19 */
  439. AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0,
  440. AON_MUX(0x0, "BOOT"), /* sel2 */
  441. AON_MUX(0x1, "AGPIO"), /* agpio20 */
  442. AON_MUX(0x2, "nonAON")), /* pin20 */
  443. AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9,
  444. AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */
  445. AON_MUX(0x1, "AGPIO"), /* agpio21 */
  446. AON_MUX(0x2, "nonAON")), /* pin21 */
  447. ZX_RESERVED(AON_RESERVED7),
  448. /* top_pmm_reg_0 */
  449. TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0,
  450. TOP_MUX(0x0, "GMII"), /* gtx_clk */
  451. TOP_MUX(0x1, "DVI0"), /* clk */
  452. TOP_MUX(0x2, "BGPIO")), /* gpio0 */
  453. TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9,
  454. TOP_MUX(0x0, "GMII"), /* tx_clk */
  455. TOP_MUX(0x1, "DVI0"), /* vs */
  456. TOP_MUX(0x2, "BGPIO")), /* gpio1 */
  457. TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18,
  458. TOP_MUX(0x0, "GMII"), /* txd0 */
  459. TOP_MUX(0x1, "DVI0"), /* hs */
  460. TOP_MUX(0x2, "BGPIO")), /* gpio2 */
  461. TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0,
  462. TOP_MUX(0x0, "GMII"), /* txd1 */
  463. TOP_MUX(0x1, "DVI0"), /* d0 */
  464. TOP_MUX(0x2, "BGPIO")), /* gpio3 */
  465. TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9,
  466. TOP_MUX(0x0, "GMII"), /* txd2 */
  467. TOP_MUX(0x1, "DVI0"), /* d1 */
  468. TOP_MUX(0x2, "BGPIO")), /* gpio4 */
  469. TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18,
  470. TOP_MUX(0x0, "GMII"), /* txd3 */
  471. TOP_MUX(0x1, "DVI0"), /* d2 */
  472. TOP_MUX(0x2, "BGPIO")), /* gpio5 */
  473. TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0,
  474. TOP_MUX(0x0, "GMII"), /* txd4 */
  475. TOP_MUX(0x1, "DVI0"), /* d3 */
  476. TOP_MUX(0x2, "BGPIO")), /* gpio6 */
  477. TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9,
  478. TOP_MUX(0x0, "GMII"), /* txd5 */
  479. TOP_MUX(0x1, "DVI0"), /* d4 */
  480. TOP_MUX(0x2, "BGPIO")), /* gpio7 */
  481. TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18,
  482. TOP_MUX(0x0, "GMII"), /* txd6 */
  483. TOP_MUX(0x1, "DVI0"), /* d5 */
  484. TOP_MUX(0x2, "BGPIO")), /* gpio8 */
  485. TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0,
  486. TOP_MUX(0x0, "GMII"), /* txd7 */
  487. TOP_MUX(0x1, "DVI0"), /* d6 */
  488. TOP_MUX(0x2, "BGPIO")), /* gpio9 */
  489. TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9,
  490. TOP_MUX(0x0, "GMII"), /* tx_er */
  491. TOP_MUX(0x1, "DVI0"), /* d7 */
  492. TOP_MUX(0x2, "BGPIO")), /* gpio10 */
  493. TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18,
  494. TOP_MUX(0x0, "GMII"), /* tx_en */
  495. TOP_MUX(0x1, "DVI0"), /* d8 */
  496. TOP_MUX(0x3, "BGPIO")), /* gpio11 */
  497. TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0,
  498. TOP_MUX(0x0, "GMII"), /* rx_clk */
  499. TOP_MUX(0x1, "DVI0"), /* d9 */
  500. TOP_MUX(0x3, "BGPIO")), /* gpio12 */
  501. TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9,
  502. TOP_MUX(0x0, "GMII"), /* rxd0 */
  503. TOP_MUX(0x1, "DVI0"), /* d10 */
  504. TOP_MUX(0x3, "BGPIO")), /* gpio13 */
  505. TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18,
  506. TOP_MUX(0x0, "GMII"), /* rxd1 */
  507. TOP_MUX(0x1, "DVI0"), /* d11 */
  508. TOP_MUX(0x2, "BGPIO")), /* gpio14 */
  509. TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0,
  510. TOP_MUX(0x0, "GMII"), /* rxd2 */
  511. TOP_MUX(0x1, "DVI1"), /* clk */
  512. TOP_MUX(0x2, "BGPIO")), /* gpio15 */
  513. /* top_pmm_reg_1 */
  514. TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9,
  515. TOP_MUX(0x0, "GMII"), /* rxd3 */
  516. TOP_MUX(0x1, "DVI1"), /* hs */
  517. TOP_MUX(0x2, "BGPIO")), /* gpio16 */
  518. TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18,
  519. TOP_MUX(0x0, "GMII"), /* rxd4 */
  520. TOP_MUX(0x1, "DVI1"), /* vs */
  521. TOP_MUX(0x2, "BGPIO")), /* gpio17 */
  522. TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0,
  523. TOP_MUX(0x0, "GMII"), /* rxd5 */
  524. TOP_MUX(0x1, "DVI1"), /* d0 */
  525. TOP_MUX(0x2, "BGPIO"), /* gpio18 */
  526. TOP_MUX(0x3, "TSI0")), /* dat0 */
  527. TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9,
  528. TOP_MUX(0x0, "GMII"), /* rxd6 */
  529. TOP_MUX(0x1, "DVI1"), /* d1 */
  530. TOP_MUX(0x2, "BGPIO"), /* gpio19 */
  531. TOP_MUX(0x3, "TSI0")), /* clk */
  532. TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18,
  533. TOP_MUX(0x0, "GMII"), /* rxd7 */
  534. TOP_MUX(0x1, "DVI1"), /* d2 */
  535. TOP_MUX(0x2, "BGPIO"), /* gpio20 */
  536. TOP_MUX(0x3, "TSI0")), /* sync */
  537. TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0,
  538. TOP_MUX(0x0, "GMII"), /* rx_er */
  539. TOP_MUX(0x1, "DVI1"), /* d3 */
  540. TOP_MUX(0x2, "BGPIO"), /* gpio21 */
  541. TOP_MUX(0x3, "TSI0")), /* valid */
  542. TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9,
  543. TOP_MUX(0x0, "GMII"), /* rx_dv */
  544. TOP_MUX(0x1, "DVI1"), /* d4 */
  545. TOP_MUX(0x2, "BGPIO"), /* gpio22 */
  546. TOP_MUX(0x3, "TSI1")), /* dat0 */
  547. TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18,
  548. TOP_MUX(0x0, "GMII"), /* col */
  549. TOP_MUX(0x1, "DVI1"), /* d5 */
  550. TOP_MUX(0x2, "BGPIO"), /* gpio23 */
  551. TOP_MUX(0x3, "TSI1")), /* clk */
  552. TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0,
  553. TOP_MUX(0x0, "GMII"), /* crs */
  554. TOP_MUX(0x1, "DVI1"), /* d6 */
  555. TOP_MUX(0x2, "BGPIO"), /* gpio24 */
  556. TOP_MUX(0x3, "TSI1")), /* sync */
  557. TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9,
  558. TOP_MUX(0x0, "GMII"), /* mdc */
  559. TOP_MUX(0x1, "DVI1"), /* d7 */
  560. TOP_MUX(0x2, "BGPIO"), /* gpio25 */
  561. TOP_MUX(0x3, "TSI1")), /* valid */
  562. TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18,
  563. TOP_MUX(0x0, "GMII"), /* mdio */
  564. TOP_MUX(0x2, "BGPIO")), /* gpio26 */
  565. TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18,
  566. TOP_MUX(0x0, "SDIO1"), /* clk */
  567. TOP_MUX(0x1, "USIM0"), /* clk */
  568. TOP_MUX(0x2, "BGPIO"), /* gpio27 */
  569. TOP_MUX(0x3, "SPINOR")), /* clk */
  570. TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0,
  571. TOP_MUX(0x0, "SDIO1"), /* cmd */
  572. TOP_MUX(0x1, "USIM0"), /* cd */
  573. TOP_MUX(0x2, "BGPIO"), /* gpio28 */
  574. TOP_MUX(0x3, "SPINOR")), /* cs */
  575. TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9,
  576. TOP_MUX(0x0, "SDIO1"), /* dat0 */
  577. TOP_MUX(0x1, "USIM0"), /* rst */
  578. TOP_MUX(0x2, "BGPIO"), /* gpio29 */
  579. TOP_MUX(0x3, "SPINOR")), /* dq0 */
  580. TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18,
  581. TOP_MUX(0x0, "SDIO1"), /* dat1 */
  582. TOP_MUX(0x1, "USIM0"), /* data */
  583. TOP_MUX(0x2, "BGPIO"), /* gpio30 */
  584. TOP_MUX(0x3, "SPINOR")), /* dq1 */
  585. TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0,
  586. TOP_MUX(0x0, "SDIO1"), /* dat2 */
  587. TOP_MUX(0x1, "BGPIO"), /* gpio31 */
  588. TOP_MUX(0x2, "SPINOR")), /* dq2 */
  589. /* top_pmm_reg_2 */
  590. TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9,
  591. TOP_MUX(0x0, "SDIO1"), /* dat3 */
  592. TOP_MUX(0x1, "BGPIO"), /* gpio32 */
  593. TOP_MUX(0x2, "SPINOR")), /* dq3 */
  594. TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18,
  595. TOP_MUX(0x0, "SDIO1"), /* cd */
  596. TOP_MUX(0x1, "BGPIO"), /* gpio33 */
  597. TOP_MUX(0x2, "ISP")), /* fl_trig */
  598. TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0,
  599. TOP_MUX(0x0, "SDIO1"), /* wp */
  600. TOP_MUX(0x1, "BGPIO"), /* gpio34 */
  601. TOP_MUX(0x2, "ISP")), /* ref_clk */
  602. TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18,
  603. TOP_MUX(0x0, "USIM1"), /* cd */
  604. TOP_MUX(0x1, "UART4"), /* rxd */
  605. TOP_MUX(0x2, "BGPIO"), /* gpio39 */
  606. TOP_MUX(0x3, "SPI3"), /* clk */
  607. TOP_MUX(0x4, "I2S0"), /* bclk */
  608. TOP_MUX(0x5, "B_DVI0")), /* d8 */
  609. TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18,
  610. TOP_MUX(0x0, "USIM1"), /* clk */
  611. TOP_MUX(0x1, "UART4"), /* txd */
  612. TOP_MUX(0x2, "BGPIO"), /* gpio40 */
  613. TOP_MUX(0x3, "SPI3"), /* cs */
  614. TOP_MUX(0x4, "I2S0"), /* ws */
  615. TOP_MUX(0x5, "B_DVI0")), /* d9 */
  616. TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0,
  617. TOP_MUX(0x0, "USIM1"), /* rst */
  618. TOP_MUX(0x1, "UART4"), /* cts */
  619. TOP_MUX(0x2, "BGPIO"), /* gpio41 */
  620. TOP_MUX(0x3, "SPI3"), /* txd */
  621. TOP_MUX(0x4, "I2S0"), /* dout0 */
  622. TOP_MUX(0x5, "B_DVI0")), /* d10 */
  623. /* top_pmm_reg_3 */
  624. TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9,
  625. TOP_MUX(0x0, "USIM1"), /* dat */
  626. TOP_MUX(0x1, "UART4"), /* rst */
  627. TOP_MUX(0x2, "BGPIO"), /* gpio42 */
  628. TOP_MUX(0x3, "SPI3"), /* rxd */
  629. TOP_MUX(0x4, "I2S0"), /* din0 */
  630. TOP_MUX(0x5, "B_DVI0")), /* d11 */
  631. TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0,
  632. TOP_MUX(0x0, "SDIO0"), /* clk */
  633. TOP_MUX(0x1, "GPIO")), /* gpio43 */
  634. TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9,
  635. TOP_MUX(0x0, "SDIO0"), /* cmd */
  636. TOP_MUX(0x1, "GPIO")), /* gpio44 */
  637. TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18,
  638. TOP_MUX(0x0, "SDIO0"), /* dat0 */
  639. TOP_MUX(0x1, "GPIO")), /* gpio45 */
  640. TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0,
  641. TOP_MUX(0x0, "SDIO0"), /* dat1 */
  642. TOP_MUX(0x1, "GPIO")), /* gpio46 */
  643. TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9,
  644. TOP_MUX(0x0, "SDIO0"), /* dat2 */
  645. TOP_MUX(0x1, "GPIO")), /* gpio47 */
  646. TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18,
  647. TOP_MUX(0x0, "SDIO0"), /* dat3 */
  648. TOP_MUX(0x1, "GPIO")), /* gpio48 */
  649. TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0,
  650. TOP_MUX(0x0, "SDIO0"), /* cd */
  651. TOP_MUX(0x1, "GPIO")), /* gpio49 */
  652. TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9,
  653. TOP_MUX(0x0, "SDIO0"), /* wp */
  654. TOP_MUX(0x1, "GPIO")), /* gpio50 */
  655. /* top_pmm_reg_4 */
  656. TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18,
  657. TOP_MUX(0x0, "TSI0"), /* dat0 */
  658. TOP_MUX(0x1, "LCD"), /* clk */
  659. TOP_MUX(0x2, "BGPIO")), /* gpio51 */
  660. TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18,
  661. TOP_MUX(0x0, "SPINOR"), /* clk */
  662. TOP_MUX(0x1, "TSI0"), /* dat1 */
  663. TOP_MUX(0x2, "LCD"), /* dat0 */
  664. TOP_MUX(0x3, "BGPIO")), /* gpio52 */
  665. TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0,
  666. TOP_MUX(0x0, "TSI2"), /* dat */
  667. TOP_MUX(0x1, "TSI0"), /* dat2 */
  668. TOP_MUX(0x2, "LCD"), /* dat1 */
  669. TOP_MUX(0x3, "BGPIO")), /* gpio53 */
  670. TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9,
  671. TOP_MUX(0x0, "TSI2"), /* clk */
  672. TOP_MUX(0x1, "TSI0"), /* dat3 */
  673. TOP_MUX(0x2, "LCD"), /* dat2 */
  674. TOP_MUX(0x3, "BGPIO")), /* gpio54 */
  675. TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18,
  676. TOP_MUX(0x0, "TSI2"), /* sync */
  677. TOP_MUX(0x1, "TSI0"), /* dat4 */
  678. TOP_MUX(0x2, "LCD"), /* dat3 */
  679. TOP_MUX(0x3, "BGPIO")), /* gpio55 */
  680. TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0,
  681. TOP_MUX(0x0, "TSI2"), /* valid */
  682. TOP_MUX(0x1, "TSI0"), /* dat5 */
  683. TOP_MUX(0x2, "LCD"), /* dat4 */
  684. TOP_MUX(0x3, "BGPIO")), /* gpio56 */
  685. TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9,
  686. TOP_MUX(0x0, "SPINOR"), /* cs */
  687. TOP_MUX(0x1, "TSI0"), /* dat6 */
  688. TOP_MUX(0x2, "LCD"), /* dat5 */
  689. TOP_MUX(0x3, "BGPIO")), /* gpio57 */
  690. TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18,
  691. TOP_MUX(0x0, "SPINOR"), /* dq0 */
  692. TOP_MUX(0x1, "TSI0"), /* dat7 */
  693. TOP_MUX(0x2, "LCD"), /* dat6 */
  694. TOP_MUX(0x3, "BGPIO")), /* gpio58 */
  695. TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0,
  696. TOP_MUX(0x0, "SPINOR"), /* dq1 */
  697. TOP_MUX(0x1, "TSI0"), /* clk */
  698. TOP_MUX(0x2, "LCD"), /* dat7 */
  699. TOP_MUX(0x3, "BGPIO")), /* gpio59 */
  700. TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9,
  701. TOP_MUX(0x0, "SPINOR"), /* dq2 */
  702. TOP_MUX(0x1, "TSI0"), /* sync */
  703. TOP_MUX(0x2, "LCD"), /* dat8 */
  704. TOP_MUX(0x3, "BGPIO")), /* gpio60 */
  705. TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18,
  706. TOP_MUX(0x0, "SPINOR"), /* dq3 */
  707. TOP_MUX(0x1, "TSI0"), /* valid */
  708. TOP_MUX(0x2, "LCD"), /* dat9 */
  709. TOP_MUX(0x3, "BGPIO")), /* gpio61 */
  710. TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0,
  711. TOP_MUX(0x0, "VGA"), /* hs */
  712. TOP_MUX(0x1, "TSI1"), /* dat0 */
  713. TOP_MUX(0x2, "LCD"), /* dat10 */
  714. TOP_MUX(0x3, "BGPIO"), /* gpio62 */
  715. TOP_MUX(0x4, "I2S1"), /* din1 */
  716. TOP_MUX(0x5, "B_DVI0")), /* clk */
  717. TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9,
  718. TOP_MUX(0x0, "VGA"), /* vs0 */
  719. TOP_MUX(0x1, "TSI1"), /* dat1 */
  720. TOP_MUX(0x2, "LCD"), /* dat11 */
  721. TOP_MUX(0x3, "BGPIO"), /* gpio63 */
  722. TOP_MUX(0x4, "I2S1"), /* din2 */
  723. TOP_MUX(0x5, "B_DVI0")), /* vs */
  724. TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18,
  725. TOP_MUX(0x0, "TSI3"), /* dat */
  726. TOP_MUX(0x1, "TSI1"), /* dat2 */
  727. TOP_MUX(0x2, "LCD"), /* dat12 */
  728. TOP_MUX(0x3, "BGPIO"), /* gpio64 */
  729. TOP_MUX(0x4, "I2S1"), /* din3 */
  730. TOP_MUX(0x5, "B_DVI0")), /* hs */
  731. /* top_pmm_reg_5 */
  732. TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0,
  733. TOP_MUX(0x0, "TSI3"), /* clk */
  734. TOP_MUX(0x1, "TSI1"), /* dat3 */
  735. TOP_MUX(0x2, "LCD"), /* dat13 */
  736. TOP_MUX(0x3, "BGPIO"), /* gpio65 */
  737. TOP_MUX(0x4, "I2S1"), /* dout1 */
  738. TOP_MUX(0x5, "B_DVI0")), /* d0 */
  739. TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9,
  740. TOP_MUX(0x0, "TSI3"), /* sync */
  741. TOP_MUX(0x1, "TSI1"), /* dat4 */
  742. TOP_MUX(0x2, "LCD"), /* dat14 */
  743. TOP_MUX(0x3, "BGPIO"), /* gpio66 */
  744. TOP_MUX(0x4, "I2S1"), /* dout2 */
  745. TOP_MUX(0x5, "B_DVI0")), /* d1 */
  746. TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18,
  747. TOP_MUX(0x0, "TSI3"), /* valid */
  748. TOP_MUX(0x1, "TSI1"), /* dat5 */
  749. TOP_MUX(0x2, "LCD"), /* dat15 */
  750. TOP_MUX(0x3, "BGPIO"), /* gpio67 */
  751. TOP_MUX(0x4, "I2S1"), /* dout3 */
  752. TOP_MUX(0x5, "B_DVI0")), /* d2 */
  753. TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0,
  754. TOP_MUX(0x0, "I2S1"), /* ws */
  755. TOP_MUX(0x1, "TSI1"), /* dat6 */
  756. TOP_MUX(0x2, "LCD"), /* dat16 */
  757. TOP_MUX(0x3, "BGPIO"), /* gpio68 */
  758. TOP_MUX(0x4, "VGA"), /* scl */
  759. TOP_MUX(0x5, "B_DVI0")), /* d3 */
  760. TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9,
  761. TOP_MUX(0x0, "I2S1"), /* bclk */
  762. TOP_MUX(0x1, "TSI1"), /* dat7 */
  763. TOP_MUX(0x2, "LCD"), /* dat17 */
  764. TOP_MUX(0x3, "BGPIO"), /* gpio69 */
  765. TOP_MUX(0x4, "VGA"), /* sda */
  766. TOP_MUX(0x5, "B_DVI0")), /* d4 */
  767. TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18,
  768. TOP_MUX(0x0, "I2S1"), /* mclk */
  769. TOP_MUX(0x1, "TSI1"), /* clk */
  770. TOP_MUX(0x2, "LCD"), /* dat18 */
  771. TOP_MUX(0x3, "BGPIO")), /* gpio70 */
  772. TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0,
  773. TOP_MUX(0x0, "I2S1"), /* din0 */
  774. TOP_MUX(0x1, "TSI1"), /* sync */
  775. TOP_MUX(0x2, "LCD"), /* dat19 */
  776. TOP_MUX(0x3, "BGPIO")), /* gpio71 */
  777. TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9,
  778. TOP_MUX(0x0, "I2S1"), /* dout0 */
  779. TOP_MUX(0x1, "TSI1"), /* valid */
  780. TOP_MUX(0x2, "LCD"), /* dat20 */
  781. TOP_MUX(0x3, "BGPIO")), /* gpio72 */
  782. TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18,
  783. TOP_MUX(0x0, "SPI3"), /* clk */
  784. TOP_MUX(0x1, "TSO1"), /* clk */
  785. TOP_MUX(0x2, "LCD"), /* dat21 */
  786. TOP_MUX(0x3, "BGPIO"), /* gpio73 */
  787. TOP_MUX(0x4, "UART5"), /* rxd */
  788. TOP_MUX(0x5, "PCM"), /* fs */
  789. TOP_MUX(0x6, "I2S0"), /* din1 */
  790. TOP_MUX(0x7, "B_DVI0")), /* d5 */
  791. TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0,
  792. TOP_MUX(0x0, "SPI3"), /* cs */
  793. TOP_MUX(0x1, "TSO1"), /* dat0 */
  794. TOP_MUX(0x2, "LCD"), /* dat22 */
  795. TOP_MUX(0x3, "BGPIO"), /* gpio74 */
  796. TOP_MUX(0x4, "UART5"), /* txd */
  797. TOP_MUX(0x5, "PCM"), /* clk */
  798. TOP_MUX(0x6, "I2S0"), /* din2 */
  799. TOP_MUX(0x7, "B_DVI0")), /* d6 */
  800. TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9,
  801. TOP_MUX(0x0, "SPI3"), /* txd */
  802. TOP_MUX(0x1, "TSO1"), /* dat1 */
  803. TOP_MUX(0x2, "LCD"), /* dat23 */
  804. TOP_MUX(0x3, "BGPIO"), /* gpio75 */
  805. TOP_MUX(0x4, "UART5"), /* cts */
  806. TOP_MUX(0x5, "PCM"), /* txd */
  807. TOP_MUX(0x6, "I2S0"), /* din3 */
  808. TOP_MUX(0x7, "B_DVI0")), /* d7 */
  809. TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0,
  810. TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */
  811. TOP_MUX(0x1, "BGPIO")), /* gpio99 */
  812. /* top_pmm_reg_6 */
  813. TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18,
  814. TOP_MUX(0x0, "SPI3"), /* rxd */
  815. TOP_MUX(0x1, "TSO1"), /* dat2 */
  816. TOP_MUX(0x2, "LCD"), /* stvu_vsync */
  817. TOP_MUX(0x3, "BGPIO"), /* gpio76 */
  818. TOP_MUX(0x4, "UART5"), /* rts */
  819. TOP_MUX(0x5, "PCM"), /* rxd */
  820. TOP_MUX(0x6, "I2S0"), /* dout1 */
  821. TOP_MUX(0x7, "B_DVI1")), /* clk */
  822. TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0,
  823. TOP_MUX(0x0, "I2S0"), /* mclk */
  824. TOP_MUX(0x1, "TSO1"), /* dat3 */
  825. TOP_MUX(0x2, "LCD"), /* stvd */
  826. TOP_MUX(0x3, "BGPIO"), /* gpio77 */
  827. TOP_MUX(0x4, "USIM0"), /* cd */
  828. TOP_MUX(0x5, "B_DVI1")), /* vs */
  829. TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9,
  830. TOP_MUX(0x0, "I2S0"), /* bclk */
  831. TOP_MUX(0x1, "TSO1"), /* dat4 */
  832. TOP_MUX(0x2, "LCD"), /* sthl_hsync */
  833. TOP_MUX(0x3, "BGPIO"), /* gpio78 */
  834. TOP_MUX(0x4, "USIM0"), /* clk */
  835. TOP_MUX(0x5, "B_DVI1")), /* hs */
  836. TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18,
  837. TOP_MUX(0x0, "I2S0"), /* ws */
  838. TOP_MUX(0x1, "TSO1"), /* dat5 */
  839. TOP_MUX(0x2, "LCD"), /* sthr */
  840. TOP_MUX(0x3, "BGPIO"), /* gpio79 */
  841. TOP_MUX(0x4, "USIM0"), /* rst */
  842. TOP_MUX(0x5, "B_DVI1")), /* d0 */
  843. TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0,
  844. TOP_MUX(0x0, "I2S0"), /* din0 */
  845. TOP_MUX(0x1, "TSO1"), /* dat6 */
  846. TOP_MUX(0x2, "LCD"), /* oev_dataen */
  847. TOP_MUX(0x3, "BGPIO"), /* gpio80 */
  848. TOP_MUX(0x4, "USIM0"), /* dat */
  849. TOP_MUX(0x5, "B_DVI1")), /* d1 */
  850. TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9,
  851. TOP_MUX(0x0, "I2S0"), /* dout0 */
  852. TOP_MUX(0x1, "TSO1"), /* dat7 */
  853. TOP_MUX(0x2, "LCD"), /* ckv */
  854. TOP_MUX(0x3, "BGPIO")), /* gpio81 */
  855. TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18,
  856. TOP_MUX(0x0, "I2C5"), /* scl */
  857. TOP_MUX(0x1, "TSO1"), /* sync */
  858. TOP_MUX(0x2, "LCD"), /* ld */
  859. TOP_MUX(0x3, "BGPIO"), /* gpio82 */
  860. TOP_MUX(0x4, "PWM"), /* out2 */
  861. TOP_MUX(0x5, "I2S0"), /* dout2 */
  862. TOP_MUX(0x6, "B_DVI1")), /* d2 */
  863. TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0,
  864. TOP_MUX(0x0, "I2C5"), /* sda */
  865. TOP_MUX(0x1, "TSO1"), /* vld */
  866. TOP_MUX(0x2, "LCD"), /* pol */
  867. TOP_MUX(0x3, "BGPIO"), /* gpio83 */
  868. TOP_MUX(0x4, "PWM"), /* out3 */
  869. TOP_MUX(0x5, "I2S0"), /* dout3 */
  870. TOP_MUX(0x6, "B_DVI1")), /* d3 */
  871. TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9,
  872. TOP_MUX(0x0, "SPI2"), /* clk */
  873. TOP_MUX(0x1, "TSO0"), /* clk */
  874. TOP_MUX(0x2, "LCD"), /* degsl */
  875. TOP_MUX(0x3, "BGPIO"), /* gpio84 */
  876. TOP_MUX(0x4, "I2C4"), /* scl */
  877. TOP_MUX(0x5, "B_DVI1")), /* d4 */
  878. TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18,
  879. TOP_MUX(0x0, "SPI2"), /* cs */
  880. TOP_MUX(0x1, "TSO0"), /* data */
  881. TOP_MUX(0x2, "LCD"), /* rev */
  882. TOP_MUX(0x3, "BGPIO"), /* gpio85 */
  883. TOP_MUX(0x4, "I2C4"), /* sda */
  884. TOP_MUX(0x5, "B_DVI1")), /* d5 */
  885. TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0,
  886. TOP_MUX(0x0, "SPI2"), /* txd */
  887. TOP_MUX(0x1, "TSO0"), /* sync */
  888. TOP_MUX(0x2, "LCD"), /* u_d */
  889. TOP_MUX(0x3, "BGPIO"), /* gpio86 */
  890. TOP_MUX(0x4, "I2C4"), /* scl */
  891. TOP_MUX(0x5, "B_DVI1")), /* d6 */
  892. /* top_pmm_reg_7 */
  893. TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9,
  894. TOP_MUX(0x0, "SPI2"), /* rxd */
  895. TOP_MUX(0x1, "TSO0"), /* vld */
  896. TOP_MUX(0x2, "LCD"), /* r_l */
  897. TOP_MUX(0x3, "BGPIO"), /* gpio87 */
  898. TOP_MUX(0x4, "I2C3"), /* sda */
  899. TOP_MUX(0x5, "B_DVI1")), /* d7 */
  900. TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9,
  901. TOP_MUX(0x0, "NAND"), /* wp */
  902. TOP_MUX(0x1, "PWM"), /* out2 */
  903. TOP_MUX(0x2, "SPI2"), /* clk */
  904. TOP_MUX(0x3, "BGPIO"), /* gpio88 */
  905. TOP_MUX(0x4, "TSI0"), /* dat0 */
  906. TOP_MUX(0x5, "I2S1")), /* din1 */
  907. TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0,
  908. TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */
  909. TOP_MUX(0x1, "PWM"), /* out3 */
  910. TOP_MUX(0x2, "SPI2"), /* cs */
  911. TOP_MUX(0x3, "BGPIO"), /* gpio89 */
  912. TOP_MUX(0x4, "TSI0"), /* clk */
  913. TOP_MUX(0x5, "I2S1")), /* din2 */
  914. TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9,
  915. TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */
  916. TOP_MUX(0x1, "I2C4"), /* scl */
  917. TOP_MUX(0x2, "SPI2"), /* txd */
  918. TOP_MUX(0x3, "BGPIO"), /* gpio90 */
  919. TOP_MUX(0x4, "TSI0"), /* sync */
  920. TOP_MUX(0x5, "I2S1")), /* din3 */
  921. TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18,
  922. TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */
  923. TOP_MUX(0x1, "I2C4"), /* sda */
  924. TOP_MUX(0x2, "SPI2"), /* rxd */
  925. TOP_MUX(0x3, "BGPIO"), /* gpio91 */
  926. TOP_MUX(0x4, "TSI0"), /* valid */
  927. TOP_MUX(0x5, "I2S1")), /* dout1 */
  928. TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0,
  929. TOP_MUX(0x0, "NAND"), /* rdy_busy0 */
  930. TOP_MUX(0x1, "I2C2"), /* scl */
  931. TOP_MUX(0x2, "USIM0"), /* cd */
  932. TOP_MUX(0x3, "BGPIO"), /* gpio92 */
  933. TOP_MUX(0x4, "TSI1")), /* data0 */
  934. TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9,
  935. TOP_MUX(0x0, "NAND"), /* rdy_busy1 */
  936. TOP_MUX(0x1, "I2C2"), /* sda */
  937. TOP_MUX(0x2, "USIM0"), /* clk */
  938. TOP_MUX(0x3, "BGPIO"), /* gpio93 */
  939. TOP_MUX(0x4, "TSI1")), /* clk */
  940. TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18,
  941. TOP_MUX(0x0, "NAND"), /* rdy_busy2 */
  942. TOP_MUX(0x1, "UART5"), /* rxd */
  943. TOP_MUX(0x2, "USIM0"), /* rst */
  944. TOP_MUX(0x3, "BGPIO"), /* gpio94 */
  945. TOP_MUX(0x4, "TSI1"), /* sync */
  946. TOP_MUX(0x4, "I2S1")), /* dout2 */
  947. TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18,
  948. TOP_MUX(0x0, "NAND"), /* rdy_busy3 */
  949. TOP_MUX(0x1, "UART5"), /* txd */
  950. TOP_MUX(0x2, "USIM0"), /* dat */
  951. TOP_MUX(0x3, "BGPIO"), /* gpio95 */
  952. TOP_MUX(0x4, "TSI1"), /* valid */
  953. TOP_MUX(0x4, "I2S1")), /* dout3 */
  954. /* top_pmm_reg_8 */
  955. TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0,
  956. TOP_MUX(0x0, "GMII"), /* 125m_in */
  957. TOP_MUX(0x1, "USB2"), /* 0_drvvbus */
  958. TOP_MUX(0x2, "ISP"), /* ref_clk */
  959. TOP_MUX(0x3, "BGPIO")), /* gpio96 */
  960. TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9,
  961. TOP_MUX(0x0, "GMII"), /* 50m_out */
  962. TOP_MUX(0x1, "USB2"), /* 1_drvvbus */
  963. TOP_MUX(0x2, "BGPIO"), /* gpio97 */
  964. TOP_MUX(0x3, "USB2")), /* 0_drvvbus */
  965. TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9,
  966. TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */
  967. TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18,
  968. TOP_MUX(0x0, "SPINOR")), /* ssclk_i */
  969. };
  970. static struct zx_pinctrl_soc_info zx296718_pinctrl_info = {
  971. .pins = zx296718_pins,
  972. .npins = ARRAY_SIZE(zx296718_pins),
  973. };
  974. static int zx296718_pinctrl_probe(struct platform_device *pdev)
  975. {
  976. return zx_pinctrl_init(pdev, &zx296718_pinctrl_info);
  977. }
  978. static const struct of_device_id zx296718_pinctrl_match[] = {
  979. { .compatible = "zte,zx296718-pmm", },
  980. {}
  981. };
  982. MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match);
  983. static struct platform_driver zx296718_pinctrl_driver = {
  984. .probe = zx296718_pinctrl_probe,
  985. .driver = {
  986. .name = "zx296718-pinctrl",
  987. .of_match_table = zx296718_pinctrl_match,
  988. },
  989. };
  990. builtin_platform_driver(zx296718_pinctrl_driver);
  991. MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver");
  992. MODULE_LICENSE("GPL");