pinctrl-stm32.c 40 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Maxime Coquelin 2015
  4. * Copyright (C) STMicroelectronics 2017
  5. * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
  6. *
  7. * Heavily based on Mediatek's pinctrl driver
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/hwspinlock.h>
  12. #include <linux/io.h>
  13. #include <linux/irq.h>
  14. #include <linux/mfd/syscon.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_device.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/pinctrl/consumer.h>
  21. #include <linux/pinctrl/machine.h>
  22. #include <linux/pinctrl/pinconf.h>
  23. #include <linux/pinctrl/pinconf-generic.h>
  24. #include <linux/pinctrl/pinctrl.h>
  25. #include <linux/pinctrl/pinmux.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/regmap.h>
  28. #include <linux/reset.h>
  29. #include <linux/slab.h>
  30. #include "../core.h"
  31. #include "../pinconf.h"
  32. #include "../pinctrl-utils.h"
  33. #include "pinctrl-stm32.h"
  34. #define STM32_GPIO_MODER 0x00
  35. #define STM32_GPIO_TYPER 0x04
  36. #define STM32_GPIO_SPEEDR 0x08
  37. #define STM32_GPIO_PUPDR 0x0c
  38. #define STM32_GPIO_IDR 0x10
  39. #define STM32_GPIO_ODR 0x14
  40. #define STM32_GPIO_BSRR 0x18
  41. #define STM32_GPIO_LCKR 0x1c
  42. #define STM32_GPIO_AFRL 0x20
  43. #define STM32_GPIO_AFRH 0x24
  44. /* custom bitfield to backup pin status */
  45. #define STM32_GPIO_BKP_MODE_SHIFT 0
  46. #define STM32_GPIO_BKP_MODE_MASK GENMASK(1, 0)
  47. #define STM32_GPIO_BKP_ALT_SHIFT 2
  48. #define STM32_GPIO_BKP_ALT_MASK GENMASK(5, 2)
  49. #define STM32_GPIO_BKP_SPEED_SHIFT 6
  50. #define STM32_GPIO_BKP_SPEED_MASK GENMASK(7, 6)
  51. #define STM32_GPIO_BKP_PUPD_SHIFT 8
  52. #define STM32_GPIO_BKP_PUPD_MASK GENMASK(9, 8)
  53. #define STM32_GPIO_BKP_TYPE 10
  54. #define STM32_GPIO_BKP_VAL 11
  55. #define STM32_GPIO_PINS_PER_BANK 16
  56. #define STM32_GPIO_IRQ_LINE 16
  57. #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
  58. #define gpio_range_to_bank(chip) \
  59. container_of(chip, struct stm32_gpio_bank, range)
  60. #define HWSPNLCK_TIMEOUT 1000 /* usec */
  61. static const char * const stm32_gpio_functions[] = {
  62. "gpio", "af0", "af1",
  63. "af2", "af3", "af4",
  64. "af5", "af6", "af7",
  65. "af8", "af9", "af10",
  66. "af11", "af12", "af13",
  67. "af14", "af15", "analog",
  68. };
  69. struct stm32_pinctrl_group {
  70. const char *name;
  71. unsigned long config;
  72. unsigned pin;
  73. };
  74. struct stm32_gpio_bank {
  75. void __iomem *base;
  76. struct clk *clk;
  77. struct reset_control *rstc;
  78. spinlock_t lock;
  79. struct gpio_chip gpio_chip;
  80. struct pinctrl_gpio_range range;
  81. struct fwnode_handle *fwnode;
  82. struct irq_domain *domain;
  83. u32 bank_nr;
  84. u32 bank_ioport_nr;
  85. u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
  86. u8 irq_type[STM32_GPIO_PINS_PER_BANK];
  87. };
  88. struct stm32_pinctrl {
  89. struct device *dev;
  90. struct pinctrl_dev *pctl_dev;
  91. struct pinctrl_desc pctl_desc;
  92. struct stm32_pinctrl_group *groups;
  93. unsigned ngroups;
  94. const char **grp_names;
  95. struct stm32_gpio_bank *banks;
  96. unsigned nbanks;
  97. const struct stm32_pinctrl_match_data *match_data;
  98. struct irq_domain *domain;
  99. struct regmap *regmap;
  100. struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
  101. struct hwspinlock *hwlock;
  102. struct stm32_desc_pin *pins;
  103. u32 npins;
  104. u32 pkg;
  105. u16 irqmux_map;
  106. spinlock_t irqmux_lock;
  107. };
  108. static inline int stm32_gpio_pin(int gpio)
  109. {
  110. return gpio % STM32_GPIO_PINS_PER_BANK;
  111. }
  112. static inline u32 stm32_gpio_get_mode(u32 function)
  113. {
  114. switch (function) {
  115. case STM32_PIN_GPIO:
  116. return 0;
  117. case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
  118. return 2;
  119. case STM32_PIN_ANALOG:
  120. return 3;
  121. }
  122. return 0;
  123. }
  124. static inline u32 stm32_gpio_get_alt(u32 function)
  125. {
  126. switch (function) {
  127. case STM32_PIN_GPIO:
  128. return 0;
  129. case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
  130. return function - 1;
  131. case STM32_PIN_ANALOG:
  132. return 0;
  133. }
  134. return 0;
  135. }
  136. static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
  137. u32 offset, u32 value)
  138. {
  139. bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
  140. bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
  141. }
  142. static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
  143. u32 mode, u32 alt)
  144. {
  145. bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
  146. STM32_GPIO_BKP_ALT_MASK);
  147. bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
  148. bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
  149. }
  150. static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
  151. u32 drive)
  152. {
  153. bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
  154. bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
  155. }
  156. static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
  157. u32 speed)
  158. {
  159. bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
  160. bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
  161. }
  162. static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
  163. u32 bias)
  164. {
  165. bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
  166. bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
  167. }
  168. /* GPIO functions */
  169. static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
  170. unsigned offset, int value)
  171. {
  172. stm32_gpio_backup_value(bank, offset, value);
  173. if (!value)
  174. offset += STM32_GPIO_PINS_PER_BANK;
  175. clk_enable(bank->clk);
  176. writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
  177. clk_disable(bank->clk);
  178. }
  179. static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
  180. {
  181. struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
  182. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  183. struct pinctrl_gpio_range *range;
  184. int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
  185. range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
  186. if (!range) {
  187. dev_err(pctl->dev, "pin %d not in range.\n", pin);
  188. return -EINVAL;
  189. }
  190. return pinctrl_gpio_request(chip->base + offset);
  191. }
  192. static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
  193. {
  194. pinctrl_gpio_free(chip->base + offset);
  195. }
  196. static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
  197. {
  198. struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
  199. int ret;
  200. clk_enable(bank->clk);
  201. ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
  202. clk_disable(bank->clk);
  203. return ret;
  204. }
  205. static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  206. {
  207. struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
  208. __stm32_gpio_set(bank, offset, value);
  209. }
  210. static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  211. {
  212. return pinctrl_gpio_direction_input(chip->base + offset);
  213. }
  214. static int stm32_gpio_direction_output(struct gpio_chip *chip,
  215. unsigned offset, int value)
  216. {
  217. struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
  218. __stm32_gpio_set(bank, offset, value);
  219. pinctrl_gpio_direction_output(chip->base + offset);
  220. return 0;
  221. }
  222. static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
  223. {
  224. struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
  225. struct irq_fwspec fwspec;
  226. fwspec.fwnode = bank->fwnode;
  227. fwspec.param_count = 2;
  228. fwspec.param[0] = offset;
  229. fwspec.param[1] = IRQ_TYPE_NONE;
  230. return irq_create_fwspec_mapping(&fwspec);
  231. }
  232. static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  233. {
  234. struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
  235. int pin = stm32_gpio_pin(offset);
  236. int ret;
  237. u32 mode, alt;
  238. stm32_pmx_get_mode(bank, pin, &mode, &alt);
  239. if ((alt == 0) && (mode == 0))
  240. ret = GPIO_LINE_DIRECTION_IN;
  241. else if ((alt == 0) && (mode == 1))
  242. ret = GPIO_LINE_DIRECTION_OUT;
  243. else
  244. ret = -EINVAL;
  245. return ret;
  246. }
  247. static const struct gpio_chip stm32_gpio_template = {
  248. .request = stm32_gpio_request,
  249. .free = stm32_gpio_free,
  250. .get = stm32_gpio_get,
  251. .set = stm32_gpio_set,
  252. .direction_input = stm32_gpio_direction_input,
  253. .direction_output = stm32_gpio_direction_output,
  254. .to_irq = stm32_gpio_to_irq,
  255. .get_direction = stm32_gpio_get_direction,
  256. .set_config = gpiochip_generic_config,
  257. };
  258. static void stm32_gpio_irq_trigger(struct irq_data *d)
  259. {
  260. struct stm32_gpio_bank *bank = d->domain->host_data;
  261. int level;
  262. /* If level interrupt type then retrig */
  263. level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
  264. if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
  265. (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
  266. irq_chip_retrigger_hierarchy(d);
  267. }
  268. static void stm32_gpio_irq_eoi(struct irq_data *d)
  269. {
  270. irq_chip_eoi_parent(d);
  271. stm32_gpio_irq_trigger(d);
  272. };
  273. static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
  274. {
  275. struct stm32_gpio_bank *bank = d->domain->host_data;
  276. u32 parent_type;
  277. switch (type) {
  278. case IRQ_TYPE_EDGE_RISING:
  279. case IRQ_TYPE_EDGE_FALLING:
  280. case IRQ_TYPE_EDGE_BOTH:
  281. parent_type = type;
  282. break;
  283. case IRQ_TYPE_LEVEL_HIGH:
  284. parent_type = IRQ_TYPE_EDGE_RISING;
  285. break;
  286. case IRQ_TYPE_LEVEL_LOW:
  287. parent_type = IRQ_TYPE_EDGE_FALLING;
  288. break;
  289. default:
  290. return -EINVAL;
  291. }
  292. bank->irq_type[d->hwirq] = type;
  293. return irq_chip_set_type_parent(d, parent_type);
  294. };
  295. static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
  296. {
  297. struct stm32_gpio_bank *bank = irq_data->domain->host_data;
  298. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  299. int ret;
  300. ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
  301. if (ret)
  302. return ret;
  303. ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
  304. if (ret) {
  305. dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
  306. irq_data->hwirq);
  307. return ret;
  308. }
  309. return 0;
  310. }
  311. static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
  312. {
  313. struct stm32_gpio_bank *bank = irq_data->domain->host_data;
  314. gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
  315. }
  316. static void stm32_gpio_irq_unmask(struct irq_data *d)
  317. {
  318. irq_chip_unmask_parent(d);
  319. stm32_gpio_irq_trigger(d);
  320. }
  321. static struct irq_chip stm32_gpio_irq_chip = {
  322. .name = "stm32gpio",
  323. .irq_eoi = stm32_gpio_irq_eoi,
  324. .irq_ack = irq_chip_ack_parent,
  325. .irq_mask = irq_chip_mask_parent,
  326. .irq_unmask = stm32_gpio_irq_unmask,
  327. .irq_set_type = stm32_gpio_set_type,
  328. .irq_set_wake = irq_chip_set_wake_parent,
  329. .irq_request_resources = stm32_gpio_irq_request_resources,
  330. .irq_release_resources = stm32_gpio_irq_release_resources,
  331. };
  332. static int stm32_gpio_domain_translate(struct irq_domain *d,
  333. struct irq_fwspec *fwspec,
  334. unsigned long *hwirq,
  335. unsigned int *type)
  336. {
  337. if ((fwspec->param_count != 2) ||
  338. (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
  339. return -EINVAL;
  340. *hwirq = fwspec->param[0];
  341. *type = fwspec->param[1];
  342. return 0;
  343. }
  344. static int stm32_gpio_domain_activate(struct irq_domain *d,
  345. struct irq_data *irq_data, bool reserve)
  346. {
  347. struct stm32_gpio_bank *bank = d->host_data;
  348. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  349. unsigned long flags;
  350. int ret = 0;
  351. /*
  352. * gpio irq mux is shared between several banks, a lock has to be done
  353. * to avoid overriding.
  354. */
  355. spin_lock_irqsave(&pctl->irqmux_lock, flags);
  356. if (pctl->hwlock) {
  357. ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
  358. HWSPNLCK_TIMEOUT);
  359. if (ret) {
  360. dev_err(pctl->dev, "Can't get hwspinlock\n");
  361. goto unlock;
  362. }
  363. }
  364. if (pctl->irqmux_map & BIT(irq_data->hwirq)) {
  365. dev_err(pctl->dev, "irq line %ld already requested.\n",
  366. irq_data->hwirq);
  367. ret = -EBUSY;
  368. if (pctl->hwlock)
  369. hwspin_unlock_in_atomic(pctl->hwlock);
  370. goto unlock;
  371. } else {
  372. pctl->irqmux_map |= BIT(irq_data->hwirq);
  373. }
  374. regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
  375. if (pctl->hwlock)
  376. hwspin_unlock_in_atomic(pctl->hwlock);
  377. unlock:
  378. spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
  379. return ret;
  380. }
  381. static void stm32_gpio_domain_deactivate(struct irq_domain *d,
  382. struct irq_data *irq_data)
  383. {
  384. struct stm32_gpio_bank *bank = d->host_data;
  385. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  386. unsigned long flags;
  387. spin_lock_irqsave(&pctl->irqmux_lock, flags);
  388. pctl->irqmux_map &= ~BIT(irq_data->hwirq);
  389. spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
  390. }
  391. static int stm32_gpio_domain_alloc(struct irq_domain *d,
  392. unsigned int virq,
  393. unsigned int nr_irqs, void *data)
  394. {
  395. struct stm32_gpio_bank *bank = d->host_data;
  396. struct irq_fwspec *fwspec = data;
  397. struct irq_fwspec parent_fwspec;
  398. irq_hw_number_t hwirq;
  399. hwirq = fwspec->param[0];
  400. parent_fwspec.fwnode = d->parent->fwnode;
  401. parent_fwspec.param_count = 2;
  402. parent_fwspec.param[0] = fwspec->param[0];
  403. parent_fwspec.param[1] = fwspec->param[1];
  404. irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
  405. bank);
  406. return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
  407. }
  408. static const struct irq_domain_ops stm32_gpio_domain_ops = {
  409. .translate = stm32_gpio_domain_translate,
  410. .alloc = stm32_gpio_domain_alloc,
  411. .free = irq_domain_free_irqs_common,
  412. .activate = stm32_gpio_domain_activate,
  413. .deactivate = stm32_gpio_domain_deactivate,
  414. };
  415. /* Pinctrl functions */
  416. static struct stm32_pinctrl_group *
  417. stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
  418. {
  419. int i;
  420. for (i = 0; i < pctl->ngroups; i++) {
  421. struct stm32_pinctrl_group *grp = pctl->groups + i;
  422. if (grp->pin == pin)
  423. return grp;
  424. }
  425. return NULL;
  426. }
  427. static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
  428. u32 pin_num, u32 fnum)
  429. {
  430. int i;
  431. for (i = 0; i < pctl->npins; i++) {
  432. const struct stm32_desc_pin *pin = pctl->pins + i;
  433. const struct stm32_desc_function *func = pin->functions;
  434. if (pin->pin.number != pin_num)
  435. continue;
  436. while (func && func->name) {
  437. if (func->num == fnum)
  438. return true;
  439. func++;
  440. }
  441. break;
  442. }
  443. return false;
  444. }
  445. static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
  446. u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
  447. struct pinctrl_map **map, unsigned *reserved_maps,
  448. unsigned *num_maps)
  449. {
  450. if (*num_maps == *reserved_maps)
  451. return -ENOSPC;
  452. (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
  453. (*map)[*num_maps].data.mux.group = grp->name;
  454. if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
  455. dev_err(pctl->dev, "invalid function %d on pin %d .\n",
  456. fnum, pin);
  457. return -EINVAL;
  458. }
  459. (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
  460. (*num_maps)++;
  461. return 0;
  462. }
  463. static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
  464. struct device_node *node,
  465. struct pinctrl_map **map,
  466. unsigned *reserved_maps,
  467. unsigned *num_maps)
  468. {
  469. struct stm32_pinctrl *pctl;
  470. struct stm32_pinctrl_group *grp;
  471. struct property *pins;
  472. u32 pinfunc, pin, func;
  473. unsigned long *configs;
  474. unsigned int num_configs;
  475. bool has_config = 0;
  476. unsigned reserve = 0;
  477. int num_pins, num_funcs, maps_per_pin, i, err = 0;
  478. pctl = pinctrl_dev_get_drvdata(pctldev);
  479. pins = of_find_property(node, "pinmux", NULL);
  480. if (!pins) {
  481. dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
  482. node);
  483. return -EINVAL;
  484. }
  485. err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
  486. &num_configs);
  487. if (err)
  488. return err;
  489. if (num_configs)
  490. has_config = 1;
  491. num_pins = pins->length / sizeof(u32);
  492. num_funcs = num_pins;
  493. maps_per_pin = 0;
  494. if (num_funcs)
  495. maps_per_pin++;
  496. if (has_config && num_pins >= 1)
  497. maps_per_pin++;
  498. if (!num_pins || !maps_per_pin) {
  499. err = -EINVAL;
  500. goto exit;
  501. }
  502. reserve = num_pins * maps_per_pin;
  503. err = pinctrl_utils_reserve_map(pctldev, map,
  504. reserved_maps, num_maps, reserve);
  505. if (err)
  506. goto exit;
  507. for (i = 0; i < num_pins; i++) {
  508. err = of_property_read_u32_index(node, "pinmux",
  509. i, &pinfunc);
  510. if (err)
  511. goto exit;
  512. pin = STM32_GET_PIN_NO(pinfunc);
  513. func = STM32_GET_PIN_FUNC(pinfunc);
  514. if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
  515. dev_err(pctl->dev, "invalid function.\n");
  516. err = -EINVAL;
  517. goto exit;
  518. }
  519. grp = stm32_pctrl_find_group_by_pin(pctl, pin);
  520. if (!grp) {
  521. dev_err(pctl->dev, "unable to match pin %d to group\n",
  522. pin);
  523. err = -EINVAL;
  524. goto exit;
  525. }
  526. err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
  527. reserved_maps, num_maps);
  528. if (err)
  529. goto exit;
  530. if (has_config) {
  531. err = pinctrl_utils_add_map_configs(pctldev, map,
  532. reserved_maps, num_maps, grp->name,
  533. configs, num_configs,
  534. PIN_MAP_TYPE_CONFIGS_GROUP);
  535. if (err)
  536. goto exit;
  537. }
  538. }
  539. exit:
  540. kfree(configs);
  541. return err;
  542. }
  543. static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
  544. struct device_node *np_config,
  545. struct pinctrl_map **map, unsigned *num_maps)
  546. {
  547. struct device_node *np;
  548. unsigned reserved_maps;
  549. int ret;
  550. *map = NULL;
  551. *num_maps = 0;
  552. reserved_maps = 0;
  553. for_each_child_of_node(np_config, np) {
  554. ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
  555. &reserved_maps, num_maps);
  556. if (ret < 0) {
  557. pinctrl_utils_free_map(pctldev, *map, *num_maps);
  558. of_node_put(np);
  559. return ret;
  560. }
  561. }
  562. return 0;
  563. }
  564. static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
  565. {
  566. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  567. return pctl->ngroups;
  568. }
  569. static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
  570. unsigned group)
  571. {
  572. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  573. return pctl->groups[group].name;
  574. }
  575. static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
  576. unsigned group,
  577. const unsigned **pins,
  578. unsigned *num_pins)
  579. {
  580. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  581. *pins = (unsigned *)&pctl->groups[group].pin;
  582. *num_pins = 1;
  583. return 0;
  584. }
  585. static const struct pinctrl_ops stm32_pctrl_ops = {
  586. .dt_node_to_map = stm32_pctrl_dt_node_to_map,
  587. .dt_free_map = pinctrl_utils_free_map,
  588. .get_groups_count = stm32_pctrl_get_groups_count,
  589. .get_group_name = stm32_pctrl_get_group_name,
  590. .get_group_pins = stm32_pctrl_get_group_pins,
  591. };
  592. /* Pinmux functions */
  593. static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
  594. {
  595. return ARRAY_SIZE(stm32_gpio_functions);
  596. }
  597. static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
  598. unsigned selector)
  599. {
  600. return stm32_gpio_functions[selector];
  601. }
  602. static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
  603. unsigned function,
  604. const char * const **groups,
  605. unsigned * const num_groups)
  606. {
  607. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  608. *groups = pctl->grp_names;
  609. *num_groups = pctl->ngroups;
  610. return 0;
  611. }
  612. static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
  613. int pin, u32 mode, u32 alt)
  614. {
  615. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  616. u32 val;
  617. int alt_shift = (pin % 8) * 4;
  618. int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
  619. unsigned long flags;
  620. int err = 0;
  621. clk_enable(bank->clk);
  622. spin_lock_irqsave(&bank->lock, flags);
  623. if (pctl->hwlock) {
  624. err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
  625. HWSPNLCK_TIMEOUT);
  626. if (err) {
  627. dev_err(pctl->dev, "Can't get hwspinlock\n");
  628. goto unlock;
  629. }
  630. }
  631. val = readl_relaxed(bank->base + alt_offset);
  632. val &= ~GENMASK(alt_shift + 3, alt_shift);
  633. val |= (alt << alt_shift);
  634. writel_relaxed(val, bank->base + alt_offset);
  635. val = readl_relaxed(bank->base + STM32_GPIO_MODER);
  636. val &= ~GENMASK(pin * 2 + 1, pin * 2);
  637. val |= mode << (pin * 2);
  638. writel_relaxed(val, bank->base + STM32_GPIO_MODER);
  639. if (pctl->hwlock)
  640. hwspin_unlock_in_atomic(pctl->hwlock);
  641. stm32_gpio_backup_mode(bank, pin, mode, alt);
  642. unlock:
  643. spin_unlock_irqrestore(&bank->lock, flags);
  644. clk_disable(bank->clk);
  645. return err;
  646. }
  647. void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
  648. u32 *alt)
  649. {
  650. u32 val;
  651. int alt_shift = (pin % 8) * 4;
  652. int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
  653. unsigned long flags;
  654. clk_enable(bank->clk);
  655. spin_lock_irqsave(&bank->lock, flags);
  656. val = readl_relaxed(bank->base + alt_offset);
  657. val &= GENMASK(alt_shift + 3, alt_shift);
  658. *alt = val >> alt_shift;
  659. val = readl_relaxed(bank->base + STM32_GPIO_MODER);
  660. val &= GENMASK(pin * 2 + 1, pin * 2);
  661. *mode = val >> (pin * 2);
  662. spin_unlock_irqrestore(&bank->lock, flags);
  663. clk_disable(bank->clk);
  664. }
  665. static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
  666. unsigned function,
  667. unsigned group)
  668. {
  669. bool ret;
  670. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  671. struct stm32_pinctrl_group *g = pctl->groups + group;
  672. struct pinctrl_gpio_range *range;
  673. struct stm32_gpio_bank *bank;
  674. u32 mode, alt;
  675. int pin;
  676. ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
  677. if (!ret) {
  678. dev_err(pctl->dev, "invalid function %d on group %d .\n",
  679. function, group);
  680. return -EINVAL;
  681. }
  682. range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
  683. if (!range) {
  684. dev_err(pctl->dev, "No gpio range defined.\n");
  685. return -EINVAL;
  686. }
  687. bank = gpiochip_get_data(range->gc);
  688. pin = stm32_gpio_pin(g->pin);
  689. mode = stm32_gpio_get_mode(function);
  690. alt = stm32_gpio_get_alt(function);
  691. return stm32_pmx_set_mode(bank, pin, mode, alt);
  692. }
  693. static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  694. struct pinctrl_gpio_range *range, unsigned gpio,
  695. bool input)
  696. {
  697. struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
  698. int pin = stm32_gpio_pin(gpio);
  699. return stm32_pmx_set_mode(bank, pin, !input, 0);
  700. }
  701. static const struct pinmux_ops stm32_pmx_ops = {
  702. .get_functions_count = stm32_pmx_get_funcs_cnt,
  703. .get_function_name = stm32_pmx_get_func_name,
  704. .get_function_groups = stm32_pmx_get_func_groups,
  705. .set_mux = stm32_pmx_set_mux,
  706. .gpio_set_direction = stm32_pmx_gpio_set_direction,
  707. .strict = true,
  708. };
  709. /* Pinconf functions */
  710. static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
  711. unsigned offset, u32 drive)
  712. {
  713. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  714. unsigned long flags;
  715. u32 val;
  716. int err = 0;
  717. clk_enable(bank->clk);
  718. spin_lock_irqsave(&bank->lock, flags);
  719. if (pctl->hwlock) {
  720. err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
  721. HWSPNLCK_TIMEOUT);
  722. if (err) {
  723. dev_err(pctl->dev, "Can't get hwspinlock\n");
  724. goto unlock;
  725. }
  726. }
  727. val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
  728. val &= ~BIT(offset);
  729. val |= drive << offset;
  730. writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
  731. if (pctl->hwlock)
  732. hwspin_unlock_in_atomic(pctl->hwlock);
  733. stm32_gpio_backup_driving(bank, offset, drive);
  734. unlock:
  735. spin_unlock_irqrestore(&bank->lock, flags);
  736. clk_disable(bank->clk);
  737. return err;
  738. }
  739. static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
  740. unsigned int offset)
  741. {
  742. unsigned long flags;
  743. u32 val;
  744. clk_enable(bank->clk);
  745. spin_lock_irqsave(&bank->lock, flags);
  746. val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
  747. val &= BIT(offset);
  748. spin_unlock_irqrestore(&bank->lock, flags);
  749. clk_disable(bank->clk);
  750. return (val >> offset);
  751. }
  752. static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
  753. unsigned offset, u32 speed)
  754. {
  755. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  756. unsigned long flags;
  757. u32 val;
  758. int err = 0;
  759. clk_enable(bank->clk);
  760. spin_lock_irqsave(&bank->lock, flags);
  761. if (pctl->hwlock) {
  762. err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
  763. HWSPNLCK_TIMEOUT);
  764. if (err) {
  765. dev_err(pctl->dev, "Can't get hwspinlock\n");
  766. goto unlock;
  767. }
  768. }
  769. val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
  770. val &= ~GENMASK(offset * 2 + 1, offset * 2);
  771. val |= speed << (offset * 2);
  772. writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
  773. if (pctl->hwlock)
  774. hwspin_unlock_in_atomic(pctl->hwlock);
  775. stm32_gpio_backup_speed(bank, offset, speed);
  776. unlock:
  777. spin_unlock_irqrestore(&bank->lock, flags);
  778. clk_disable(bank->clk);
  779. return err;
  780. }
  781. static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
  782. unsigned int offset)
  783. {
  784. unsigned long flags;
  785. u32 val;
  786. clk_enable(bank->clk);
  787. spin_lock_irqsave(&bank->lock, flags);
  788. val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
  789. val &= GENMASK(offset * 2 + 1, offset * 2);
  790. spin_unlock_irqrestore(&bank->lock, flags);
  791. clk_disable(bank->clk);
  792. return (val >> (offset * 2));
  793. }
  794. static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
  795. unsigned offset, u32 bias)
  796. {
  797. struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
  798. unsigned long flags;
  799. u32 val;
  800. int err = 0;
  801. clk_enable(bank->clk);
  802. spin_lock_irqsave(&bank->lock, flags);
  803. if (pctl->hwlock) {
  804. err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
  805. HWSPNLCK_TIMEOUT);
  806. if (err) {
  807. dev_err(pctl->dev, "Can't get hwspinlock\n");
  808. goto unlock;
  809. }
  810. }
  811. val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
  812. val &= ~GENMASK(offset * 2 + 1, offset * 2);
  813. val |= bias << (offset * 2);
  814. writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
  815. if (pctl->hwlock)
  816. hwspin_unlock_in_atomic(pctl->hwlock);
  817. stm32_gpio_backup_bias(bank, offset, bias);
  818. unlock:
  819. spin_unlock_irqrestore(&bank->lock, flags);
  820. clk_disable(bank->clk);
  821. return err;
  822. }
  823. static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
  824. unsigned int offset)
  825. {
  826. unsigned long flags;
  827. u32 val;
  828. clk_enable(bank->clk);
  829. spin_lock_irqsave(&bank->lock, flags);
  830. val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
  831. val &= GENMASK(offset * 2 + 1, offset * 2);
  832. spin_unlock_irqrestore(&bank->lock, flags);
  833. clk_disable(bank->clk);
  834. return (val >> (offset * 2));
  835. }
  836. static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
  837. unsigned int offset, bool dir)
  838. {
  839. unsigned long flags;
  840. u32 val;
  841. clk_enable(bank->clk);
  842. spin_lock_irqsave(&bank->lock, flags);
  843. if (dir)
  844. val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
  845. BIT(offset));
  846. else
  847. val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
  848. BIT(offset));
  849. spin_unlock_irqrestore(&bank->lock, flags);
  850. clk_disable(bank->clk);
  851. return val;
  852. }
  853. static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
  854. unsigned int pin, enum pin_config_param param,
  855. enum pin_config_param arg)
  856. {
  857. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  858. struct pinctrl_gpio_range *range;
  859. struct stm32_gpio_bank *bank;
  860. int offset, ret = 0;
  861. range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
  862. if (!range) {
  863. dev_err(pctl->dev, "No gpio range defined.\n");
  864. return -EINVAL;
  865. }
  866. bank = gpiochip_get_data(range->gc);
  867. offset = stm32_gpio_pin(pin);
  868. switch (param) {
  869. case PIN_CONFIG_DRIVE_PUSH_PULL:
  870. ret = stm32_pconf_set_driving(bank, offset, 0);
  871. break;
  872. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  873. ret = stm32_pconf_set_driving(bank, offset, 1);
  874. break;
  875. case PIN_CONFIG_SLEW_RATE:
  876. ret = stm32_pconf_set_speed(bank, offset, arg);
  877. break;
  878. case PIN_CONFIG_BIAS_DISABLE:
  879. ret = stm32_pconf_set_bias(bank, offset, 0);
  880. break;
  881. case PIN_CONFIG_BIAS_PULL_UP:
  882. ret = stm32_pconf_set_bias(bank, offset, 1);
  883. break;
  884. case PIN_CONFIG_BIAS_PULL_DOWN:
  885. ret = stm32_pconf_set_bias(bank, offset, 2);
  886. break;
  887. case PIN_CONFIG_OUTPUT:
  888. __stm32_gpio_set(bank, offset, arg);
  889. ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
  890. break;
  891. default:
  892. ret = -ENOTSUPP;
  893. }
  894. return ret;
  895. }
  896. static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
  897. unsigned group,
  898. unsigned long *config)
  899. {
  900. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  901. *config = pctl->groups[group].config;
  902. return 0;
  903. }
  904. static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
  905. unsigned long *configs, unsigned num_configs)
  906. {
  907. struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  908. struct stm32_pinctrl_group *g = &pctl->groups[group];
  909. int i, ret;
  910. for (i = 0; i < num_configs; i++) {
  911. mutex_lock(&pctldev->mutex);
  912. ret = stm32_pconf_parse_conf(pctldev, g->pin,
  913. pinconf_to_config_param(configs[i]),
  914. pinconf_to_config_argument(configs[i]));
  915. mutex_unlock(&pctldev->mutex);
  916. if (ret < 0)
  917. return ret;
  918. g->config = configs[i];
  919. }
  920. return 0;
  921. }
  922. static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  923. unsigned long *configs, unsigned int num_configs)
  924. {
  925. int i, ret;
  926. for (i = 0; i < num_configs; i++) {
  927. ret = stm32_pconf_parse_conf(pctldev, pin,
  928. pinconf_to_config_param(configs[i]),
  929. pinconf_to_config_argument(configs[i]));
  930. if (ret < 0)
  931. return ret;
  932. }
  933. return 0;
  934. }
  935. static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
  936. struct seq_file *s,
  937. unsigned int pin)
  938. {
  939. struct pinctrl_gpio_range *range;
  940. struct stm32_gpio_bank *bank;
  941. int offset;
  942. u32 mode, alt, drive, speed, bias;
  943. static const char * const modes[] = {
  944. "input", "output", "alternate", "analog" };
  945. static const char * const speeds[] = {
  946. "low", "medium", "high", "very high" };
  947. static const char * const biasing[] = {
  948. "floating", "pull up", "pull down", "" };
  949. bool val;
  950. range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
  951. if (!range)
  952. return;
  953. bank = gpiochip_get_data(range->gc);
  954. offset = stm32_gpio_pin(pin);
  955. stm32_pmx_get_mode(bank, offset, &mode, &alt);
  956. bias = stm32_pconf_get_bias(bank, offset);
  957. seq_printf(s, "%s ", modes[mode]);
  958. switch (mode) {
  959. /* input */
  960. case 0:
  961. val = stm32_pconf_get(bank, offset, true);
  962. seq_printf(s, "- %s - %s",
  963. val ? "high" : "low",
  964. biasing[bias]);
  965. break;
  966. /* output */
  967. case 1:
  968. drive = stm32_pconf_get_driving(bank, offset);
  969. speed = stm32_pconf_get_speed(bank, offset);
  970. val = stm32_pconf_get(bank, offset, false);
  971. seq_printf(s, "- %s - %s - %s - %s %s",
  972. val ? "high" : "low",
  973. drive ? "open drain" : "push pull",
  974. biasing[bias],
  975. speeds[speed], "speed");
  976. break;
  977. /* alternate */
  978. case 2:
  979. drive = stm32_pconf_get_driving(bank, offset);
  980. speed = stm32_pconf_get_speed(bank, offset);
  981. seq_printf(s, "%d - %s - %s - %s %s", alt,
  982. drive ? "open drain" : "push pull",
  983. biasing[bias],
  984. speeds[speed], "speed");
  985. break;
  986. /* analog */
  987. case 3:
  988. break;
  989. }
  990. }
  991. static const struct pinconf_ops stm32_pconf_ops = {
  992. .pin_config_group_get = stm32_pconf_group_get,
  993. .pin_config_group_set = stm32_pconf_group_set,
  994. .pin_config_set = stm32_pconf_set,
  995. .pin_config_dbg_show = stm32_pconf_dbg_show,
  996. };
  997. static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
  998. struct device_node *np)
  999. {
  1000. struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
  1001. int bank_ioport_nr;
  1002. struct pinctrl_gpio_range *range = &bank->range;
  1003. struct of_phandle_args args;
  1004. struct device *dev = pctl->dev;
  1005. struct resource res;
  1006. int npins = STM32_GPIO_PINS_PER_BANK;
  1007. int bank_nr, err, i = 0;
  1008. if (!IS_ERR(bank->rstc))
  1009. reset_control_deassert(bank->rstc);
  1010. if (of_address_to_resource(np, 0, &res))
  1011. return -ENODEV;
  1012. bank->base = devm_ioremap_resource(dev, &res);
  1013. if (IS_ERR(bank->base))
  1014. return PTR_ERR(bank->base);
  1015. err = clk_prepare(bank->clk);
  1016. if (err) {
  1017. dev_err(dev, "failed to prepare clk (%d)\n", err);
  1018. return err;
  1019. }
  1020. bank->gpio_chip = stm32_gpio_template;
  1021. of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
  1022. if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) {
  1023. bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
  1024. bank->gpio_chip.base = args.args[1];
  1025. /* get the last defined gpio line (offset + nb of pins) */
  1026. npins = args.args[0] + args.args[2];
  1027. while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args))
  1028. npins = max(npins, (int)(args.args[0] + args.args[2]));
  1029. } else {
  1030. bank_nr = pctl->nbanks;
  1031. bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
  1032. range->name = bank->gpio_chip.label;
  1033. range->id = bank_nr;
  1034. range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
  1035. range->base = range->id * STM32_GPIO_PINS_PER_BANK;
  1036. range->npins = npins;
  1037. range->gc = &bank->gpio_chip;
  1038. pinctrl_add_gpio_range(pctl->pctl_dev,
  1039. &pctl->banks[bank_nr].range);
  1040. }
  1041. if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr))
  1042. bank_ioport_nr = bank_nr;
  1043. bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
  1044. bank->gpio_chip.ngpio = npins;
  1045. bank->gpio_chip.of_node = np;
  1046. bank->gpio_chip.parent = dev;
  1047. bank->bank_nr = bank_nr;
  1048. bank->bank_ioport_nr = bank_ioport_nr;
  1049. spin_lock_init(&bank->lock);
  1050. /* create irq hierarchical domain */
  1051. bank->fwnode = of_node_to_fwnode(np);
  1052. bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
  1053. STM32_GPIO_IRQ_LINE, bank->fwnode,
  1054. &stm32_gpio_domain_ops, bank);
  1055. if (!bank->domain)
  1056. return -ENODEV;
  1057. err = gpiochip_add_data(&bank->gpio_chip, bank);
  1058. if (err) {
  1059. dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
  1060. return err;
  1061. }
  1062. dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
  1063. return 0;
  1064. }
  1065. static struct irq_domain *stm32_pctrl_get_irq_domain(struct device_node *np)
  1066. {
  1067. struct device_node *parent;
  1068. struct irq_domain *domain;
  1069. if (!of_find_property(np, "interrupt-parent", NULL))
  1070. return NULL;
  1071. parent = of_irq_find_parent(np);
  1072. if (!parent)
  1073. return ERR_PTR(-ENXIO);
  1074. domain = irq_find_host(parent);
  1075. if (!domain)
  1076. /* domain not registered yet */
  1077. return ERR_PTR(-EPROBE_DEFER);
  1078. return domain;
  1079. }
  1080. static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
  1081. struct stm32_pinctrl *pctl)
  1082. {
  1083. struct device_node *np = pdev->dev.of_node;
  1084. struct device *dev = &pdev->dev;
  1085. struct regmap *rm;
  1086. int offset, ret, i;
  1087. int mask, mask_width;
  1088. pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
  1089. if (IS_ERR(pctl->regmap))
  1090. return PTR_ERR(pctl->regmap);
  1091. rm = pctl->regmap;
  1092. ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
  1093. if (ret)
  1094. return ret;
  1095. ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
  1096. if (ret)
  1097. mask = SYSCFG_IRQMUX_MASK;
  1098. mask_width = fls(mask);
  1099. for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
  1100. struct reg_field mux;
  1101. mux.reg = offset + (i / 4) * 4;
  1102. mux.lsb = (i % 4) * mask_width;
  1103. mux.msb = mux.lsb + mask_width - 1;
  1104. dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
  1105. i, mux.reg, mux.lsb, mux.msb);
  1106. pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
  1107. if (IS_ERR(pctl->irqmux[i]))
  1108. return PTR_ERR(pctl->irqmux[i]);
  1109. }
  1110. return 0;
  1111. }
  1112. static int stm32_pctrl_build_state(struct platform_device *pdev)
  1113. {
  1114. struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
  1115. int i;
  1116. pctl->ngroups = pctl->npins;
  1117. /* Allocate groups */
  1118. pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
  1119. sizeof(*pctl->groups), GFP_KERNEL);
  1120. if (!pctl->groups)
  1121. return -ENOMEM;
  1122. /* We assume that one pin is one group, use pin name as group name. */
  1123. pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
  1124. sizeof(*pctl->grp_names), GFP_KERNEL);
  1125. if (!pctl->grp_names)
  1126. return -ENOMEM;
  1127. for (i = 0; i < pctl->npins; i++) {
  1128. const struct stm32_desc_pin *pin = pctl->pins + i;
  1129. struct stm32_pinctrl_group *group = pctl->groups + i;
  1130. group->name = pin->pin.name;
  1131. group->pin = pin->pin.number;
  1132. pctl->grp_names[i] = pin->pin.name;
  1133. }
  1134. return 0;
  1135. }
  1136. static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
  1137. struct stm32_desc_pin *pins)
  1138. {
  1139. const struct stm32_desc_pin *p;
  1140. int i, nb_pins_available = 0;
  1141. for (i = 0; i < pctl->match_data->npins; i++) {
  1142. p = pctl->match_data->pins + i;
  1143. if (pctl->pkg && !(pctl->pkg & p->pkg))
  1144. continue;
  1145. pins->pin = p->pin;
  1146. pins->functions = p->functions;
  1147. pins++;
  1148. nb_pins_available++;
  1149. }
  1150. pctl->npins = nb_pins_available;
  1151. return 0;
  1152. }
  1153. static void stm32_pctl_get_package(struct device_node *np,
  1154. struct stm32_pinctrl *pctl)
  1155. {
  1156. if (of_property_read_u32(np, "st,package", &pctl->pkg)) {
  1157. pctl->pkg = 0;
  1158. dev_warn(pctl->dev, "No package detected, use default one\n");
  1159. } else {
  1160. dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
  1161. }
  1162. }
  1163. int stm32_pctl_probe(struct platform_device *pdev)
  1164. {
  1165. struct device_node *np = pdev->dev.of_node;
  1166. struct device_node *child;
  1167. const struct of_device_id *match;
  1168. struct device *dev = &pdev->dev;
  1169. struct stm32_pinctrl *pctl;
  1170. struct pinctrl_pin_desc *pins;
  1171. int i, ret, hwlock_id, banks = 0;
  1172. if (!np)
  1173. return -EINVAL;
  1174. match = of_match_device(dev->driver->of_match_table, dev);
  1175. if (!match || !match->data)
  1176. return -EINVAL;
  1177. if (!of_find_property(np, "pins-are-numbered", NULL)) {
  1178. dev_err(dev, "only support pins-are-numbered format\n");
  1179. return -EINVAL;
  1180. }
  1181. pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
  1182. if (!pctl)
  1183. return -ENOMEM;
  1184. platform_set_drvdata(pdev, pctl);
  1185. /* check for IRQ controller (may require deferred probe) */
  1186. pctl->domain = stm32_pctrl_get_irq_domain(np);
  1187. if (IS_ERR(pctl->domain))
  1188. return PTR_ERR(pctl->domain);
  1189. /* hwspinlock is optional */
  1190. hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
  1191. if (hwlock_id < 0) {
  1192. if (hwlock_id == -EPROBE_DEFER)
  1193. return hwlock_id;
  1194. } else {
  1195. pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
  1196. }
  1197. spin_lock_init(&pctl->irqmux_lock);
  1198. pctl->dev = dev;
  1199. pctl->match_data = match->data;
  1200. /* get package information */
  1201. stm32_pctl_get_package(np, pctl);
  1202. pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
  1203. sizeof(*pctl->pins), GFP_KERNEL);
  1204. if (!pctl->pins)
  1205. return -ENOMEM;
  1206. ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
  1207. if (ret)
  1208. return ret;
  1209. ret = stm32_pctrl_build_state(pdev);
  1210. if (ret) {
  1211. dev_err(dev, "build state failed: %d\n", ret);
  1212. return -EINVAL;
  1213. }
  1214. if (pctl->domain) {
  1215. ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
  1216. if (ret)
  1217. return ret;
  1218. }
  1219. pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
  1220. GFP_KERNEL);
  1221. if (!pins)
  1222. return -ENOMEM;
  1223. for (i = 0; i < pctl->npins; i++)
  1224. pins[i] = pctl->pins[i].pin;
  1225. pctl->pctl_desc.name = dev_name(&pdev->dev);
  1226. pctl->pctl_desc.owner = THIS_MODULE;
  1227. pctl->pctl_desc.pins = pins;
  1228. pctl->pctl_desc.npins = pctl->npins;
  1229. pctl->pctl_desc.link_consumers = true;
  1230. pctl->pctl_desc.confops = &stm32_pconf_ops;
  1231. pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
  1232. pctl->pctl_desc.pmxops = &stm32_pmx_ops;
  1233. pctl->dev = &pdev->dev;
  1234. pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
  1235. pctl);
  1236. if (IS_ERR(pctl->pctl_dev)) {
  1237. dev_err(&pdev->dev, "Failed pinctrl registration\n");
  1238. return PTR_ERR(pctl->pctl_dev);
  1239. }
  1240. for_each_available_child_of_node(np, child)
  1241. if (of_property_read_bool(child, "gpio-controller"))
  1242. banks++;
  1243. if (!banks) {
  1244. dev_err(dev, "at least one GPIO bank is required\n");
  1245. return -EINVAL;
  1246. }
  1247. pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
  1248. GFP_KERNEL);
  1249. if (!pctl->banks)
  1250. return -ENOMEM;
  1251. i = 0;
  1252. for_each_available_child_of_node(np, child) {
  1253. struct stm32_gpio_bank *bank = &pctl->banks[i];
  1254. if (of_property_read_bool(child, "gpio-controller")) {
  1255. bank->rstc = of_reset_control_get_exclusive(child,
  1256. NULL);
  1257. if (PTR_ERR(bank->rstc) == -EPROBE_DEFER)
  1258. return -EPROBE_DEFER;
  1259. bank->clk = of_clk_get_by_name(child, NULL);
  1260. if (IS_ERR(bank->clk)) {
  1261. if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
  1262. dev_err(dev,
  1263. "failed to get clk (%ld)\n",
  1264. PTR_ERR(bank->clk));
  1265. return PTR_ERR(bank->clk);
  1266. }
  1267. i++;
  1268. }
  1269. }
  1270. for_each_available_child_of_node(np, child) {
  1271. if (of_property_read_bool(child, "gpio-controller")) {
  1272. ret = stm32_gpiolib_register_bank(pctl, child);
  1273. if (ret) {
  1274. of_node_put(child);
  1275. return ret;
  1276. }
  1277. pctl->nbanks++;
  1278. }
  1279. }
  1280. dev_info(dev, "Pinctrl STM32 initialized\n");
  1281. return 0;
  1282. }
  1283. static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
  1284. struct stm32_pinctrl *pctl, u32 pin)
  1285. {
  1286. const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
  1287. u32 val, alt, mode, offset = stm32_gpio_pin(pin);
  1288. struct pinctrl_gpio_range *range;
  1289. struct stm32_gpio_bank *bank;
  1290. bool pin_is_irq;
  1291. int ret;
  1292. range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
  1293. if (!range)
  1294. return 0;
  1295. pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
  1296. if (!desc || (!pin_is_irq && !desc->gpio_owner))
  1297. return 0;
  1298. bank = gpiochip_get_data(range->gc);
  1299. alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
  1300. alt >>= STM32_GPIO_BKP_ALT_SHIFT;
  1301. mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
  1302. mode >>= STM32_GPIO_BKP_MODE_SHIFT;
  1303. ret = stm32_pmx_set_mode(bank, offset, mode, alt);
  1304. if (ret)
  1305. return ret;
  1306. if (mode == 1) {
  1307. val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
  1308. val = val >> STM32_GPIO_BKP_VAL;
  1309. __stm32_gpio_set(bank, offset, val);
  1310. }
  1311. val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
  1312. val >>= STM32_GPIO_BKP_TYPE;
  1313. ret = stm32_pconf_set_driving(bank, offset, val);
  1314. if (ret)
  1315. return ret;
  1316. val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
  1317. val >>= STM32_GPIO_BKP_SPEED_SHIFT;
  1318. ret = stm32_pconf_set_speed(bank, offset, val);
  1319. if (ret)
  1320. return ret;
  1321. val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
  1322. val >>= STM32_GPIO_BKP_PUPD_SHIFT;
  1323. ret = stm32_pconf_set_bias(bank, offset, val);
  1324. if (ret)
  1325. return ret;
  1326. if (pin_is_irq)
  1327. regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
  1328. return 0;
  1329. }
  1330. int __maybe_unused stm32_pinctrl_resume(struct device *dev)
  1331. {
  1332. struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
  1333. struct stm32_pinctrl_group *g = pctl->groups;
  1334. int i;
  1335. for (i = 0; i < pctl->ngroups; i++, g++)
  1336. stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
  1337. return 0;
  1338. }