pinctrl-spear3xx.c 12 KB

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  1. /*
  2. * Driver for the ST Microelectronics SPEAr3xx pinmux
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Viresh Kumar <vireshk@kernel.org>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include "pinctrl-spear3xx.h"
  13. /* pins */
  14. static const struct pinctrl_pin_desc spear3xx_pins[] = {
  15. SPEAR_PIN_0_TO_101,
  16. };
  17. /* firda_pins */
  18. static const unsigned firda_pins[] = { 0, 1 };
  19. static struct spear_muxreg firda_muxreg[] = {
  20. {
  21. .reg = -1,
  22. .mask = PMX_FIRDA_MASK,
  23. .val = PMX_FIRDA_MASK,
  24. },
  25. };
  26. static struct spear_modemux firda_modemux[] = {
  27. {
  28. .modes = ~0,
  29. .muxregs = firda_muxreg,
  30. .nmuxregs = ARRAY_SIZE(firda_muxreg),
  31. },
  32. };
  33. struct spear_pingroup spear3xx_firda_pingroup = {
  34. .name = "firda_grp",
  35. .pins = firda_pins,
  36. .npins = ARRAY_SIZE(firda_pins),
  37. .modemuxs = firda_modemux,
  38. .nmodemuxs = ARRAY_SIZE(firda_modemux),
  39. };
  40. static const char *const firda_grps[] = { "firda_grp" };
  41. struct spear_function spear3xx_firda_function = {
  42. .name = "firda",
  43. .groups = firda_grps,
  44. .ngroups = ARRAY_SIZE(firda_grps),
  45. };
  46. /* i2c_pins */
  47. static const unsigned i2c_pins[] = { 4, 5 };
  48. static struct spear_muxreg i2c_muxreg[] = {
  49. {
  50. .reg = -1,
  51. .mask = PMX_I2C_MASK,
  52. .val = PMX_I2C_MASK,
  53. },
  54. };
  55. static struct spear_modemux i2c_modemux[] = {
  56. {
  57. .modes = ~0,
  58. .muxregs = i2c_muxreg,
  59. .nmuxregs = ARRAY_SIZE(i2c_muxreg),
  60. },
  61. };
  62. struct spear_pingroup spear3xx_i2c_pingroup = {
  63. .name = "i2c0_grp",
  64. .pins = i2c_pins,
  65. .npins = ARRAY_SIZE(i2c_pins),
  66. .modemuxs = i2c_modemux,
  67. .nmodemuxs = ARRAY_SIZE(i2c_modemux),
  68. };
  69. static const char *const i2c_grps[] = { "i2c0_grp" };
  70. struct spear_function spear3xx_i2c_function = {
  71. .name = "i2c0",
  72. .groups = i2c_grps,
  73. .ngroups = ARRAY_SIZE(i2c_grps),
  74. };
  75. /* ssp_cs_pins */
  76. static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
  77. static struct spear_muxreg ssp_cs_muxreg[] = {
  78. {
  79. .reg = -1,
  80. .mask = PMX_SSP_CS_MASK,
  81. .val = PMX_SSP_CS_MASK,
  82. },
  83. };
  84. static struct spear_modemux ssp_cs_modemux[] = {
  85. {
  86. .modes = ~0,
  87. .muxregs = ssp_cs_muxreg,
  88. .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
  89. },
  90. };
  91. struct spear_pingroup spear3xx_ssp_cs_pingroup = {
  92. .name = "ssp_cs_grp",
  93. .pins = ssp_cs_pins,
  94. .npins = ARRAY_SIZE(ssp_cs_pins),
  95. .modemuxs = ssp_cs_modemux,
  96. .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
  97. };
  98. static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
  99. struct spear_function spear3xx_ssp_cs_function = {
  100. .name = "ssp_cs",
  101. .groups = ssp_cs_grps,
  102. .ngroups = ARRAY_SIZE(ssp_cs_grps),
  103. };
  104. /* ssp_pins */
  105. static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
  106. static struct spear_muxreg ssp_muxreg[] = {
  107. {
  108. .reg = -1,
  109. .mask = PMX_SSP_MASK,
  110. .val = PMX_SSP_MASK,
  111. },
  112. };
  113. static struct spear_modemux ssp_modemux[] = {
  114. {
  115. .modes = ~0,
  116. .muxregs = ssp_muxreg,
  117. .nmuxregs = ARRAY_SIZE(ssp_muxreg),
  118. },
  119. };
  120. struct spear_pingroup spear3xx_ssp_pingroup = {
  121. .name = "ssp0_grp",
  122. .pins = ssp_pins,
  123. .npins = ARRAY_SIZE(ssp_pins),
  124. .modemuxs = ssp_modemux,
  125. .nmodemuxs = ARRAY_SIZE(ssp_modemux),
  126. };
  127. static const char *const ssp_grps[] = { "ssp0_grp" };
  128. struct spear_function spear3xx_ssp_function = {
  129. .name = "ssp0",
  130. .groups = ssp_grps,
  131. .ngroups = ARRAY_SIZE(ssp_grps),
  132. };
  133. /* mii_pins */
  134. static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
  135. 21, 22, 23, 24, 25, 26, 27 };
  136. static struct spear_muxreg mii_muxreg[] = {
  137. {
  138. .reg = -1,
  139. .mask = PMX_MII_MASK,
  140. .val = PMX_MII_MASK,
  141. },
  142. };
  143. static struct spear_modemux mii_modemux[] = {
  144. {
  145. .modes = ~0,
  146. .muxregs = mii_muxreg,
  147. .nmuxregs = ARRAY_SIZE(mii_muxreg),
  148. },
  149. };
  150. struct spear_pingroup spear3xx_mii_pingroup = {
  151. .name = "mii0_grp",
  152. .pins = mii_pins,
  153. .npins = ARRAY_SIZE(mii_pins),
  154. .modemuxs = mii_modemux,
  155. .nmodemuxs = ARRAY_SIZE(mii_modemux),
  156. };
  157. static const char *const mii_grps[] = { "mii0_grp" };
  158. struct spear_function spear3xx_mii_function = {
  159. .name = "mii0",
  160. .groups = mii_grps,
  161. .ngroups = ARRAY_SIZE(mii_grps),
  162. };
  163. /* gpio0_pin0_pins */
  164. static const unsigned gpio0_pin0_pins[] = { 28 };
  165. static struct spear_muxreg gpio0_pin0_muxreg[] = {
  166. {
  167. .reg = -1,
  168. .mask = PMX_GPIO_PIN0_MASK,
  169. .val = PMX_GPIO_PIN0_MASK,
  170. },
  171. };
  172. static struct spear_modemux gpio0_pin0_modemux[] = {
  173. {
  174. .modes = ~0,
  175. .muxregs = gpio0_pin0_muxreg,
  176. .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
  177. },
  178. };
  179. struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
  180. .name = "gpio0_pin0_grp",
  181. .pins = gpio0_pin0_pins,
  182. .npins = ARRAY_SIZE(gpio0_pin0_pins),
  183. .modemuxs = gpio0_pin0_modemux,
  184. .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
  185. };
  186. /* gpio0_pin1_pins */
  187. static const unsigned gpio0_pin1_pins[] = { 29 };
  188. static struct spear_muxreg gpio0_pin1_muxreg[] = {
  189. {
  190. .reg = -1,
  191. .mask = PMX_GPIO_PIN1_MASK,
  192. .val = PMX_GPIO_PIN1_MASK,
  193. },
  194. };
  195. static struct spear_modemux gpio0_pin1_modemux[] = {
  196. {
  197. .modes = ~0,
  198. .muxregs = gpio0_pin1_muxreg,
  199. .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
  200. },
  201. };
  202. struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
  203. .name = "gpio0_pin1_grp",
  204. .pins = gpio0_pin1_pins,
  205. .npins = ARRAY_SIZE(gpio0_pin1_pins),
  206. .modemuxs = gpio0_pin1_modemux,
  207. .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
  208. };
  209. /* gpio0_pin2_pins */
  210. static const unsigned gpio0_pin2_pins[] = { 30 };
  211. static struct spear_muxreg gpio0_pin2_muxreg[] = {
  212. {
  213. .reg = -1,
  214. .mask = PMX_GPIO_PIN2_MASK,
  215. .val = PMX_GPIO_PIN2_MASK,
  216. },
  217. };
  218. static struct spear_modemux gpio0_pin2_modemux[] = {
  219. {
  220. .modes = ~0,
  221. .muxregs = gpio0_pin2_muxreg,
  222. .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
  223. },
  224. };
  225. struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
  226. .name = "gpio0_pin2_grp",
  227. .pins = gpio0_pin2_pins,
  228. .npins = ARRAY_SIZE(gpio0_pin2_pins),
  229. .modemuxs = gpio0_pin2_modemux,
  230. .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
  231. };
  232. /* gpio0_pin3_pins */
  233. static const unsigned gpio0_pin3_pins[] = { 31 };
  234. static struct spear_muxreg gpio0_pin3_muxreg[] = {
  235. {
  236. .reg = -1,
  237. .mask = PMX_GPIO_PIN3_MASK,
  238. .val = PMX_GPIO_PIN3_MASK,
  239. },
  240. };
  241. static struct spear_modemux gpio0_pin3_modemux[] = {
  242. {
  243. .modes = ~0,
  244. .muxregs = gpio0_pin3_muxreg,
  245. .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
  246. },
  247. };
  248. struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
  249. .name = "gpio0_pin3_grp",
  250. .pins = gpio0_pin3_pins,
  251. .npins = ARRAY_SIZE(gpio0_pin3_pins),
  252. .modemuxs = gpio0_pin3_modemux,
  253. .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
  254. };
  255. /* gpio0_pin4_pins */
  256. static const unsigned gpio0_pin4_pins[] = { 32 };
  257. static struct spear_muxreg gpio0_pin4_muxreg[] = {
  258. {
  259. .reg = -1,
  260. .mask = PMX_GPIO_PIN4_MASK,
  261. .val = PMX_GPIO_PIN4_MASK,
  262. },
  263. };
  264. static struct spear_modemux gpio0_pin4_modemux[] = {
  265. {
  266. .modes = ~0,
  267. .muxregs = gpio0_pin4_muxreg,
  268. .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
  269. },
  270. };
  271. struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
  272. .name = "gpio0_pin4_grp",
  273. .pins = gpio0_pin4_pins,
  274. .npins = ARRAY_SIZE(gpio0_pin4_pins),
  275. .modemuxs = gpio0_pin4_modemux,
  276. .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
  277. };
  278. /* gpio0_pin5_pins */
  279. static const unsigned gpio0_pin5_pins[] = { 33 };
  280. static struct spear_muxreg gpio0_pin5_muxreg[] = {
  281. {
  282. .reg = -1,
  283. .mask = PMX_GPIO_PIN5_MASK,
  284. .val = PMX_GPIO_PIN5_MASK,
  285. },
  286. };
  287. static struct spear_modemux gpio0_pin5_modemux[] = {
  288. {
  289. .modes = ~0,
  290. .muxregs = gpio0_pin5_muxreg,
  291. .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
  292. },
  293. };
  294. struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
  295. .name = "gpio0_pin5_grp",
  296. .pins = gpio0_pin5_pins,
  297. .npins = ARRAY_SIZE(gpio0_pin5_pins),
  298. .modemuxs = gpio0_pin5_modemux,
  299. .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
  300. };
  301. static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
  302. "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
  303. };
  304. struct spear_function spear3xx_gpio0_function = {
  305. .name = "gpio0",
  306. .groups = gpio0_grps,
  307. .ngroups = ARRAY_SIZE(gpio0_grps),
  308. };
  309. /* uart0_ext_pins */
  310. static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
  311. static struct spear_muxreg uart0_ext_muxreg[] = {
  312. {
  313. .reg = -1,
  314. .mask = PMX_UART0_MODEM_MASK,
  315. .val = PMX_UART0_MODEM_MASK,
  316. },
  317. };
  318. static struct spear_modemux uart0_ext_modemux[] = {
  319. {
  320. .modes = ~0,
  321. .muxregs = uart0_ext_muxreg,
  322. .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
  323. },
  324. };
  325. struct spear_pingroup spear3xx_uart0_ext_pingroup = {
  326. .name = "uart0_ext_grp",
  327. .pins = uart0_ext_pins,
  328. .npins = ARRAY_SIZE(uart0_ext_pins),
  329. .modemuxs = uart0_ext_modemux,
  330. .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
  331. };
  332. static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
  333. struct spear_function spear3xx_uart0_ext_function = {
  334. .name = "uart0_ext",
  335. .groups = uart0_ext_grps,
  336. .ngroups = ARRAY_SIZE(uart0_ext_grps),
  337. };
  338. /* uart0_pins */
  339. static const unsigned uart0_pins[] = { 2, 3 };
  340. static struct spear_muxreg uart0_muxreg[] = {
  341. {
  342. .reg = -1,
  343. .mask = PMX_UART0_MASK,
  344. .val = PMX_UART0_MASK,
  345. },
  346. };
  347. static struct spear_modemux uart0_modemux[] = {
  348. {
  349. .modes = ~0,
  350. .muxregs = uart0_muxreg,
  351. .nmuxregs = ARRAY_SIZE(uart0_muxreg),
  352. },
  353. };
  354. struct spear_pingroup spear3xx_uart0_pingroup = {
  355. .name = "uart0_grp",
  356. .pins = uart0_pins,
  357. .npins = ARRAY_SIZE(uart0_pins),
  358. .modemuxs = uart0_modemux,
  359. .nmodemuxs = ARRAY_SIZE(uart0_modemux),
  360. };
  361. static const char *const uart0_grps[] = { "uart0_grp" };
  362. struct spear_function spear3xx_uart0_function = {
  363. .name = "uart0",
  364. .groups = uart0_grps,
  365. .ngroups = ARRAY_SIZE(uart0_grps),
  366. };
  367. /* timer_0_1_pins */
  368. static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
  369. static struct spear_muxreg timer_0_1_muxreg[] = {
  370. {
  371. .reg = -1,
  372. .mask = PMX_TIMER_0_1_MASK,
  373. .val = PMX_TIMER_0_1_MASK,
  374. },
  375. };
  376. static struct spear_modemux timer_0_1_modemux[] = {
  377. {
  378. .modes = ~0,
  379. .muxregs = timer_0_1_muxreg,
  380. .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
  381. },
  382. };
  383. struct spear_pingroup spear3xx_timer_0_1_pingroup = {
  384. .name = "timer_0_1_grp",
  385. .pins = timer_0_1_pins,
  386. .npins = ARRAY_SIZE(timer_0_1_pins),
  387. .modemuxs = timer_0_1_modemux,
  388. .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
  389. };
  390. static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
  391. struct spear_function spear3xx_timer_0_1_function = {
  392. .name = "timer_0_1",
  393. .groups = timer_0_1_grps,
  394. .ngroups = ARRAY_SIZE(timer_0_1_grps),
  395. };
  396. /* timer_2_3_pins */
  397. static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
  398. static struct spear_muxreg timer_2_3_muxreg[] = {
  399. {
  400. .reg = -1,
  401. .mask = PMX_TIMER_2_3_MASK,
  402. .val = PMX_TIMER_2_3_MASK,
  403. },
  404. };
  405. static struct spear_modemux timer_2_3_modemux[] = {
  406. {
  407. .modes = ~0,
  408. .muxregs = timer_2_3_muxreg,
  409. .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
  410. },
  411. };
  412. struct spear_pingroup spear3xx_timer_2_3_pingroup = {
  413. .name = "timer_2_3_grp",
  414. .pins = timer_2_3_pins,
  415. .npins = ARRAY_SIZE(timer_2_3_pins),
  416. .modemuxs = timer_2_3_modemux,
  417. .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
  418. };
  419. static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
  420. struct spear_function spear3xx_timer_2_3_function = {
  421. .name = "timer_2_3",
  422. .groups = timer_2_3_grps,
  423. .ngroups = ARRAY_SIZE(timer_2_3_grps),
  424. };
  425. /* Define muxreg arrays */
  426. DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
  427. DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
  428. DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
  429. DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
  430. DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
  431. DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
  432. DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
  433. DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
  434. DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
  435. DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
  436. DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
  437. DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
  438. DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
  439. DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
  440. DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
  441. static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
  442. GPIO_PINGROUP(firda_pins),
  443. GPIO_PINGROUP(i2c_pins),
  444. GPIO_PINGROUP(ssp_cs_pins),
  445. GPIO_PINGROUP(ssp_pins),
  446. GPIO_PINGROUP(mii_pins),
  447. GPIO_PINGROUP(gpio0_pin0_pins),
  448. GPIO_PINGROUP(gpio0_pin1_pins),
  449. GPIO_PINGROUP(gpio0_pin2_pins),
  450. GPIO_PINGROUP(gpio0_pin3_pins),
  451. GPIO_PINGROUP(gpio0_pin4_pins),
  452. GPIO_PINGROUP(gpio0_pin5_pins),
  453. GPIO_PINGROUP(uart0_ext_pins),
  454. GPIO_PINGROUP(uart0_pins),
  455. GPIO_PINGROUP(timer_0_1_pins),
  456. GPIO_PINGROUP(timer_2_3_pins),
  457. };
  458. struct spear_pinctrl_machdata spear3xx_machdata = {
  459. .pins = spear3xx_pins,
  460. .npins = ARRAY_SIZE(spear3xx_pins),
  461. .gpio_pingroups = spear3xx_gpio_pingroup,
  462. .ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
  463. };