pinctrl-spear310.c 9.1 KB

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  1. /*
  2. * Driver for the ST Microelectronics SPEAr310 pinmux
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Viresh Kumar <vireshk@kernel.org>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include "pinctrl-spear3xx.h"
  16. #define DRIVER_NAME "spear310-pinmux"
  17. /* addresses */
  18. #define PMX_CONFIG_REG 0x08
  19. /* emi_cs_0_to_5_pins */
  20. static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 };
  21. static struct spear_muxreg emi_cs_0_to_5_muxreg[] = {
  22. {
  23. .reg = PMX_CONFIG_REG,
  24. .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
  25. .val = 0,
  26. },
  27. };
  28. static struct spear_modemux emi_cs_0_to_5_modemux[] = {
  29. {
  30. .muxregs = emi_cs_0_to_5_muxreg,
  31. .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg),
  32. },
  33. };
  34. static struct spear_pingroup emi_cs_0_to_5_pingroup = {
  35. .name = "emi_cs_0_to_5_grp",
  36. .pins = emi_cs_0_to_5_pins,
  37. .npins = ARRAY_SIZE(emi_cs_0_to_5_pins),
  38. .modemuxs = emi_cs_0_to_5_modemux,
  39. .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux),
  40. };
  41. static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" };
  42. static struct spear_function emi_cs_0_to_5_function = {
  43. .name = "emi",
  44. .groups = emi_cs_0_to_5_grps,
  45. .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps),
  46. };
  47. /* uart1_pins */
  48. static const unsigned uart1_pins[] = { 0, 1 };
  49. static struct spear_muxreg uart1_muxreg[] = {
  50. {
  51. .reg = PMX_CONFIG_REG,
  52. .mask = PMX_FIRDA_MASK,
  53. .val = 0,
  54. },
  55. };
  56. static struct spear_modemux uart1_modemux[] = {
  57. {
  58. .muxregs = uart1_muxreg,
  59. .nmuxregs = ARRAY_SIZE(uart1_muxreg),
  60. },
  61. };
  62. static struct spear_pingroup uart1_pingroup = {
  63. .name = "uart1_grp",
  64. .pins = uart1_pins,
  65. .npins = ARRAY_SIZE(uart1_pins),
  66. .modemuxs = uart1_modemux,
  67. .nmodemuxs = ARRAY_SIZE(uart1_modemux),
  68. };
  69. static const char *const uart1_grps[] = { "uart1_grp" };
  70. static struct spear_function uart1_function = {
  71. .name = "uart1",
  72. .groups = uart1_grps,
  73. .ngroups = ARRAY_SIZE(uart1_grps),
  74. };
  75. /* uart2_pins */
  76. static const unsigned uart2_pins[] = { 43, 44 };
  77. static struct spear_muxreg uart2_muxreg[] = {
  78. {
  79. .reg = PMX_CONFIG_REG,
  80. .mask = PMX_TIMER_0_1_MASK,
  81. .val = 0,
  82. },
  83. };
  84. static struct spear_modemux uart2_modemux[] = {
  85. {
  86. .muxregs = uart2_muxreg,
  87. .nmuxregs = ARRAY_SIZE(uart2_muxreg),
  88. },
  89. };
  90. static struct spear_pingroup uart2_pingroup = {
  91. .name = "uart2_grp",
  92. .pins = uart2_pins,
  93. .npins = ARRAY_SIZE(uart2_pins),
  94. .modemuxs = uart2_modemux,
  95. .nmodemuxs = ARRAY_SIZE(uart2_modemux),
  96. };
  97. static const char *const uart2_grps[] = { "uart2_grp" };
  98. static struct spear_function uart2_function = {
  99. .name = "uart2",
  100. .groups = uart2_grps,
  101. .ngroups = ARRAY_SIZE(uart2_grps),
  102. };
  103. /* uart3_pins */
  104. static const unsigned uart3_pins[] = { 37, 38 };
  105. static struct spear_muxreg uart3_muxreg[] = {
  106. {
  107. .reg = PMX_CONFIG_REG,
  108. .mask = PMX_UART0_MODEM_MASK,
  109. .val = 0,
  110. },
  111. };
  112. static struct spear_modemux uart3_modemux[] = {
  113. {
  114. .muxregs = uart3_muxreg,
  115. .nmuxregs = ARRAY_SIZE(uart3_muxreg),
  116. },
  117. };
  118. static struct spear_pingroup uart3_pingroup = {
  119. .name = "uart3_grp",
  120. .pins = uart3_pins,
  121. .npins = ARRAY_SIZE(uart3_pins),
  122. .modemuxs = uart3_modemux,
  123. .nmodemuxs = ARRAY_SIZE(uart3_modemux),
  124. };
  125. static const char *const uart3_grps[] = { "uart3_grp" };
  126. static struct spear_function uart3_function = {
  127. .name = "uart3",
  128. .groups = uart3_grps,
  129. .ngroups = ARRAY_SIZE(uart3_grps),
  130. };
  131. /* uart4_pins */
  132. static const unsigned uart4_pins[] = { 39, 40 };
  133. static struct spear_muxreg uart4_muxreg[] = {
  134. {
  135. .reg = PMX_CONFIG_REG,
  136. .mask = PMX_UART0_MODEM_MASK,
  137. .val = 0,
  138. },
  139. };
  140. static struct spear_modemux uart4_modemux[] = {
  141. {
  142. .muxregs = uart4_muxreg,
  143. .nmuxregs = ARRAY_SIZE(uart4_muxreg),
  144. },
  145. };
  146. static struct spear_pingroup uart4_pingroup = {
  147. .name = "uart4_grp",
  148. .pins = uart4_pins,
  149. .npins = ARRAY_SIZE(uart4_pins),
  150. .modemuxs = uart4_modemux,
  151. .nmodemuxs = ARRAY_SIZE(uart4_modemux),
  152. };
  153. static const char *const uart4_grps[] = { "uart4_grp" };
  154. static struct spear_function uart4_function = {
  155. .name = "uart4",
  156. .groups = uart4_grps,
  157. .ngroups = ARRAY_SIZE(uart4_grps),
  158. };
  159. /* uart5_pins */
  160. static const unsigned uart5_pins[] = { 41, 42 };
  161. static struct spear_muxreg uart5_muxreg[] = {
  162. {
  163. .reg = PMX_CONFIG_REG,
  164. .mask = PMX_UART0_MODEM_MASK,
  165. .val = 0,
  166. },
  167. };
  168. static struct spear_modemux uart5_modemux[] = {
  169. {
  170. .muxregs = uart5_muxreg,
  171. .nmuxregs = ARRAY_SIZE(uart5_muxreg),
  172. },
  173. };
  174. static struct spear_pingroup uart5_pingroup = {
  175. .name = "uart5_grp",
  176. .pins = uart5_pins,
  177. .npins = ARRAY_SIZE(uart5_pins),
  178. .modemuxs = uart5_modemux,
  179. .nmodemuxs = ARRAY_SIZE(uart5_modemux),
  180. };
  181. static const char *const uart5_grps[] = { "uart5_grp" };
  182. static struct spear_function uart5_function = {
  183. .name = "uart5",
  184. .groups = uart5_grps,
  185. .ngroups = ARRAY_SIZE(uart5_grps),
  186. };
  187. /* fsmc_pins */
  188. static const unsigned fsmc_pins[] = { 34, 35, 36 };
  189. static struct spear_muxreg fsmc_muxreg[] = {
  190. {
  191. .reg = PMX_CONFIG_REG,
  192. .mask = PMX_SSP_CS_MASK,
  193. .val = 0,
  194. },
  195. };
  196. static struct spear_modemux fsmc_modemux[] = {
  197. {
  198. .muxregs = fsmc_muxreg,
  199. .nmuxregs = ARRAY_SIZE(fsmc_muxreg),
  200. },
  201. };
  202. static struct spear_pingroup fsmc_pingroup = {
  203. .name = "fsmc_grp",
  204. .pins = fsmc_pins,
  205. .npins = ARRAY_SIZE(fsmc_pins),
  206. .modemuxs = fsmc_modemux,
  207. .nmodemuxs = ARRAY_SIZE(fsmc_modemux),
  208. };
  209. static const char *const fsmc_grps[] = { "fsmc_grp" };
  210. static struct spear_function fsmc_function = {
  211. .name = "fsmc",
  212. .groups = fsmc_grps,
  213. .ngroups = ARRAY_SIZE(fsmc_grps),
  214. };
  215. /* rs485_0_pins */
  216. static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 };
  217. static struct spear_muxreg rs485_0_muxreg[] = {
  218. {
  219. .reg = PMX_CONFIG_REG,
  220. .mask = PMX_MII_MASK,
  221. .val = 0,
  222. },
  223. };
  224. static struct spear_modemux rs485_0_modemux[] = {
  225. {
  226. .muxregs = rs485_0_muxreg,
  227. .nmuxregs = ARRAY_SIZE(rs485_0_muxreg),
  228. },
  229. };
  230. static struct spear_pingroup rs485_0_pingroup = {
  231. .name = "rs485_0_grp",
  232. .pins = rs485_0_pins,
  233. .npins = ARRAY_SIZE(rs485_0_pins),
  234. .modemuxs = rs485_0_modemux,
  235. .nmodemuxs = ARRAY_SIZE(rs485_0_modemux),
  236. };
  237. static const char *const rs485_0_grps[] = { "rs485_0" };
  238. static struct spear_function rs485_0_function = {
  239. .name = "rs485_0",
  240. .groups = rs485_0_grps,
  241. .ngroups = ARRAY_SIZE(rs485_0_grps),
  242. };
  243. /* rs485_1_pins */
  244. static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 };
  245. static struct spear_muxreg rs485_1_muxreg[] = {
  246. {
  247. .reg = PMX_CONFIG_REG,
  248. .mask = PMX_MII_MASK,
  249. .val = 0,
  250. },
  251. };
  252. static struct spear_modemux rs485_1_modemux[] = {
  253. {
  254. .muxregs = rs485_1_muxreg,
  255. .nmuxregs = ARRAY_SIZE(rs485_1_muxreg),
  256. },
  257. };
  258. static struct spear_pingroup rs485_1_pingroup = {
  259. .name = "rs485_1_grp",
  260. .pins = rs485_1_pins,
  261. .npins = ARRAY_SIZE(rs485_1_pins),
  262. .modemuxs = rs485_1_modemux,
  263. .nmodemuxs = ARRAY_SIZE(rs485_1_modemux),
  264. };
  265. static const char *const rs485_1_grps[] = { "rs485_1" };
  266. static struct spear_function rs485_1_function = {
  267. .name = "rs485_1",
  268. .groups = rs485_1_grps,
  269. .ngroups = ARRAY_SIZE(rs485_1_grps),
  270. };
  271. /* tdm_pins */
  272. static const unsigned tdm_pins[] = { 10, 11, 12, 13 };
  273. static struct spear_muxreg tdm_muxreg[] = {
  274. {
  275. .reg = PMX_CONFIG_REG,
  276. .mask = PMX_MII_MASK,
  277. .val = 0,
  278. },
  279. };
  280. static struct spear_modemux tdm_modemux[] = {
  281. {
  282. .muxregs = tdm_muxreg,
  283. .nmuxregs = ARRAY_SIZE(tdm_muxreg),
  284. },
  285. };
  286. static struct spear_pingroup tdm_pingroup = {
  287. .name = "tdm_grp",
  288. .pins = tdm_pins,
  289. .npins = ARRAY_SIZE(tdm_pins),
  290. .modemuxs = tdm_modemux,
  291. .nmodemuxs = ARRAY_SIZE(tdm_modemux),
  292. };
  293. static const char *const tdm_grps[] = { "tdm_grp" };
  294. static struct spear_function tdm_function = {
  295. .name = "tdm",
  296. .groups = tdm_grps,
  297. .ngroups = ARRAY_SIZE(tdm_grps),
  298. };
  299. /* pingroups */
  300. static struct spear_pingroup *spear310_pingroups[] = {
  301. SPEAR3XX_COMMON_PINGROUPS,
  302. &emi_cs_0_to_5_pingroup,
  303. &uart1_pingroup,
  304. &uart2_pingroup,
  305. &uart3_pingroup,
  306. &uart4_pingroup,
  307. &uart5_pingroup,
  308. &fsmc_pingroup,
  309. &rs485_0_pingroup,
  310. &rs485_1_pingroup,
  311. &tdm_pingroup,
  312. };
  313. /* functions */
  314. static struct spear_function *spear310_functions[] = {
  315. SPEAR3XX_COMMON_FUNCTIONS,
  316. &emi_cs_0_to_5_function,
  317. &uart1_function,
  318. &uart2_function,
  319. &uart3_function,
  320. &uart4_function,
  321. &uart5_function,
  322. &fsmc_function,
  323. &rs485_0_function,
  324. &rs485_1_function,
  325. &tdm_function,
  326. };
  327. static const struct of_device_id spear310_pinctrl_of_match[] = {
  328. {
  329. .compatible = "st,spear310-pinmux",
  330. },
  331. {},
  332. };
  333. static int spear310_pinctrl_probe(struct platform_device *pdev)
  334. {
  335. spear3xx_machdata.groups = spear310_pingroups;
  336. spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups);
  337. spear3xx_machdata.functions = spear310_functions;
  338. spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
  339. pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
  340. pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
  341. spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
  342. spear3xx_machdata.modes_supported = false;
  343. return spear_pinctrl_probe(pdev, &spear3xx_machdata);
  344. }
  345. static struct platform_driver spear310_pinctrl_driver = {
  346. .driver = {
  347. .name = DRIVER_NAME,
  348. .of_match_table = spear310_pinctrl_of_match,
  349. },
  350. .probe = spear310_pinctrl_probe,
  351. };
  352. static int __init spear310_pinctrl_init(void)
  353. {
  354. return platform_driver_register(&spear310_pinctrl_driver);
  355. }
  356. arch_initcall(spear310_pinctrl_init);