pinctrl-spear1310.c 76 KB

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  1. /*
  2. * Driver for the ST Microelectronics SPEAr1310 pinmux
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Viresh Kumar <vireshk@kernel.org>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/of_device.h>
  14. #include <linux/platform_device.h>
  15. #include "pinctrl-spear.h"
  16. #define DRIVER_NAME "spear1310-pinmux"
  17. /* pins */
  18. static const struct pinctrl_pin_desc spear1310_pins[] = {
  19. SPEAR_PIN_0_TO_101,
  20. SPEAR_PIN_102_TO_245,
  21. };
  22. /* registers */
  23. #define PERIP_CFG 0x3B0
  24. #define MCIF_SEL_SHIFT 5
  25. #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
  26. #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
  27. #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
  28. #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
  29. #define PCIE_SATA_CFG 0x3A4
  30. #define PCIE_SATA2_SEL_PCIE (0 << 31)
  31. #define PCIE_SATA1_SEL_PCIE (0 << 30)
  32. #define PCIE_SATA0_SEL_PCIE (0 << 29)
  33. #define PCIE_SATA2_SEL_SATA (1 << 31)
  34. #define PCIE_SATA1_SEL_SATA (1 << 30)
  35. #define PCIE_SATA0_SEL_SATA (1 << 29)
  36. #define SATA2_CFG_TX_CLK_EN (1 << 27)
  37. #define SATA2_CFG_RX_CLK_EN (1 << 26)
  38. #define SATA2_CFG_POWERUP_RESET (1 << 25)
  39. #define SATA2_CFG_PM_CLK_EN (1 << 24)
  40. #define SATA1_CFG_TX_CLK_EN (1 << 23)
  41. #define SATA1_CFG_RX_CLK_EN (1 << 22)
  42. #define SATA1_CFG_POWERUP_RESET (1 << 21)
  43. #define SATA1_CFG_PM_CLK_EN (1 << 20)
  44. #define SATA0_CFG_TX_CLK_EN (1 << 19)
  45. #define SATA0_CFG_RX_CLK_EN (1 << 18)
  46. #define SATA0_CFG_POWERUP_RESET (1 << 17)
  47. #define SATA0_CFG_PM_CLK_EN (1 << 16)
  48. #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
  49. #define PCIE2_CFG_POWERUP_RESET (1 << 10)
  50. #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
  51. #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
  52. #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
  53. #define PCIE1_CFG_POWERUP_RESET (1 << 6)
  54. #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
  55. #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
  56. #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
  57. #define PCIE0_CFG_POWERUP_RESET (1 << 2)
  58. #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
  59. #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
  60. #define PAD_FUNCTION_EN_0 0x650
  61. #define PMX_UART0_MASK (1 << 1)
  62. #define PMX_I2C0_MASK (1 << 2)
  63. #define PMX_I2S0_MASK (1 << 3)
  64. #define PMX_SSP0_MASK (1 << 4)
  65. #define PMX_CLCD1_MASK (1 << 5)
  66. #define PMX_EGPIO00_MASK (1 << 6)
  67. #define PMX_EGPIO01_MASK (1 << 7)
  68. #define PMX_EGPIO02_MASK (1 << 8)
  69. #define PMX_EGPIO03_MASK (1 << 9)
  70. #define PMX_EGPIO04_MASK (1 << 10)
  71. #define PMX_EGPIO05_MASK (1 << 11)
  72. #define PMX_EGPIO06_MASK (1 << 12)
  73. #define PMX_EGPIO07_MASK (1 << 13)
  74. #define PMX_EGPIO08_MASK (1 << 14)
  75. #define PMX_EGPIO09_MASK (1 << 15)
  76. #define PMX_SMI_MASK (1 << 16)
  77. #define PMX_NAND8_MASK (1 << 17)
  78. #define PMX_GMIICLK_MASK (1 << 18)
  79. #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
  80. #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
  81. #define PMX_GMIID47_MASK (1 << 21)
  82. #define PMX_MDC_MDIO_MASK (1 << 22)
  83. #define PMX_MCI_DATA8_15_MASK (1 << 23)
  84. #define PMX_NFAD23_MASK (1 << 24)
  85. #define PMX_NFAD24_MASK (1 << 25)
  86. #define PMX_NFAD25_MASK (1 << 26)
  87. #define PMX_NFCE3_MASK (1 << 27)
  88. #define PMX_NFWPRT3_MASK (1 << 28)
  89. #define PMX_NFRSTPWDWN0_MASK (1 << 29)
  90. #define PMX_NFRSTPWDWN1_MASK (1 << 30)
  91. #define PMX_NFRSTPWDWN2_MASK (1 << 31)
  92. #define PAD_FUNCTION_EN_1 0x654
  93. #define PMX_NFRSTPWDWN3_MASK (1 << 0)
  94. #define PMX_SMINCS2_MASK (1 << 1)
  95. #define PMX_SMINCS3_MASK (1 << 2)
  96. #define PMX_CLCD2_MASK (1 << 3)
  97. #define PMX_KBD_ROWCOL68_MASK (1 << 4)
  98. #define PMX_EGPIO10_MASK (1 << 5)
  99. #define PMX_EGPIO11_MASK (1 << 6)
  100. #define PMX_EGPIO12_MASK (1 << 7)
  101. #define PMX_EGPIO13_MASK (1 << 8)
  102. #define PMX_EGPIO14_MASK (1 << 9)
  103. #define PMX_EGPIO15_MASK (1 << 10)
  104. #define PMX_UART0_MODEM_MASK (1 << 11)
  105. #define PMX_GPT0_TMR0_MASK (1 << 12)
  106. #define PMX_GPT0_TMR1_MASK (1 << 13)
  107. #define PMX_GPT1_TMR0_MASK (1 << 14)
  108. #define PMX_GPT1_TMR1_MASK (1 << 15)
  109. #define PMX_I2S1_MASK (1 << 16)
  110. #define PMX_KBD_ROWCOL25_MASK (1 << 17)
  111. #define PMX_NFIO8_15_MASK (1 << 18)
  112. #define PMX_KBD_COL1_MASK (1 << 19)
  113. #define PMX_NFCE1_MASK (1 << 20)
  114. #define PMX_KBD_COL0_MASK (1 << 21)
  115. #define PMX_NFCE2_MASK (1 << 22)
  116. #define PMX_KBD_ROW1_MASK (1 << 23)
  117. #define PMX_NFWPRT1_MASK (1 << 24)
  118. #define PMX_KBD_ROW0_MASK (1 << 25)
  119. #define PMX_NFWPRT2_MASK (1 << 26)
  120. #define PMX_MCIDATA0_MASK (1 << 27)
  121. #define PMX_MCIDATA1_MASK (1 << 28)
  122. #define PMX_MCIDATA2_MASK (1 << 29)
  123. #define PMX_MCIDATA3_MASK (1 << 30)
  124. #define PMX_MCIDATA4_MASK (1 << 31)
  125. #define PAD_FUNCTION_EN_2 0x658
  126. #define PMX_MCIDATA5_MASK (1 << 0)
  127. #define PMX_MCIDATA6_MASK (1 << 1)
  128. #define PMX_MCIDATA7_MASK (1 << 2)
  129. #define PMX_MCIDATA1SD_MASK (1 << 3)
  130. #define PMX_MCIDATA2SD_MASK (1 << 4)
  131. #define PMX_MCIDATA3SD_MASK (1 << 5)
  132. #define PMX_MCIADDR0ALE_MASK (1 << 6)
  133. #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
  134. #define PMX_MCIADDR2_MASK (1 << 8)
  135. #define PMX_MCICECF_MASK (1 << 9)
  136. #define PMX_MCICEXD_MASK (1 << 10)
  137. #define PMX_MCICESDMMC_MASK (1 << 11)
  138. #define PMX_MCICDCF1_MASK (1 << 12)
  139. #define PMX_MCICDCF2_MASK (1 << 13)
  140. #define PMX_MCICDXD_MASK (1 << 14)
  141. #define PMX_MCICDSDMMC_MASK (1 << 15)
  142. #define PMX_MCIDATADIR_MASK (1 << 16)
  143. #define PMX_MCIDMARQWP_MASK (1 << 17)
  144. #define PMX_MCIIORDRE_MASK (1 << 18)
  145. #define PMX_MCIIOWRWE_MASK (1 << 19)
  146. #define PMX_MCIRESETCF_MASK (1 << 20)
  147. #define PMX_MCICS0CE_MASK (1 << 21)
  148. #define PMX_MCICFINTR_MASK (1 << 22)
  149. #define PMX_MCIIORDY_MASK (1 << 23)
  150. #define PMX_MCICS1_MASK (1 << 24)
  151. #define PMX_MCIDMAACK_MASK (1 << 25)
  152. #define PMX_MCISDCMD_MASK (1 << 26)
  153. #define PMX_MCILEDS_MASK (1 << 27)
  154. #define PMX_TOUCH_XY_MASK (1 << 28)
  155. #define PMX_SSP0_CS0_MASK (1 << 29)
  156. #define PMX_SSP0_CS1_2_MASK (1 << 30)
  157. #define PAD_DIRECTION_SEL_0 0x65C
  158. #define PAD_DIRECTION_SEL_1 0x660
  159. #define PAD_DIRECTION_SEL_2 0x664
  160. /* combined macros */
  161. #define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
  162. PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
  163. PMX_RXCLK_RDV_TXEN_D03_MASK | \
  164. PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
  165. #define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
  166. PMX_EGPIO02_MASK | \
  167. PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
  168. PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
  169. PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
  170. PMX_EGPIO09_MASK)
  171. #define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
  172. PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
  173. PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
  174. #define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
  175. PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
  176. PMX_KBD_COL1_MASK)
  177. #define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
  178. PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
  179. PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
  180. PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
  181. PMX_NFCE3_MASK)
  182. #define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
  183. #define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
  184. #define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
  185. PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
  186. PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
  187. PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
  188. #define PMX_MCIFALL_1_MASK 0xF8000000
  189. #define PMX_MCIFALL_2_MASK 0x0FFFFFFF
  190. #define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
  191. PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
  192. PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
  193. PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
  194. PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
  195. PMX_NFCE2_MASK)
  196. #define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
  197. PMX_SSP0_CS1_2_MASK)
  198. #define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
  199. #define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
  200. PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
  201. PMX_GMIID47_MASK)
  202. #define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
  203. PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
  204. PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
  205. #define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
  206. PMX_SSP0_CS1_2_MASK)
  207. #define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
  208. PCIE##x##_CFG_AUX_CLK_EN | \
  209. PCIE##x##_CFG_CORE_CLK_EN | \
  210. PCIE##x##_CFG_POWERUP_RESET | \
  211. PCIE##x##_CFG_DEVICE_PRESENT)
  212. #define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
  213. SATA##x##_CFG_PM_CLK_EN | \
  214. SATA##x##_CFG_POWERUP_RESET | \
  215. SATA##x##_CFG_RX_CLK_EN | \
  216. SATA##x##_CFG_TX_CLK_EN)
  217. /* Pad multiplexing for i2c0 device */
  218. static const unsigned i2c0_pins[] = { 102, 103 };
  219. static struct spear_muxreg i2c0_muxreg[] = {
  220. {
  221. .reg = PAD_FUNCTION_EN_0,
  222. .mask = PMX_I2C0_MASK,
  223. .val = PMX_I2C0_MASK,
  224. }, {
  225. .reg = PAD_DIRECTION_SEL_0,
  226. .mask = PMX_I2C0_MASK,
  227. .val = PMX_I2C0_MASK,
  228. },
  229. };
  230. static struct spear_modemux i2c0_modemux[] = {
  231. {
  232. .muxregs = i2c0_muxreg,
  233. .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
  234. },
  235. };
  236. static struct spear_pingroup i2c0_pingroup = {
  237. .name = "i2c0_grp",
  238. .pins = i2c0_pins,
  239. .npins = ARRAY_SIZE(i2c0_pins),
  240. .modemuxs = i2c0_modemux,
  241. .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
  242. };
  243. static const char *const i2c0_grps[] = { "i2c0_grp" };
  244. static struct spear_function i2c0_function = {
  245. .name = "i2c0",
  246. .groups = i2c0_grps,
  247. .ngroups = ARRAY_SIZE(i2c0_grps),
  248. };
  249. /* Pad multiplexing for ssp0 device */
  250. static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
  251. static struct spear_muxreg ssp0_muxreg[] = {
  252. {
  253. .reg = PAD_FUNCTION_EN_0,
  254. .mask = PMX_SSP0_MASK,
  255. .val = PMX_SSP0_MASK,
  256. }, {
  257. .reg = PAD_DIRECTION_SEL_0,
  258. .mask = PMX_SSP0_MASK,
  259. .val = PMX_SSP0_MASK,
  260. },
  261. };
  262. static struct spear_modemux ssp0_modemux[] = {
  263. {
  264. .muxregs = ssp0_muxreg,
  265. .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
  266. },
  267. };
  268. static struct spear_pingroup ssp0_pingroup = {
  269. .name = "ssp0_grp",
  270. .pins = ssp0_pins,
  271. .npins = ARRAY_SIZE(ssp0_pins),
  272. .modemuxs = ssp0_modemux,
  273. .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
  274. };
  275. /* Pad multiplexing for ssp0_cs0 device */
  276. static const unsigned ssp0_cs0_pins[] = { 96 };
  277. static struct spear_muxreg ssp0_cs0_muxreg[] = {
  278. {
  279. .reg = PAD_FUNCTION_EN_2,
  280. .mask = PMX_SSP0_CS0_MASK,
  281. .val = PMX_SSP0_CS0_MASK,
  282. }, {
  283. .reg = PAD_DIRECTION_SEL_2,
  284. .mask = PMX_SSP0_CS0_MASK,
  285. .val = PMX_SSP0_CS0_MASK,
  286. },
  287. };
  288. static struct spear_modemux ssp0_cs0_modemux[] = {
  289. {
  290. .muxregs = ssp0_cs0_muxreg,
  291. .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
  292. },
  293. };
  294. static struct spear_pingroup ssp0_cs0_pingroup = {
  295. .name = "ssp0_cs0_grp",
  296. .pins = ssp0_cs0_pins,
  297. .npins = ARRAY_SIZE(ssp0_cs0_pins),
  298. .modemuxs = ssp0_cs0_modemux,
  299. .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
  300. };
  301. /* ssp0_cs1_2 device */
  302. static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
  303. static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
  304. {
  305. .reg = PAD_FUNCTION_EN_2,
  306. .mask = PMX_SSP0_CS1_2_MASK,
  307. .val = PMX_SSP0_CS1_2_MASK,
  308. }, {
  309. .reg = PAD_DIRECTION_SEL_2,
  310. .mask = PMX_SSP0_CS1_2_MASK,
  311. .val = PMX_SSP0_CS1_2_MASK,
  312. },
  313. };
  314. static struct spear_modemux ssp0_cs1_2_modemux[] = {
  315. {
  316. .muxregs = ssp0_cs1_2_muxreg,
  317. .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
  318. },
  319. };
  320. static struct spear_pingroup ssp0_cs1_2_pingroup = {
  321. .name = "ssp0_cs1_2_grp",
  322. .pins = ssp0_cs1_2_pins,
  323. .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
  324. .modemuxs = ssp0_cs1_2_modemux,
  325. .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
  326. };
  327. static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
  328. "ssp0_cs1_2_grp" };
  329. static struct spear_function ssp0_function = {
  330. .name = "ssp0",
  331. .groups = ssp0_grps,
  332. .ngroups = ARRAY_SIZE(ssp0_grps),
  333. };
  334. /* Pad multiplexing for i2s0 device */
  335. static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
  336. static struct spear_muxreg i2s0_muxreg[] = {
  337. {
  338. .reg = PAD_FUNCTION_EN_0,
  339. .mask = PMX_I2S0_MASK,
  340. .val = PMX_I2S0_MASK,
  341. }, {
  342. .reg = PAD_DIRECTION_SEL_0,
  343. .mask = PMX_I2S0_MASK,
  344. .val = PMX_I2S0_MASK,
  345. },
  346. };
  347. static struct spear_modemux i2s0_modemux[] = {
  348. {
  349. .muxregs = i2s0_muxreg,
  350. .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
  351. },
  352. };
  353. static struct spear_pingroup i2s0_pingroup = {
  354. .name = "i2s0_grp",
  355. .pins = i2s0_pins,
  356. .npins = ARRAY_SIZE(i2s0_pins),
  357. .modemuxs = i2s0_modemux,
  358. .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
  359. };
  360. static const char *const i2s0_grps[] = { "i2s0_grp" };
  361. static struct spear_function i2s0_function = {
  362. .name = "i2s0",
  363. .groups = i2s0_grps,
  364. .ngroups = ARRAY_SIZE(i2s0_grps),
  365. };
  366. /* Pad multiplexing for i2s1 device */
  367. static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
  368. static struct spear_muxreg i2s1_muxreg[] = {
  369. {
  370. .reg = PAD_FUNCTION_EN_1,
  371. .mask = PMX_I2S1_MASK,
  372. .val = PMX_I2S1_MASK,
  373. }, {
  374. .reg = PAD_DIRECTION_SEL_1,
  375. .mask = PMX_I2S1_MASK,
  376. .val = PMX_I2S1_MASK,
  377. },
  378. };
  379. static struct spear_modemux i2s1_modemux[] = {
  380. {
  381. .muxregs = i2s1_muxreg,
  382. .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
  383. },
  384. };
  385. static struct spear_pingroup i2s1_pingroup = {
  386. .name = "i2s1_grp",
  387. .pins = i2s1_pins,
  388. .npins = ARRAY_SIZE(i2s1_pins),
  389. .modemuxs = i2s1_modemux,
  390. .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
  391. };
  392. static const char *const i2s1_grps[] = { "i2s1_grp" };
  393. static struct spear_function i2s1_function = {
  394. .name = "i2s1",
  395. .groups = i2s1_grps,
  396. .ngroups = ARRAY_SIZE(i2s1_grps),
  397. };
  398. /* Pad multiplexing for clcd device */
  399. static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
  400. 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
  401. 135, 136, 137, 138, 139, 140, 141, 142 };
  402. static struct spear_muxreg clcd_muxreg[] = {
  403. {
  404. .reg = PAD_FUNCTION_EN_0,
  405. .mask = PMX_CLCD1_MASK,
  406. .val = PMX_CLCD1_MASK,
  407. }, {
  408. .reg = PAD_DIRECTION_SEL_0,
  409. .mask = PMX_CLCD1_MASK,
  410. .val = PMX_CLCD1_MASK,
  411. },
  412. };
  413. static struct spear_modemux clcd_modemux[] = {
  414. {
  415. .muxregs = clcd_muxreg,
  416. .nmuxregs = ARRAY_SIZE(clcd_muxreg),
  417. },
  418. };
  419. static struct spear_pingroup clcd_pingroup = {
  420. .name = "clcd_grp",
  421. .pins = clcd_pins,
  422. .npins = ARRAY_SIZE(clcd_pins),
  423. .modemuxs = clcd_modemux,
  424. .nmodemuxs = ARRAY_SIZE(clcd_modemux),
  425. };
  426. static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
  427. 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
  428. static struct spear_muxreg clcd_high_res_muxreg[] = {
  429. {
  430. .reg = PAD_FUNCTION_EN_1,
  431. .mask = PMX_CLCD2_MASK,
  432. .val = PMX_CLCD2_MASK,
  433. }, {
  434. .reg = PAD_DIRECTION_SEL_1,
  435. .mask = PMX_CLCD2_MASK,
  436. .val = PMX_CLCD2_MASK,
  437. },
  438. };
  439. static struct spear_modemux clcd_high_res_modemux[] = {
  440. {
  441. .muxregs = clcd_high_res_muxreg,
  442. .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
  443. },
  444. };
  445. static struct spear_pingroup clcd_high_res_pingroup = {
  446. .name = "clcd_high_res_grp",
  447. .pins = clcd_high_res_pins,
  448. .npins = ARRAY_SIZE(clcd_high_res_pins),
  449. .modemuxs = clcd_high_res_modemux,
  450. .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
  451. };
  452. static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
  453. static struct spear_function clcd_function = {
  454. .name = "clcd",
  455. .groups = clcd_grps,
  456. .ngroups = ARRAY_SIZE(clcd_grps),
  457. };
  458. static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
  459. 146, 147, 148, 149, 150, 151, 152 };
  460. static struct spear_muxreg arm_gpio_muxreg[] = {
  461. {
  462. .reg = PAD_FUNCTION_EN_0,
  463. .mask = PMX_EGPIO_0_GRP_MASK,
  464. .val = PMX_EGPIO_0_GRP_MASK,
  465. }, {
  466. .reg = PAD_FUNCTION_EN_1,
  467. .mask = PMX_EGPIO_1_GRP_MASK,
  468. .val = PMX_EGPIO_1_GRP_MASK,
  469. }, {
  470. .reg = PAD_DIRECTION_SEL_0,
  471. .mask = PMX_EGPIO_0_GRP_MASK,
  472. .val = PMX_EGPIO_0_GRP_MASK,
  473. }, {
  474. .reg = PAD_DIRECTION_SEL_1,
  475. .mask = PMX_EGPIO_1_GRP_MASK,
  476. .val = PMX_EGPIO_1_GRP_MASK,
  477. },
  478. };
  479. static struct spear_modemux arm_gpio_modemux[] = {
  480. {
  481. .muxregs = arm_gpio_muxreg,
  482. .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
  483. },
  484. };
  485. static struct spear_pingroup arm_gpio_pingroup = {
  486. .name = "arm_gpio_grp",
  487. .pins = arm_gpio_pins,
  488. .npins = ARRAY_SIZE(arm_gpio_pins),
  489. .modemuxs = arm_gpio_modemux,
  490. .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
  491. };
  492. static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
  493. static struct spear_function arm_gpio_function = {
  494. .name = "arm_gpio",
  495. .groups = arm_gpio_grps,
  496. .ngroups = ARRAY_SIZE(arm_gpio_grps),
  497. };
  498. /* Pad multiplexing for smi 2 chips device */
  499. static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
  500. static struct spear_muxreg smi_2_chips_muxreg[] = {
  501. {
  502. .reg = PAD_FUNCTION_EN_0,
  503. .mask = PMX_SMI_MASK,
  504. .val = PMX_SMI_MASK,
  505. }, {
  506. .reg = PAD_DIRECTION_SEL_0,
  507. .mask = PMX_SMI_MASK,
  508. .val = PMX_SMI_MASK,
  509. },
  510. };
  511. static struct spear_modemux smi_2_chips_modemux[] = {
  512. {
  513. .muxregs = smi_2_chips_muxreg,
  514. .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
  515. },
  516. };
  517. static struct spear_pingroup smi_2_chips_pingroup = {
  518. .name = "smi_2_chips_grp",
  519. .pins = smi_2_chips_pins,
  520. .npins = ARRAY_SIZE(smi_2_chips_pins),
  521. .modemuxs = smi_2_chips_modemux,
  522. .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
  523. };
  524. static const unsigned smi_4_chips_pins[] = { 54, 55 };
  525. static struct spear_muxreg smi_4_chips_muxreg[] = {
  526. {
  527. .reg = PAD_FUNCTION_EN_0,
  528. .mask = PMX_SMI_MASK,
  529. .val = PMX_SMI_MASK,
  530. }, {
  531. .reg = PAD_FUNCTION_EN_1,
  532. .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
  533. .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
  534. }, {
  535. .reg = PAD_DIRECTION_SEL_0,
  536. .mask = PMX_SMI_MASK,
  537. .val = PMX_SMI_MASK,
  538. }, {
  539. .reg = PAD_DIRECTION_SEL_1,
  540. .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
  541. .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
  542. },
  543. };
  544. static struct spear_modemux smi_4_chips_modemux[] = {
  545. {
  546. .muxregs = smi_4_chips_muxreg,
  547. .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
  548. },
  549. };
  550. static struct spear_pingroup smi_4_chips_pingroup = {
  551. .name = "smi_4_chips_grp",
  552. .pins = smi_4_chips_pins,
  553. .npins = ARRAY_SIZE(smi_4_chips_pins),
  554. .modemuxs = smi_4_chips_modemux,
  555. .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
  556. };
  557. static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
  558. static struct spear_function smi_function = {
  559. .name = "smi",
  560. .groups = smi_grps,
  561. .ngroups = ARRAY_SIZE(smi_grps),
  562. };
  563. /* Pad multiplexing for gmii device */
  564. static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
  565. 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
  566. 195, 196, 197, 198, 199, 200 };
  567. static struct spear_muxreg gmii_muxreg[] = {
  568. {
  569. .reg = PAD_FUNCTION_EN_0,
  570. .mask = PMX_GMII_MASK,
  571. .val = PMX_GMII_MASK,
  572. }, {
  573. .reg = PAD_DIRECTION_SEL_0,
  574. .mask = PMX_GMII_MASK,
  575. .val = PMX_GMII_MASK,
  576. },
  577. };
  578. static struct spear_modemux gmii_modemux[] = {
  579. {
  580. .muxregs = gmii_muxreg,
  581. .nmuxregs = ARRAY_SIZE(gmii_muxreg),
  582. },
  583. };
  584. static struct spear_pingroup gmii_pingroup = {
  585. .name = "gmii_grp",
  586. .pins = gmii_pins,
  587. .npins = ARRAY_SIZE(gmii_pins),
  588. .modemuxs = gmii_modemux,
  589. .nmodemuxs = ARRAY_SIZE(gmii_modemux),
  590. };
  591. static const char *const gmii_grps[] = { "gmii_grp" };
  592. static struct spear_function gmii_function = {
  593. .name = "gmii",
  594. .groups = gmii_grps,
  595. .ngroups = ARRAY_SIZE(gmii_grps),
  596. };
  597. /* Pad multiplexing for rgmii device */
  598. static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
  599. 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
  600. 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
  601. static struct spear_muxreg rgmii_muxreg[] = {
  602. {
  603. .reg = PAD_FUNCTION_EN_0,
  604. .mask = PMX_RGMII_REG0_MASK,
  605. .val = 0,
  606. }, {
  607. .reg = PAD_FUNCTION_EN_1,
  608. .mask = PMX_RGMII_REG1_MASK,
  609. .val = 0,
  610. }, {
  611. .reg = PAD_FUNCTION_EN_2,
  612. .mask = PMX_RGMII_REG2_MASK,
  613. .val = 0,
  614. }, {
  615. .reg = PAD_DIRECTION_SEL_0,
  616. .mask = PMX_RGMII_REG0_MASK,
  617. .val = PMX_RGMII_REG0_MASK,
  618. }, {
  619. .reg = PAD_DIRECTION_SEL_1,
  620. .mask = PMX_RGMII_REG1_MASK,
  621. .val = PMX_RGMII_REG1_MASK,
  622. }, {
  623. .reg = PAD_DIRECTION_SEL_2,
  624. .mask = PMX_RGMII_REG2_MASK,
  625. .val = PMX_RGMII_REG2_MASK,
  626. },
  627. };
  628. static struct spear_modemux rgmii_modemux[] = {
  629. {
  630. .muxregs = rgmii_muxreg,
  631. .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
  632. },
  633. };
  634. static struct spear_pingroup rgmii_pingroup = {
  635. .name = "rgmii_grp",
  636. .pins = rgmii_pins,
  637. .npins = ARRAY_SIZE(rgmii_pins),
  638. .modemuxs = rgmii_modemux,
  639. .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
  640. };
  641. static const char *const rgmii_grps[] = { "rgmii_grp" };
  642. static struct spear_function rgmii_function = {
  643. .name = "rgmii",
  644. .groups = rgmii_grps,
  645. .ngroups = ARRAY_SIZE(rgmii_grps),
  646. };
  647. /* Pad multiplexing for smii_0_1_2 device */
  648. static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
  649. 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
  650. 51, 52, 53, 54, 55 };
  651. static struct spear_muxreg smii_0_1_2_muxreg[] = {
  652. {
  653. .reg = PAD_FUNCTION_EN_1,
  654. .mask = PMX_SMII_0_1_2_MASK,
  655. .val = 0,
  656. }, {
  657. .reg = PAD_DIRECTION_SEL_1,
  658. .mask = PMX_SMII_0_1_2_MASK,
  659. .val = PMX_SMII_0_1_2_MASK,
  660. },
  661. };
  662. static struct spear_modemux smii_0_1_2_modemux[] = {
  663. {
  664. .muxregs = smii_0_1_2_muxreg,
  665. .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
  666. },
  667. };
  668. static struct spear_pingroup smii_0_1_2_pingroup = {
  669. .name = "smii_0_1_2_grp",
  670. .pins = smii_0_1_2_pins,
  671. .npins = ARRAY_SIZE(smii_0_1_2_pins),
  672. .modemuxs = smii_0_1_2_modemux,
  673. .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
  674. };
  675. static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
  676. static struct spear_function smii_0_1_2_function = {
  677. .name = "smii_0_1_2",
  678. .groups = smii_0_1_2_grps,
  679. .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
  680. };
  681. /* Pad multiplexing for ras_mii_txclk device */
  682. static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
  683. static struct spear_muxreg ras_mii_txclk_muxreg[] = {
  684. {
  685. .reg = PAD_FUNCTION_EN_1,
  686. .mask = PMX_NFCE2_MASK,
  687. .val = 0,
  688. }, {
  689. .reg = PAD_DIRECTION_SEL_1,
  690. .mask = PMX_NFCE2_MASK,
  691. .val = PMX_NFCE2_MASK,
  692. },
  693. };
  694. static struct spear_modemux ras_mii_txclk_modemux[] = {
  695. {
  696. .muxregs = ras_mii_txclk_muxreg,
  697. .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
  698. },
  699. };
  700. static struct spear_pingroup ras_mii_txclk_pingroup = {
  701. .name = "ras_mii_txclk_grp",
  702. .pins = ras_mii_txclk_pins,
  703. .npins = ARRAY_SIZE(ras_mii_txclk_pins),
  704. .modemuxs = ras_mii_txclk_modemux,
  705. .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
  706. };
  707. static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
  708. static struct spear_function ras_mii_txclk_function = {
  709. .name = "ras_mii_txclk",
  710. .groups = ras_mii_txclk_grps,
  711. .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
  712. };
  713. /* Pad multiplexing for nand 8bit device (cs0 only) */
  714. static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
  715. 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
  716. 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
  717. 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
  718. 212 };
  719. static struct spear_muxreg nand_8bit_muxreg[] = {
  720. {
  721. .reg = PAD_FUNCTION_EN_0,
  722. .mask = PMX_NAND8BIT_0_MASK,
  723. .val = PMX_NAND8BIT_0_MASK,
  724. }, {
  725. .reg = PAD_FUNCTION_EN_1,
  726. .mask = PMX_NAND8BIT_1_MASK,
  727. .val = PMX_NAND8BIT_1_MASK,
  728. }, {
  729. .reg = PAD_DIRECTION_SEL_0,
  730. .mask = PMX_NAND8BIT_0_MASK,
  731. .val = PMX_NAND8BIT_0_MASK,
  732. }, {
  733. .reg = PAD_DIRECTION_SEL_1,
  734. .mask = PMX_NAND8BIT_1_MASK,
  735. .val = PMX_NAND8BIT_1_MASK,
  736. },
  737. };
  738. static struct spear_modemux nand_8bit_modemux[] = {
  739. {
  740. .muxregs = nand_8bit_muxreg,
  741. .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
  742. },
  743. };
  744. static struct spear_pingroup nand_8bit_pingroup = {
  745. .name = "nand_8bit_grp",
  746. .pins = nand_8bit_pins,
  747. .npins = ARRAY_SIZE(nand_8bit_pins),
  748. .modemuxs = nand_8bit_modemux,
  749. .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
  750. };
  751. /* Pad multiplexing for nand 16bit device */
  752. static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
  753. 210 };
  754. static struct spear_muxreg nand_16bit_muxreg[] = {
  755. {
  756. .reg = PAD_FUNCTION_EN_1,
  757. .mask = PMX_NAND16BIT_1_MASK,
  758. .val = PMX_NAND16BIT_1_MASK,
  759. }, {
  760. .reg = PAD_DIRECTION_SEL_1,
  761. .mask = PMX_NAND16BIT_1_MASK,
  762. .val = PMX_NAND16BIT_1_MASK,
  763. },
  764. };
  765. static struct spear_modemux nand_16bit_modemux[] = {
  766. {
  767. .muxregs = nand_16bit_muxreg,
  768. .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
  769. },
  770. };
  771. static struct spear_pingroup nand_16bit_pingroup = {
  772. .name = "nand_16bit_grp",
  773. .pins = nand_16bit_pins,
  774. .npins = ARRAY_SIZE(nand_16bit_pins),
  775. .modemuxs = nand_16bit_modemux,
  776. .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
  777. };
  778. /* Pad multiplexing for nand 4 chips */
  779. static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
  780. static struct spear_muxreg nand_4_chips_muxreg[] = {
  781. {
  782. .reg = PAD_FUNCTION_EN_1,
  783. .mask = PMX_NAND_4CHIPS_MASK,
  784. .val = PMX_NAND_4CHIPS_MASK,
  785. }, {
  786. .reg = PAD_DIRECTION_SEL_1,
  787. .mask = PMX_NAND_4CHIPS_MASK,
  788. .val = PMX_NAND_4CHIPS_MASK,
  789. },
  790. };
  791. static struct spear_modemux nand_4_chips_modemux[] = {
  792. {
  793. .muxregs = nand_4_chips_muxreg,
  794. .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
  795. },
  796. };
  797. static struct spear_pingroup nand_4_chips_pingroup = {
  798. .name = "nand_4_chips_grp",
  799. .pins = nand_4_chips_pins,
  800. .npins = ARRAY_SIZE(nand_4_chips_pins),
  801. .modemuxs = nand_4_chips_modemux,
  802. .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
  803. };
  804. static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
  805. "nand_4_chips_grp" };
  806. static struct spear_function nand_function = {
  807. .name = "nand",
  808. .groups = nand_grps,
  809. .ngroups = ARRAY_SIZE(nand_grps),
  810. };
  811. /* Pad multiplexing for keyboard_6x6 device */
  812. static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
  813. 208, 209, 210, 211, 212 };
  814. static struct spear_muxreg keyboard_6x6_muxreg[] = {
  815. {
  816. .reg = PAD_FUNCTION_EN_1,
  817. .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
  818. PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
  819. PMX_NFWPRT2_MASK,
  820. .val = PMX_KEYBOARD_6X6_MASK,
  821. },
  822. };
  823. static struct spear_modemux keyboard_6x6_modemux[] = {
  824. {
  825. .muxregs = keyboard_6x6_muxreg,
  826. .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
  827. },
  828. };
  829. static struct spear_pingroup keyboard_6x6_pingroup = {
  830. .name = "keyboard_6x6_grp",
  831. .pins = keyboard_6x6_pins,
  832. .npins = ARRAY_SIZE(keyboard_6x6_pins),
  833. .modemuxs = keyboard_6x6_modemux,
  834. .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
  835. };
  836. /* Pad multiplexing for keyboard_rowcol6_8 device */
  837. static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
  838. static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
  839. {
  840. .reg = PAD_FUNCTION_EN_1,
  841. .mask = PMX_KBD_ROWCOL68_MASK,
  842. .val = PMX_KBD_ROWCOL68_MASK,
  843. }, {
  844. .reg = PAD_DIRECTION_SEL_1,
  845. .mask = PMX_KBD_ROWCOL68_MASK,
  846. .val = PMX_KBD_ROWCOL68_MASK,
  847. },
  848. };
  849. static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
  850. {
  851. .muxregs = keyboard_rowcol6_8_muxreg,
  852. .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
  853. },
  854. };
  855. static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
  856. .name = "keyboard_rowcol6_8_grp",
  857. .pins = keyboard_rowcol6_8_pins,
  858. .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
  859. .modemuxs = keyboard_rowcol6_8_modemux,
  860. .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
  861. };
  862. static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
  863. "keyboard_rowcol6_8_grp" };
  864. static struct spear_function keyboard_function = {
  865. .name = "keyboard",
  866. .groups = keyboard_grps,
  867. .ngroups = ARRAY_SIZE(keyboard_grps),
  868. };
  869. /* Pad multiplexing for uart0 device */
  870. static const unsigned uart0_pins[] = { 100, 101 };
  871. static struct spear_muxreg uart0_muxreg[] = {
  872. {
  873. .reg = PAD_FUNCTION_EN_0,
  874. .mask = PMX_UART0_MASK,
  875. .val = PMX_UART0_MASK,
  876. }, {
  877. .reg = PAD_DIRECTION_SEL_0,
  878. .mask = PMX_UART0_MASK,
  879. .val = PMX_UART0_MASK,
  880. },
  881. };
  882. static struct spear_modemux uart0_modemux[] = {
  883. {
  884. .muxregs = uart0_muxreg,
  885. .nmuxregs = ARRAY_SIZE(uart0_muxreg),
  886. },
  887. };
  888. static struct spear_pingroup uart0_pingroup = {
  889. .name = "uart0_grp",
  890. .pins = uart0_pins,
  891. .npins = ARRAY_SIZE(uart0_pins),
  892. .modemuxs = uart0_modemux,
  893. .nmodemuxs = ARRAY_SIZE(uart0_modemux),
  894. };
  895. /* Pad multiplexing for uart0_modem device */
  896. static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
  897. static struct spear_muxreg uart0_modem_muxreg[] = {
  898. {
  899. .reg = PAD_FUNCTION_EN_1,
  900. .mask = PMX_UART0_MODEM_MASK,
  901. .val = PMX_UART0_MODEM_MASK,
  902. }, {
  903. .reg = PAD_DIRECTION_SEL_1,
  904. .mask = PMX_UART0_MODEM_MASK,
  905. .val = PMX_UART0_MODEM_MASK,
  906. },
  907. };
  908. static struct spear_modemux uart0_modem_modemux[] = {
  909. {
  910. .muxregs = uart0_modem_muxreg,
  911. .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
  912. },
  913. };
  914. static struct spear_pingroup uart0_modem_pingroup = {
  915. .name = "uart0_modem_grp",
  916. .pins = uart0_modem_pins,
  917. .npins = ARRAY_SIZE(uart0_modem_pins),
  918. .modemuxs = uart0_modem_modemux,
  919. .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
  920. };
  921. static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
  922. static struct spear_function uart0_function = {
  923. .name = "uart0",
  924. .groups = uart0_grps,
  925. .ngroups = ARRAY_SIZE(uart0_grps),
  926. };
  927. /* Pad multiplexing for gpt0_tmr0 device */
  928. static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
  929. static struct spear_muxreg gpt0_tmr0_muxreg[] = {
  930. {
  931. .reg = PAD_FUNCTION_EN_1,
  932. .mask = PMX_GPT0_TMR0_MASK,
  933. .val = PMX_GPT0_TMR0_MASK,
  934. }, {
  935. .reg = PAD_DIRECTION_SEL_1,
  936. .mask = PMX_GPT0_TMR0_MASK,
  937. .val = PMX_GPT0_TMR0_MASK,
  938. },
  939. };
  940. static struct spear_modemux gpt0_tmr0_modemux[] = {
  941. {
  942. .muxregs = gpt0_tmr0_muxreg,
  943. .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
  944. },
  945. };
  946. static struct spear_pingroup gpt0_tmr0_pingroup = {
  947. .name = "gpt0_tmr0_grp",
  948. .pins = gpt0_tmr0_pins,
  949. .npins = ARRAY_SIZE(gpt0_tmr0_pins),
  950. .modemuxs = gpt0_tmr0_modemux,
  951. .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
  952. };
  953. /* Pad multiplexing for gpt0_tmr1 device */
  954. static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
  955. static struct spear_muxreg gpt0_tmr1_muxreg[] = {
  956. {
  957. .reg = PAD_FUNCTION_EN_1,
  958. .mask = PMX_GPT0_TMR1_MASK,
  959. .val = PMX_GPT0_TMR1_MASK,
  960. }, {
  961. .reg = PAD_DIRECTION_SEL_1,
  962. .mask = PMX_GPT0_TMR1_MASK,
  963. .val = PMX_GPT0_TMR1_MASK,
  964. },
  965. };
  966. static struct spear_modemux gpt0_tmr1_modemux[] = {
  967. {
  968. .muxregs = gpt0_tmr1_muxreg,
  969. .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
  970. },
  971. };
  972. static struct spear_pingroup gpt0_tmr1_pingroup = {
  973. .name = "gpt0_tmr1_grp",
  974. .pins = gpt0_tmr1_pins,
  975. .npins = ARRAY_SIZE(gpt0_tmr1_pins),
  976. .modemuxs = gpt0_tmr1_modemux,
  977. .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
  978. };
  979. static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
  980. static struct spear_function gpt0_function = {
  981. .name = "gpt0",
  982. .groups = gpt0_grps,
  983. .ngroups = ARRAY_SIZE(gpt0_grps),
  984. };
  985. /* Pad multiplexing for gpt1_tmr0 device */
  986. static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
  987. static struct spear_muxreg gpt1_tmr0_muxreg[] = {
  988. {
  989. .reg = PAD_FUNCTION_EN_1,
  990. .mask = PMX_GPT1_TMR0_MASK,
  991. .val = PMX_GPT1_TMR0_MASK,
  992. }, {
  993. .reg = PAD_DIRECTION_SEL_1,
  994. .mask = PMX_GPT1_TMR0_MASK,
  995. .val = PMX_GPT1_TMR0_MASK,
  996. },
  997. };
  998. static struct spear_modemux gpt1_tmr0_modemux[] = {
  999. {
  1000. .muxregs = gpt1_tmr0_muxreg,
  1001. .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
  1002. },
  1003. };
  1004. static struct spear_pingroup gpt1_tmr0_pingroup = {
  1005. .name = "gpt1_tmr0_grp",
  1006. .pins = gpt1_tmr0_pins,
  1007. .npins = ARRAY_SIZE(gpt1_tmr0_pins),
  1008. .modemuxs = gpt1_tmr0_modemux,
  1009. .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
  1010. };
  1011. /* Pad multiplexing for gpt1_tmr1 device */
  1012. static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
  1013. static struct spear_muxreg gpt1_tmr1_muxreg[] = {
  1014. {
  1015. .reg = PAD_FUNCTION_EN_1,
  1016. .mask = PMX_GPT1_TMR1_MASK,
  1017. .val = PMX_GPT1_TMR1_MASK,
  1018. }, {
  1019. .reg = PAD_DIRECTION_SEL_1,
  1020. .mask = PMX_GPT1_TMR1_MASK,
  1021. .val = PMX_GPT1_TMR1_MASK,
  1022. },
  1023. };
  1024. static struct spear_modemux gpt1_tmr1_modemux[] = {
  1025. {
  1026. .muxregs = gpt1_tmr1_muxreg,
  1027. .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
  1028. },
  1029. };
  1030. static struct spear_pingroup gpt1_tmr1_pingroup = {
  1031. .name = "gpt1_tmr1_grp",
  1032. .pins = gpt1_tmr1_pins,
  1033. .npins = ARRAY_SIZE(gpt1_tmr1_pins),
  1034. .modemuxs = gpt1_tmr1_modemux,
  1035. .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
  1036. };
  1037. static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
  1038. static struct spear_function gpt1_function = {
  1039. .name = "gpt1",
  1040. .groups = gpt1_grps,
  1041. .ngroups = ARRAY_SIZE(gpt1_grps),
  1042. };
  1043. /* Pad multiplexing for mcif device */
  1044. static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
  1045. 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
  1046. 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
  1047. 243, 244, 245 };
  1048. #define MCIF_MUXREG \
  1049. { \
  1050. .reg = PAD_FUNCTION_EN_0, \
  1051. .mask = PMX_MCI_DATA8_15_MASK, \
  1052. .val = PMX_MCI_DATA8_15_MASK, \
  1053. }, { \
  1054. .reg = PAD_FUNCTION_EN_1, \
  1055. .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
  1056. PMX_NFWPRT2_MASK, \
  1057. .val = PMX_MCIFALL_1_MASK, \
  1058. }, { \
  1059. .reg = PAD_FUNCTION_EN_2, \
  1060. .mask = PMX_MCIFALL_2_MASK, \
  1061. .val = PMX_MCIFALL_2_MASK, \
  1062. }, { \
  1063. .reg = PAD_DIRECTION_SEL_0, \
  1064. .mask = PMX_MCI_DATA8_15_MASK, \
  1065. .val = PMX_MCI_DATA8_15_MASK, \
  1066. }, { \
  1067. .reg = PAD_DIRECTION_SEL_1, \
  1068. .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
  1069. PMX_NFWPRT2_MASK, \
  1070. .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
  1071. PMX_NFWPRT2_MASK, \
  1072. }, { \
  1073. .reg = PAD_DIRECTION_SEL_2, \
  1074. .mask = PMX_MCIFALL_2_MASK, \
  1075. .val = PMX_MCIFALL_2_MASK, \
  1076. }
  1077. /* sdhci device */
  1078. static struct spear_muxreg sdhci_muxreg[] = {
  1079. MCIF_MUXREG,
  1080. {
  1081. .reg = PERIP_CFG,
  1082. .mask = MCIF_SEL_MASK,
  1083. .val = MCIF_SEL_SD,
  1084. },
  1085. };
  1086. static struct spear_modemux sdhci_modemux[] = {
  1087. {
  1088. .muxregs = sdhci_muxreg,
  1089. .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
  1090. },
  1091. };
  1092. static struct spear_pingroup sdhci_pingroup = {
  1093. .name = "sdhci_grp",
  1094. .pins = mcif_pins,
  1095. .npins = ARRAY_SIZE(mcif_pins),
  1096. .modemuxs = sdhci_modemux,
  1097. .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
  1098. };
  1099. static const char *const sdhci_grps[] = { "sdhci_grp" };
  1100. static struct spear_function sdhci_function = {
  1101. .name = "sdhci",
  1102. .groups = sdhci_grps,
  1103. .ngroups = ARRAY_SIZE(sdhci_grps),
  1104. };
  1105. /* cf device */
  1106. static struct spear_muxreg cf_muxreg[] = {
  1107. MCIF_MUXREG,
  1108. {
  1109. .reg = PERIP_CFG,
  1110. .mask = MCIF_SEL_MASK,
  1111. .val = MCIF_SEL_CF,
  1112. },
  1113. };
  1114. static struct spear_modemux cf_modemux[] = {
  1115. {
  1116. .muxregs = cf_muxreg,
  1117. .nmuxregs = ARRAY_SIZE(cf_muxreg),
  1118. },
  1119. };
  1120. static struct spear_pingroup cf_pingroup = {
  1121. .name = "cf_grp",
  1122. .pins = mcif_pins,
  1123. .npins = ARRAY_SIZE(mcif_pins),
  1124. .modemuxs = cf_modemux,
  1125. .nmodemuxs = ARRAY_SIZE(cf_modemux),
  1126. };
  1127. static const char *const cf_grps[] = { "cf_grp" };
  1128. static struct spear_function cf_function = {
  1129. .name = "cf",
  1130. .groups = cf_grps,
  1131. .ngroups = ARRAY_SIZE(cf_grps),
  1132. };
  1133. /* xd device */
  1134. static struct spear_muxreg xd_muxreg[] = {
  1135. MCIF_MUXREG,
  1136. {
  1137. .reg = PERIP_CFG,
  1138. .mask = MCIF_SEL_MASK,
  1139. .val = MCIF_SEL_XD,
  1140. },
  1141. };
  1142. static struct spear_modemux xd_modemux[] = {
  1143. {
  1144. .muxregs = xd_muxreg,
  1145. .nmuxregs = ARRAY_SIZE(xd_muxreg),
  1146. },
  1147. };
  1148. static struct spear_pingroup xd_pingroup = {
  1149. .name = "xd_grp",
  1150. .pins = mcif_pins,
  1151. .npins = ARRAY_SIZE(mcif_pins),
  1152. .modemuxs = xd_modemux,
  1153. .nmodemuxs = ARRAY_SIZE(xd_modemux),
  1154. };
  1155. static const char *const xd_grps[] = { "xd_grp" };
  1156. static struct spear_function xd_function = {
  1157. .name = "xd",
  1158. .groups = xd_grps,
  1159. .ngroups = ARRAY_SIZE(xd_grps),
  1160. };
  1161. /* Pad multiplexing for touch_xy device */
  1162. static const unsigned touch_xy_pins[] = { 97 };
  1163. static struct spear_muxreg touch_xy_muxreg[] = {
  1164. {
  1165. .reg = PAD_FUNCTION_EN_2,
  1166. .mask = PMX_TOUCH_XY_MASK,
  1167. .val = PMX_TOUCH_XY_MASK,
  1168. }, {
  1169. .reg = PAD_DIRECTION_SEL_2,
  1170. .mask = PMX_TOUCH_XY_MASK,
  1171. .val = PMX_TOUCH_XY_MASK,
  1172. },
  1173. };
  1174. static struct spear_modemux touch_xy_modemux[] = {
  1175. {
  1176. .muxregs = touch_xy_muxreg,
  1177. .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
  1178. },
  1179. };
  1180. static struct spear_pingroup touch_xy_pingroup = {
  1181. .name = "touch_xy_grp",
  1182. .pins = touch_xy_pins,
  1183. .npins = ARRAY_SIZE(touch_xy_pins),
  1184. .modemuxs = touch_xy_modemux,
  1185. .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
  1186. };
  1187. static const char *const touch_xy_grps[] = { "touch_xy_grp" };
  1188. static struct spear_function touch_xy_function = {
  1189. .name = "touchscreen",
  1190. .groups = touch_xy_grps,
  1191. .ngroups = ARRAY_SIZE(touch_xy_grps),
  1192. };
  1193. /* Pad multiplexing for uart1 device */
  1194. /* Muxed with I2C */
  1195. static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
  1196. static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
  1197. {
  1198. .reg = PAD_FUNCTION_EN_0,
  1199. .mask = PMX_I2C0_MASK,
  1200. .val = 0,
  1201. }, {
  1202. .reg = PAD_DIRECTION_SEL_0,
  1203. .mask = PMX_I2C0_MASK,
  1204. .val = PMX_I2C0_MASK,
  1205. },
  1206. };
  1207. static struct spear_modemux uart1_dis_i2c_modemux[] = {
  1208. {
  1209. .muxregs = uart1_dis_i2c_muxreg,
  1210. .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
  1211. },
  1212. };
  1213. static struct spear_pingroup uart_1_dis_i2c_pingroup = {
  1214. .name = "uart1_disable_i2c_grp",
  1215. .pins = uart1_dis_i2c_pins,
  1216. .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
  1217. .modemuxs = uart1_dis_i2c_modemux,
  1218. .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
  1219. };
  1220. /* Muxed with SD/MMC */
  1221. static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
  1222. static struct spear_muxreg uart1_dis_sd_muxreg[] = {
  1223. {
  1224. .reg = PAD_FUNCTION_EN_1,
  1225. .mask = PMX_MCIDATA1_MASK |
  1226. PMX_MCIDATA2_MASK,
  1227. .val = 0,
  1228. }, {
  1229. .reg = PAD_DIRECTION_SEL_1,
  1230. .mask = PMX_MCIDATA1_MASK |
  1231. PMX_MCIDATA2_MASK,
  1232. .val = PMX_MCIDATA1_MASK |
  1233. PMX_MCIDATA2_MASK,
  1234. },
  1235. };
  1236. static struct spear_modemux uart1_dis_sd_modemux[] = {
  1237. {
  1238. .muxregs = uart1_dis_sd_muxreg,
  1239. .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
  1240. },
  1241. };
  1242. static struct spear_pingroup uart_1_dis_sd_pingroup = {
  1243. .name = "uart1_disable_sd_grp",
  1244. .pins = uart1_dis_sd_pins,
  1245. .npins = ARRAY_SIZE(uart1_dis_sd_pins),
  1246. .modemuxs = uart1_dis_sd_modemux,
  1247. .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
  1248. };
  1249. static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
  1250. "uart1_disable_sd_grp" };
  1251. static struct spear_function uart1_function = {
  1252. .name = "uart1",
  1253. .groups = uart1_grps,
  1254. .ngroups = ARRAY_SIZE(uart1_grps),
  1255. };
  1256. /* Pad multiplexing for uart2_3 device */
  1257. static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
  1258. static struct spear_muxreg uart2_3_muxreg[] = {
  1259. {
  1260. .reg = PAD_FUNCTION_EN_0,
  1261. .mask = PMX_I2S0_MASK,
  1262. .val = 0,
  1263. }, {
  1264. .reg = PAD_DIRECTION_SEL_0,
  1265. .mask = PMX_I2S0_MASK,
  1266. .val = PMX_I2S0_MASK,
  1267. },
  1268. };
  1269. static struct spear_modemux uart2_3_modemux[] = {
  1270. {
  1271. .muxregs = uart2_3_muxreg,
  1272. .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
  1273. },
  1274. };
  1275. static struct spear_pingroup uart_2_3_pingroup = {
  1276. .name = "uart2_3_grp",
  1277. .pins = uart2_3_pins,
  1278. .npins = ARRAY_SIZE(uart2_3_pins),
  1279. .modemuxs = uart2_3_modemux,
  1280. .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
  1281. };
  1282. static const char *const uart2_3_grps[] = { "uart2_3_grp" };
  1283. static struct spear_function uart2_3_function = {
  1284. .name = "uart2_3",
  1285. .groups = uart2_3_grps,
  1286. .ngroups = ARRAY_SIZE(uart2_3_grps),
  1287. };
  1288. /* Pad multiplexing for uart4 device */
  1289. static const unsigned uart4_pins[] = { 108, 113 };
  1290. static struct spear_muxreg uart4_muxreg[] = {
  1291. {
  1292. .reg = PAD_FUNCTION_EN_0,
  1293. .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
  1294. .val = 0,
  1295. }, {
  1296. .reg = PAD_DIRECTION_SEL_0,
  1297. .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
  1298. .val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
  1299. },
  1300. };
  1301. static struct spear_modemux uart4_modemux[] = {
  1302. {
  1303. .muxregs = uart4_muxreg,
  1304. .nmuxregs = ARRAY_SIZE(uart4_muxreg),
  1305. },
  1306. };
  1307. static struct spear_pingroup uart_4_pingroup = {
  1308. .name = "uart4_grp",
  1309. .pins = uart4_pins,
  1310. .npins = ARRAY_SIZE(uart4_pins),
  1311. .modemuxs = uart4_modemux,
  1312. .nmodemuxs = ARRAY_SIZE(uart4_modemux),
  1313. };
  1314. static const char *const uart4_grps[] = { "uart4_grp" };
  1315. static struct spear_function uart4_function = {
  1316. .name = "uart4",
  1317. .groups = uart4_grps,
  1318. .ngroups = ARRAY_SIZE(uart4_grps),
  1319. };
  1320. /* Pad multiplexing for uart5 device */
  1321. static const unsigned uart5_pins[] = { 114, 115 };
  1322. static struct spear_muxreg uart5_muxreg[] = {
  1323. {
  1324. .reg = PAD_FUNCTION_EN_0,
  1325. .mask = PMX_CLCD1_MASK,
  1326. .val = 0,
  1327. }, {
  1328. .reg = PAD_DIRECTION_SEL_0,
  1329. .mask = PMX_CLCD1_MASK,
  1330. .val = PMX_CLCD1_MASK,
  1331. },
  1332. };
  1333. static struct spear_modemux uart5_modemux[] = {
  1334. {
  1335. .muxregs = uart5_muxreg,
  1336. .nmuxregs = ARRAY_SIZE(uart5_muxreg),
  1337. },
  1338. };
  1339. static struct spear_pingroup uart_5_pingroup = {
  1340. .name = "uart5_grp",
  1341. .pins = uart5_pins,
  1342. .npins = ARRAY_SIZE(uart5_pins),
  1343. .modemuxs = uart5_modemux,
  1344. .nmodemuxs = ARRAY_SIZE(uart5_modemux),
  1345. };
  1346. static const char *const uart5_grps[] = { "uart5_grp" };
  1347. static struct spear_function uart5_function = {
  1348. .name = "uart5",
  1349. .groups = uart5_grps,
  1350. .ngroups = ARRAY_SIZE(uart5_grps),
  1351. };
  1352. /* Pad multiplexing for rs485_0_1_tdm_0_1 device */
  1353. static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
  1354. 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
  1355. 136, 137 };
  1356. static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
  1357. {
  1358. .reg = PAD_FUNCTION_EN_0,
  1359. .mask = PMX_CLCD1_MASK,
  1360. .val = 0,
  1361. }, {
  1362. .reg = PAD_DIRECTION_SEL_0,
  1363. .mask = PMX_CLCD1_MASK,
  1364. .val = PMX_CLCD1_MASK,
  1365. },
  1366. };
  1367. static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
  1368. {
  1369. .muxregs = rs485_0_1_tdm_0_1_muxreg,
  1370. .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
  1371. },
  1372. };
  1373. static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
  1374. .name = "rs485_0_1_tdm_0_1_grp",
  1375. .pins = rs485_0_1_tdm_0_1_pins,
  1376. .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
  1377. .modemuxs = rs485_0_1_tdm_0_1_modemux,
  1378. .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
  1379. };
  1380. static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
  1381. static struct spear_function rs485_0_1_tdm_0_1_function = {
  1382. .name = "rs485_0_1_tdm_0_1",
  1383. .groups = rs485_0_1_tdm_0_1_grps,
  1384. .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
  1385. };
  1386. /* Pad multiplexing for i2c_1_2 device */
  1387. static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
  1388. static struct spear_muxreg i2c_1_2_muxreg[] = {
  1389. {
  1390. .reg = PAD_FUNCTION_EN_0,
  1391. .mask = PMX_CLCD1_MASK,
  1392. .val = 0,
  1393. }, {
  1394. .reg = PAD_DIRECTION_SEL_0,
  1395. .mask = PMX_CLCD1_MASK,
  1396. .val = PMX_CLCD1_MASK,
  1397. },
  1398. };
  1399. static struct spear_modemux i2c_1_2_modemux[] = {
  1400. {
  1401. .muxregs = i2c_1_2_muxreg,
  1402. .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
  1403. },
  1404. };
  1405. static struct spear_pingroup i2c_1_2_pingroup = {
  1406. .name = "i2c_1_2_grp",
  1407. .pins = i2c_1_2_pins,
  1408. .npins = ARRAY_SIZE(i2c_1_2_pins),
  1409. .modemuxs = i2c_1_2_modemux,
  1410. .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
  1411. };
  1412. static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
  1413. static struct spear_function i2c_1_2_function = {
  1414. .name = "i2c_1_2",
  1415. .groups = i2c_1_2_grps,
  1416. .ngroups = ARRAY_SIZE(i2c_1_2_grps),
  1417. };
  1418. /* Pad multiplexing for i2c3_dis_smi_clcd device */
  1419. /* Muxed with SMI & CLCD */
  1420. static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
  1421. static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
  1422. {
  1423. .reg = PAD_FUNCTION_EN_0,
  1424. .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
  1425. .val = 0,
  1426. }, {
  1427. .reg = PAD_DIRECTION_SEL_0,
  1428. .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
  1429. .val = PMX_CLCD1_MASK | PMX_SMI_MASK,
  1430. },
  1431. };
  1432. static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
  1433. {
  1434. .muxregs = i2c3_dis_smi_clcd_muxreg,
  1435. .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
  1436. },
  1437. };
  1438. static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
  1439. .name = "i2c3_dis_smi_clcd_grp",
  1440. .pins = i2c3_dis_smi_clcd_pins,
  1441. .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
  1442. .modemuxs = i2c3_dis_smi_clcd_modemux,
  1443. .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
  1444. };
  1445. /* Pad multiplexing for i2c3_dis_sd_i2s0 device */
  1446. /* Muxed with SD/MMC & I2S1 */
  1447. static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
  1448. static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
  1449. {
  1450. .reg = PAD_FUNCTION_EN_1,
  1451. .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
  1452. .val = 0,
  1453. }, {
  1454. .reg = PAD_DIRECTION_SEL_1,
  1455. .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
  1456. .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
  1457. },
  1458. };
  1459. static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
  1460. {
  1461. .muxregs = i2c3_dis_sd_i2s0_muxreg,
  1462. .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
  1463. },
  1464. };
  1465. static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
  1466. .name = "i2c3_dis_sd_i2s0_grp",
  1467. .pins = i2c3_dis_sd_i2s0_pins,
  1468. .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
  1469. .modemuxs = i2c3_dis_sd_i2s0_modemux,
  1470. .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
  1471. };
  1472. static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
  1473. "i2c3_dis_sd_i2s0_grp" };
  1474. static struct spear_function i2c3_unction = {
  1475. .name = "i2c3_i2s1",
  1476. .groups = i2c3_grps,
  1477. .ngroups = ARRAY_SIZE(i2c3_grps),
  1478. };
  1479. /* Pad multiplexing for i2c_4_5_dis_smi device */
  1480. /* Muxed with SMI */
  1481. static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
  1482. static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
  1483. {
  1484. .reg = PAD_FUNCTION_EN_0,
  1485. .mask = PMX_SMI_MASK,
  1486. .val = 0,
  1487. }, {
  1488. .reg = PAD_DIRECTION_SEL_0,
  1489. .mask = PMX_SMI_MASK,
  1490. .val = PMX_SMI_MASK,
  1491. },
  1492. };
  1493. static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
  1494. {
  1495. .muxregs = i2c_4_5_dis_smi_muxreg,
  1496. .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
  1497. },
  1498. };
  1499. static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
  1500. .name = "i2c_4_5_dis_smi_grp",
  1501. .pins = i2c_4_5_dis_smi_pins,
  1502. .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
  1503. .modemuxs = i2c_4_5_dis_smi_modemux,
  1504. .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
  1505. };
  1506. /* Pad multiplexing for i2c4_dis_sd device */
  1507. /* Muxed with SD/MMC */
  1508. static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
  1509. static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
  1510. {
  1511. .reg = PAD_FUNCTION_EN_1,
  1512. .mask = PMX_MCIDATA4_MASK,
  1513. .val = 0,
  1514. }, {
  1515. .reg = PAD_FUNCTION_EN_2,
  1516. .mask = PMX_MCIDATA5_MASK,
  1517. .val = 0,
  1518. }, {
  1519. .reg = PAD_DIRECTION_SEL_1,
  1520. .mask = PMX_MCIDATA4_MASK,
  1521. .val = PMX_MCIDATA4_MASK,
  1522. }, {
  1523. .reg = PAD_DIRECTION_SEL_2,
  1524. .mask = PMX_MCIDATA5_MASK,
  1525. .val = PMX_MCIDATA5_MASK,
  1526. },
  1527. };
  1528. static struct spear_modemux i2c4_dis_sd_modemux[] = {
  1529. {
  1530. .muxregs = i2c4_dis_sd_muxreg,
  1531. .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
  1532. },
  1533. };
  1534. static struct spear_pingroup i2c4_dis_sd_pingroup = {
  1535. .name = "i2c4_dis_sd_grp",
  1536. .pins = i2c4_dis_sd_pins,
  1537. .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
  1538. .modemuxs = i2c4_dis_sd_modemux,
  1539. .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
  1540. };
  1541. /* Pad multiplexing for i2c5_dis_sd device */
  1542. /* Muxed with SD/MMC */
  1543. static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
  1544. static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
  1545. {
  1546. .reg = PAD_FUNCTION_EN_2,
  1547. .mask = PMX_MCIDATA6_MASK |
  1548. PMX_MCIDATA7_MASK,
  1549. .val = 0,
  1550. }, {
  1551. .reg = PAD_DIRECTION_SEL_2,
  1552. .mask = PMX_MCIDATA6_MASK |
  1553. PMX_MCIDATA7_MASK,
  1554. .val = PMX_MCIDATA6_MASK |
  1555. PMX_MCIDATA7_MASK,
  1556. },
  1557. };
  1558. static struct spear_modemux i2c5_dis_sd_modemux[] = {
  1559. {
  1560. .muxregs = i2c5_dis_sd_muxreg,
  1561. .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
  1562. },
  1563. };
  1564. static struct spear_pingroup i2c5_dis_sd_pingroup = {
  1565. .name = "i2c5_dis_sd_grp",
  1566. .pins = i2c5_dis_sd_pins,
  1567. .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
  1568. .modemuxs = i2c5_dis_sd_modemux,
  1569. .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
  1570. };
  1571. static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
  1572. "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
  1573. static struct spear_function i2c_4_5_function = {
  1574. .name = "i2c_4_5",
  1575. .groups = i2c_4_5_grps,
  1576. .ngroups = ARRAY_SIZE(i2c_4_5_grps),
  1577. };
  1578. /* Pad multiplexing for i2c_6_7_dis_kbd device */
  1579. /* Muxed with KBD */
  1580. static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
  1581. static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
  1582. {
  1583. .reg = PAD_FUNCTION_EN_1,
  1584. .mask = PMX_KBD_ROWCOL25_MASK,
  1585. .val = 0,
  1586. }, {
  1587. .reg = PAD_DIRECTION_SEL_1,
  1588. .mask = PMX_KBD_ROWCOL25_MASK,
  1589. .val = PMX_KBD_ROWCOL25_MASK,
  1590. },
  1591. };
  1592. static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
  1593. {
  1594. .muxregs = i2c_6_7_dis_kbd_muxreg,
  1595. .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
  1596. },
  1597. };
  1598. static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
  1599. .name = "i2c_6_7_dis_kbd_grp",
  1600. .pins = i2c_6_7_dis_kbd_pins,
  1601. .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
  1602. .modemuxs = i2c_6_7_dis_kbd_modemux,
  1603. .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
  1604. };
  1605. /* Pad multiplexing for i2c6_dis_sd device */
  1606. /* Muxed with SD/MMC */
  1607. static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
  1608. static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
  1609. {
  1610. .reg = PAD_FUNCTION_EN_2,
  1611. .mask = PMX_MCIIORDRE_MASK |
  1612. PMX_MCIIOWRWE_MASK,
  1613. .val = 0,
  1614. }, {
  1615. .reg = PAD_DIRECTION_SEL_2,
  1616. .mask = PMX_MCIIORDRE_MASK |
  1617. PMX_MCIIOWRWE_MASK,
  1618. .val = PMX_MCIIORDRE_MASK |
  1619. PMX_MCIIOWRWE_MASK,
  1620. },
  1621. };
  1622. static struct spear_modemux i2c6_dis_sd_modemux[] = {
  1623. {
  1624. .muxregs = i2c6_dis_sd_muxreg,
  1625. .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
  1626. },
  1627. };
  1628. static struct spear_pingroup i2c6_dis_sd_pingroup = {
  1629. .name = "i2c6_dis_sd_grp",
  1630. .pins = i2c6_dis_sd_pins,
  1631. .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
  1632. .modemuxs = i2c6_dis_sd_modemux,
  1633. .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
  1634. };
  1635. /* Pad multiplexing for i2c7_dis_sd device */
  1636. static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
  1637. static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
  1638. {
  1639. .reg = PAD_FUNCTION_EN_2,
  1640. .mask = PMX_MCIRESETCF_MASK |
  1641. PMX_MCICS0CE_MASK,
  1642. .val = 0,
  1643. }, {
  1644. .reg = PAD_DIRECTION_SEL_2,
  1645. .mask = PMX_MCIRESETCF_MASK |
  1646. PMX_MCICS0CE_MASK,
  1647. .val = PMX_MCIRESETCF_MASK |
  1648. PMX_MCICS0CE_MASK,
  1649. },
  1650. };
  1651. static struct spear_modemux i2c7_dis_sd_modemux[] = {
  1652. {
  1653. .muxregs = i2c7_dis_sd_muxreg,
  1654. .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
  1655. },
  1656. };
  1657. static struct spear_pingroup i2c7_dis_sd_pingroup = {
  1658. .name = "i2c7_dis_sd_grp",
  1659. .pins = i2c7_dis_sd_pins,
  1660. .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
  1661. .modemuxs = i2c7_dis_sd_modemux,
  1662. .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
  1663. };
  1664. static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
  1665. "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
  1666. static struct spear_function i2c_6_7_function = {
  1667. .name = "i2c_6_7",
  1668. .groups = i2c_6_7_grps,
  1669. .ngroups = ARRAY_SIZE(i2c_6_7_grps),
  1670. };
  1671. /* Pad multiplexing for can0_dis_nor device */
  1672. /* Muxed with NOR */
  1673. static const unsigned can0_dis_nor_pins[] = { 56, 57 };
  1674. static struct spear_muxreg can0_dis_nor_muxreg[] = {
  1675. {
  1676. .reg = PAD_FUNCTION_EN_0,
  1677. .mask = PMX_NFRSTPWDWN2_MASK,
  1678. .val = 0,
  1679. }, {
  1680. .reg = PAD_FUNCTION_EN_1,
  1681. .mask = PMX_NFRSTPWDWN3_MASK,
  1682. .val = 0,
  1683. }, {
  1684. .reg = PAD_DIRECTION_SEL_0,
  1685. .mask = PMX_NFRSTPWDWN2_MASK,
  1686. .val = PMX_NFRSTPWDWN2_MASK,
  1687. }, {
  1688. .reg = PAD_DIRECTION_SEL_1,
  1689. .mask = PMX_NFRSTPWDWN3_MASK,
  1690. .val = PMX_NFRSTPWDWN3_MASK,
  1691. },
  1692. };
  1693. static struct spear_modemux can0_dis_nor_modemux[] = {
  1694. {
  1695. .muxregs = can0_dis_nor_muxreg,
  1696. .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
  1697. },
  1698. };
  1699. static struct spear_pingroup can0_dis_nor_pingroup = {
  1700. .name = "can0_dis_nor_grp",
  1701. .pins = can0_dis_nor_pins,
  1702. .npins = ARRAY_SIZE(can0_dis_nor_pins),
  1703. .modemuxs = can0_dis_nor_modemux,
  1704. .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
  1705. };
  1706. /* Pad multiplexing for can0_dis_sd device */
  1707. /* Muxed with SD/MMC */
  1708. static const unsigned can0_dis_sd_pins[] = { 240, 241 };
  1709. static struct spear_muxreg can0_dis_sd_muxreg[] = {
  1710. {
  1711. .reg = PAD_FUNCTION_EN_2,
  1712. .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
  1713. .val = 0,
  1714. }, {
  1715. .reg = PAD_DIRECTION_SEL_2,
  1716. .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
  1717. .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
  1718. },
  1719. };
  1720. static struct spear_modemux can0_dis_sd_modemux[] = {
  1721. {
  1722. .muxregs = can0_dis_sd_muxreg,
  1723. .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
  1724. },
  1725. };
  1726. static struct spear_pingroup can0_dis_sd_pingroup = {
  1727. .name = "can0_dis_sd_grp",
  1728. .pins = can0_dis_sd_pins,
  1729. .npins = ARRAY_SIZE(can0_dis_sd_pins),
  1730. .modemuxs = can0_dis_sd_modemux,
  1731. .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
  1732. };
  1733. static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
  1734. };
  1735. static struct spear_function can0_function = {
  1736. .name = "can0",
  1737. .groups = can0_grps,
  1738. .ngroups = ARRAY_SIZE(can0_grps),
  1739. };
  1740. /* Pad multiplexing for can1_dis_sd device */
  1741. /* Muxed with SD/MMC */
  1742. static const unsigned can1_dis_sd_pins[] = { 242, 243 };
  1743. static struct spear_muxreg can1_dis_sd_muxreg[] = {
  1744. {
  1745. .reg = PAD_FUNCTION_EN_2,
  1746. .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
  1747. .val = 0,
  1748. }, {
  1749. .reg = PAD_DIRECTION_SEL_2,
  1750. .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
  1751. .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
  1752. },
  1753. };
  1754. static struct spear_modemux can1_dis_sd_modemux[] = {
  1755. {
  1756. .muxregs = can1_dis_sd_muxreg,
  1757. .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
  1758. },
  1759. };
  1760. static struct spear_pingroup can1_dis_sd_pingroup = {
  1761. .name = "can1_dis_sd_grp",
  1762. .pins = can1_dis_sd_pins,
  1763. .npins = ARRAY_SIZE(can1_dis_sd_pins),
  1764. .modemuxs = can1_dis_sd_modemux,
  1765. .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
  1766. };
  1767. /* Pad multiplexing for can1_dis_kbd device */
  1768. /* Muxed with KBD */
  1769. static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
  1770. static struct spear_muxreg can1_dis_kbd_muxreg[] = {
  1771. {
  1772. .reg = PAD_FUNCTION_EN_1,
  1773. .mask = PMX_KBD_ROWCOL25_MASK,
  1774. .val = 0,
  1775. }, {
  1776. .reg = PAD_DIRECTION_SEL_1,
  1777. .mask = PMX_KBD_ROWCOL25_MASK,
  1778. .val = PMX_KBD_ROWCOL25_MASK,
  1779. },
  1780. };
  1781. static struct spear_modemux can1_dis_kbd_modemux[] = {
  1782. {
  1783. .muxregs = can1_dis_kbd_muxreg,
  1784. .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
  1785. },
  1786. };
  1787. static struct spear_pingroup can1_dis_kbd_pingroup = {
  1788. .name = "can1_dis_kbd_grp",
  1789. .pins = can1_dis_kbd_pins,
  1790. .npins = ARRAY_SIZE(can1_dis_kbd_pins),
  1791. .modemuxs = can1_dis_kbd_modemux,
  1792. .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
  1793. };
  1794. static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
  1795. };
  1796. static struct spear_function can1_function = {
  1797. .name = "can1",
  1798. .groups = can1_grps,
  1799. .ngroups = ARRAY_SIZE(can1_grps),
  1800. };
  1801. /* Pad multiplexing for (ras-ip) pci device */
  1802. static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
  1803. 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
  1804. 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
  1805. 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
  1806. static struct spear_muxreg pci_muxreg[] = {
  1807. {
  1808. .reg = PAD_FUNCTION_EN_0,
  1809. .mask = PMX_MCI_DATA8_15_MASK,
  1810. .val = 0,
  1811. }, {
  1812. .reg = PAD_FUNCTION_EN_1,
  1813. .mask = PMX_PCI_REG1_MASK,
  1814. .val = 0,
  1815. }, {
  1816. .reg = PAD_FUNCTION_EN_2,
  1817. .mask = PMX_PCI_REG2_MASK,
  1818. .val = 0,
  1819. }, {
  1820. .reg = PAD_DIRECTION_SEL_0,
  1821. .mask = PMX_MCI_DATA8_15_MASK,
  1822. .val = PMX_MCI_DATA8_15_MASK,
  1823. }, {
  1824. .reg = PAD_DIRECTION_SEL_1,
  1825. .mask = PMX_PCI_REG1_MASK,
  1826. .val = PMX_PCI_REG1_MASK,
  1827. }, {
  1828. .reg = PAD_DIRECTION_SEL_2,
  1829. .mask = PMX_PCI_REG2_MASK,
  1830. .val = PMX_PCI_REG2_MASK,
  1831. },
  1832. };
  1833. static struct spear_modemux pci_modemux[] = {
  1834. {
  1835. .muxregs = pci_muxreg,
  1836. .nmuxregs = ARRAY_SIZE(pci_muxreg),
  1837. },
  1838. };
  1839. static struct spear_pingroup pci_pingroup = {
  1840. .name = "pci_grp",
  1841. .pins = pci_pins,
  1842. .npins = ARRAY_SIZE(pci_pins),
  1843. .modemuxs = pci_modemux,
  1844. .nmodemuxs = ARRAY_SIZE(pci_modemux),
  1845. };
  1846. static const char *const pci_grps[] = { "pci_grp" };
  1847. static struct spear_function pci_function = {
  1848. .name = "pci",
  1849. .groups = pci_grps,
  1850. .ngroups = ARRAY_SIZE(pci_grps),
  1851. };
  1852. /* pad multiplexing for (fix-part) pcie0 device */
  1853. static struct spear_muxreg pcie0_muxreg[] = {
  1854. {
  1855. .reg = PCIE_SATA_CFG,
  1856. .mask = PCIE_CFG_VAL(0),
  1857. .val = PCIE_CFG_VAL(0),
  1858. },
  1859. };
  1860. static struct spear_modemux pcie0_modemux[] = {
  1861. {
  1862. .muxregs = pcie0_muxreg,
  1863. .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
  1864. },
  1865. };
  1866. static struct spear_pingroup pcie0_pingroup = {
  1867. .name = "pcie0_grp",
  1868. .modemuxs = pcie0_modemux,
  1869. .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
  1870. };
  1871. /* pad multiplexing for (fix-part) pcie1 device */
  1872. static struct spear_muxreg pcie1_muxreg[] = {
  1873. {
  1874. .reg = PCIE_SATA_CFG,
  1875. .mask = PCIE_CFG_VAL(1),
  1876. .val = PCIE_CFG_VAL(1),
  1877. },
  1878. };
  1879. static struct spear_modemux pcie1_modemux[] = {
  1880. {
  1881. .muxregs = pcie1_muxreg,
  1882. .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
  1883. },
  1884. };
  1885. static struct spear_pingroup pcie1_pingroup = {
  1886. .name = "pcie1_grp",
  1887. .modemuxs = pcie1_modemux,
  1888. .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
  1889. };
  1890. /* pad multiplexing for (fix-part) pcie2 device */
  1891. static struct spear_muxreg pcie2_muxreg[] = {
  1892. {
  1893. .reg = PCIE_SATA_CFG,
  1894. .mask = PCIE_CFG_VAL(2),
  1895. .val = PCIE_CFG_VAL(2),
  1896. },
  1897. };
  1898. static struct spear_modemux pcie2_modemux[] = {
  1899. {
  1900. .muxregs = pcie2_muxreg,
  1901. .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
  1902. },
  1903. };
  1904. static struct spear_pingroup pcie2_pingroup = {
  1905. .name = "pcie2_grp",
  1906. .modemuxs = pcie2_modemux,
  1907. .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
  1908. };
  1909. static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
  1910. };
  1911. static struct spear_function pcie_function = {
  1912. .name = "pci_express",
  1913. .groups = pcie_grps,
  1914. .ngroups = ARRAY_SIZE(pcie_grps),
  1915. };
  1916. /* pad multiplexing for sata0 device */
  1917. static struct spear_muxreg sata0_muxreg[] = {
  1918. {
  1919. .reg = PCIE_SATA_CFG,
  1920. .mask = SATA_CFG_VAL(0),
  1921. .val = SATA_CFG_VAL(0),
  1922. },
  1923. };
  1924. static struct spear_modemux sata0_modemux[] = {
  1925. {
  1926. .muxregs = sata0_muxreg,
  1927. .nmuxregs = ARRAY_SIZE(sata0_muxreg),
  1928. },
  1929. };
  1930. static struct spear_pingroup sata0_pingroup = {
  1931. .name = "sata0_grp",
  1932. .modemuxs = sata0_modemux,
  1933. .nmodemuxs = ARRAY_SIZE(sata0_modemux),
  1934. };
  1935. /* pad multiplexing for sata1 device */
  1936. static struct spear_muxreg sata1_muxreg[] = {
  1937. {
  1938. .reg = PCIE_SATA_CFG,
  1939. .mask = SATA_CFG_VAL(1),
  1940. .val = SATA_CFG_VAL(1),
  1941. },
  1942. };
  1943. static struct spear_modemux sata1_modemux[] = {
  1944. {
  1945. .muxregs = sata1_muxreg,
  1946. .nmuxregs = ARRAY_SIZE(sata1_muxreg),
  1947. },
  1948. };
  1949. static struct spear_pingroup sata1_pingroup = {
  1950. .name = "sata1_grp",
  1951. .modemuxs = sata1_modemux,
  1952. .nmodemuxs = ARRAY_SIZE(sata1_modemux),
  1953. };
  1954. /* pad multiplexing for sata2 device */
  1955. static struct spear_muxreg sata2_muxreg[] = {
  1956. {
  1957. .reg = PCIE_SATA_CFG,
  1958. .mask = SATA_CFG_VAL(2),
  1959. .val = SATA_CFG_VAL(2),
  1960. },
  1961. };
  1962. static struct spear_modemux sata2_modemux[] = {
  1963. {
  1964. .muxregs = sata2_muxreg,
  1965. .nmuxregs = ARRAY_SIZE(sata2_muxreg),
  1966. },
  1967. };
  1968. static struct spear_pingroup sata2_pingroup = {
  1969. .name = "sata2_grp",
  1970. .modemuxs = sata2_modemux,
  1971. .nmodemuxs = ARRAY_SIZE(sata2_modemux),
  1972. };
  1973. static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
  1974. };
  1975. static struct spear_function sata_function = {
  1976. .name = "sata",
  1977. .groups = sata_grps,
  1978. .ngroups = ARRAY_SIZE(sata_grps),
  1979. };
  1980. /* Pad multiplexing for ssp1_dis_kbd device */
  1981. static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
  1982. static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
  1983. {
  1984. .reg = PAD_FUNCTION_EN_1,
  1985. .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
  1986. PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
  1987. PMX_NFCE2_MASK,
  1988. .val = 0,
  1989. }, {
  1990. .reg = PAD_DIRECTION_SEL_1,
  1991. .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
  1992. PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
  1993. PMX_NFCE2_MASK,
  1994. .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
  1995. PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
  1996. PMX_NFCE2_MASK,
  1997. },
  1998. };
  1999. static struct spear_modemux ssp1_dis_kbd_modemux[] = {
  2000. {
  2001. .muxregs = ssp1_dis_kbd_muxreg,
  2002. .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
  2003. },
  2004. };
  2005. static struct spear_pingroup ssp1_dis_kbd_pingroup = {
  2006. .name = "ssp1_dis_kbd_grp",
  2007. .pins = ssp1_dis_kbd_pins,
  2008. .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
  2009. .modemuxs = ssp1_dis_kbd_modemux,
  2010. .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
  2011. };
  2012. /* Pad multiplexing for ssp1_dis_sd device */
  2013. static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
  2014. static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
  2015. {
  2016. .reg = PAD_FUNCTION_EN_2,
  2017. .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
  2018. PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
  2019. .val = 0,
  2020. }, {
  2021. .reg = PAD_DIRECTION_SEL_2,
  2022. .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
  2023. PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
  2024. .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
  2025. PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
  2026. },
  2027. };
  2028. static struct spear_modemux ssp1_dis_sd_modemux[] = {
  2029. {
  2030. .muxregs = ssp1_dis_sd_muxreg,
  2031. .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
  2032. },
  2033. };
  2034. static struct spear_pingroup ssp1_dis_sd_pingroup = {
  2035. .name = "ssp1_dis_sd_grp",
  2036. .pins = ssp1_dis_sd_pins,
  2037. .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
  2038. .modemuxs = ssp1_dis_sd_modemux,
  2039. .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
  2040. };
  2041. static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
  2042. "ssp1_dis_sd_grp" };
  2043. static struct spear_function ssp1_function = {
  2044. .name = "ssp1",
  2045. .groups = ssp1_grps,
  2046. .ngroups = ARRAY_SIZE(ssp1_grps),
  2047. };
  2048. /* Pad multiplexing for gpt64 device */
  2049. static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
  2050. static struct spear_muxreg gpt64_muxreg[] = {
  2051. {
  2052. .reg = PAD_FUNCTION_EN_2,
  2053. .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
  2054. | PMX_MCILEDS_MASK,
  2055. .val = 0,
  2056. }, {
  2057. .reg = PAD_DIRECTION_SEL_2,
  2058. .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
  2059. | PMX_MCILEDS_MASK,
  2060. .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
  2061. | PMX_MCILEDS_MASK,
  2062. },
  2063. };
  2064. static struct spear_modemux gpt64_modemux[] = {
  2065. {
  2066. .muxregs = gpt64_muxreg,
  2067. .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
  2068. },
  2069. };
  2070. static struct spear_pingroup gpt64_pingroup = {
  2071. .name = "gpt64_grp",
  2072. .pins = gpt64_pins,
  2073. .npins = ARRAY_SIZE(gpt64_pins),
  2074. .modemuxs = gpt64_modemux,
  2075. .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
  2076. };
  2077. static const char *const gpt64_grps[] = { "gpt64_grp" };
  2078. static struct spear_function gpt64_function = {
  2079. .name = "gpt64",
  2080. .groups = gpt64_grps,
  2081. .ngroups = ARRAY_SIZE(gpt64_grps),
  2082. };
  2083. /* pingroups */
  2084. static struct spear_pingroup *spear1310_pingroups[] = {
  2085. &i2c0_pingroup,
  2086. &ssp0_pingroup,
  2087. &i2s0_pingroup,
  2088. &i2s1_pingroup,
  2089. &clcd_pingroup,
  2090. &clcd_high_res_pingroup,
  2091. &arm_gpio_pingroup,
  2092. &smi_2_chips_pingroup,
  2093. &smi_4_chips_pingroup,
  2094. &gmii_pingroup,
  2095. &rgmii_pingroup,
  2096. &smii_0_1_2_pingroup,
  2097. &ras_mii_txclk_pingroup,
  2098. &nand_8bit_pingroup,
  2099. &nand_16bit_pingroup,
  2100. &nand_4_chips_pingroup,
  2101. &keyboard_6x6_pingroup,
  2102. &keyboard_rowcol6_8_pingroup,
  2103. &uart0_pingroup,
  2104. &uart0_modem_pingroup,
  2105. &gpt0_tmr0_pingroup,
  2106. &gpt0_tmr1_pingroup,
  2107. &gpt1_tmr0_pingroup,
  2108. &gpt1_tmr1_pingroup,
  2109. &sdhci_pingroup,
  2110. &cf_pingroup,
  2111. &xd_pingroup,
  2112. &touch_xy_pingroup,
  2113. &ssp0_cs0_pingroup,
  2114. &ssp0_cs1_2_pingroup,
  2115. &uart_1_dis_i2c_pingroup,
  2116. &uart_1_dis_sd_pingroup,
  2117. &uart_2_3_pingroup,
  2118. &uart_4_pingroup,
  2119. &uart_5_pingroup,
  2120. &rs485_0_1_tdm_0_1_pingroup,
  2121. &i2c_1_2_pingroup,
  2122. &i2c3_dis_smi_clcd_pingroup,
  2123. &i2c3_dis_sd_i2s0_pingroup,
  2124. &i2c_4_5_dis_smi_pingroup,
  2125. &i2c4_dis_sd_pingroup,
  2126. &i2c5_dis_sd_pingroup,
  2127. &i2c_6_7_dis_kbd_pingroup,
  2128. &i2c6_dis_sd_pingroup,
  2129. &i2c7_dis_sd_pingroup,
  2130. &can0_dis_nor_pingroup,
  2131. &can0_dis_sd_pingroup,
  2132. &can1_dis_sd_pingroup,
  2133. &can1_dis_kbd_pingroup,
  2134. &pci_pingroup,
  2135. &pcie0_pingroup,
  2136. &pcie1_pingroup,
  2137. &pcie2_pingroup,
  2138. &sata0_pingroup,
  2139. &sata1_pingroup,
  2140. &sata2_pingroup,
  2141. &ssp1_dis_kbd_pingroup,
  2142. &ssp1_dis_sd_pingroup,
  2143. &gpt64_pingroup,
  2144. };
  2145. /* functions */
  2146. static struct spear_function *spear1310_functions[] = {
  2147. &i2c0_function,
  2148. &ssp0_function,
  2149. &i2s0_function,
  2150. &i2s1_function,
  2151. &clcd_function,
  2152. &arm_gpio_function,
  2153. &smi_function,
  2154. &gmii_function,
  2155. &rgmii_function,
  2156. &smii_0_1_2_function,
  2157. &ras_mii_txclk_function,
  2158. &nand_function,
  2159. &keyboard_function,
  2160. &uart0_function,
  2161. &gpt0_function,
  2162. &gpt1_function,
  2163. &sdhci_function,
  2164. &cf_function,
  2165. &xd_function,
  2166. &touch_xy_function,
  2167. &uart1_function,
  2168. &uart2_3_function,
  2169. &uart4_function,
  2170. &uart5_function,
  2171. &rs485_0_1_tdm_0_1_function,
  2172. &i2c_1_2_function,
  2173. &i2c3_unction,
  2174. &i2c_4_5_function,
  2175. &i2c_6_7_function,
  2176. &can0_function,
  2177. &can1_function,
  2178. &pci_function,
  2179. &pcie_function,
  2180. &sata_function,
  2181. &ssp1_function,
  2182. &gpt64_function,
  2183. };
  2184. static const unsigned pin18[] = { 18, };
  2185. static const unsigned pin19[] = { 19, };
  2186. static const unsigned pin20[] = { 20, };
  2187. static const unsigned pin21[] = { 21, };
  2188. static const unsigned pin22[] = { 22, };
  2189. static const unsigned pin23[] = { 23, };
  2190. static const unsigned pin54[] = { 54, };
  2191. static const unsigned pin55[] = { 55, };
  2192. static const unsigned pin56[] = { 56, };
  2193. static const unsigned pin57[] = { 57, };
  2194. static const unsigned pin58[] = { 58, };
  2195. static const unsigned pin59[] = { 59, };
  2196. static const unsigned pin60[] = { 60, };
  2197. static const unsigned pin61[] = { 61, };
  2198. static const unsigned pin62[] = { 62, };
  2199. static const unsigned pin63[] = { 63, };
  2200. static const unsigned pin143[] = { 143, };
  2201. static const unsigned pin144[] = { 144, };
  2202. static const unsigned pin145[] = { 145, };
  2203. static const unsigned pin146[] = { 146, };
  2204. static const unsigned pin147[] = { 147, };
  2205. static const unsigned pin148[] = { 148, };
  2206. static const unsigned pin149[] = { 149, };
  2207. static const unsigned pin150[] = { 150, };
  2208. static const unsigned pin151[] = { 151, };
  2209. static const unsigned pin152[] = { 152, };
  2210. static const unsigned pin205[] = { 205, };
  2211. static const unsigned pin206[] = { 206, };
  2212. static const unsigned pin211[] = { 211, };
  2213. static const unsigned pin212[] = { 212, };
  2214. static const unsigned pin213[] = { 213, };
  2215. static const unsigned pin214[] = { 214, };
  2216. static const unsigned pin215[] = { 215, };
  2217. static const unsigned pin216[] = { 216, };
  2218. static const unsigned pin217[] = { 217, };
  2219. static const unsigned pin218[] = { 218, };
  2220. static const unsigned pin219[] = { 219, };
  2221. static const unsigned pin220[] = { 220, };
  2222. static const unsigned pin221[] = { 221, };
  2223. static const unsigned pin222[] = { 222, };
  2224. static const unsigned pin223[] = { 223, };
  2225. static const unsigned pin224[] = { 224, };
  2226. static const unsigned pin225[] = { 225, };
  2227. static const unsigned pin226[] = { 226, };
  2228. static const unsigned pin227[] = { 227, };
  2229. static const unsigned pin228[] = { 228, };
  2230. static const unsigned pin229[] = { 229, };
  2231. static const unsigned pin230[] = { 230, };
  2232. static const unsigned pin231[] = { 231, };
  2233. static const unsigned pin232[] = { 232, };
  2234. static const unsigned pin233[] = { 233, };
  2235. static const unsigned pin234[] = { 234, };
  2236. static const unsigned pin235[] = { 235, };
  2237. static const unsigned pin236[] = { 236, };
  2238. static const unsigned pin237[] = { 237, };
  2239. static const unsigned pin238[] = { 238, };
  2240. static const unsigned pin239[] = { 239, };
  2241. static const unsigned pin240[] = { 240, };
  2242. static const unsigned pin241[] = { 241, };
  2243. static const unsigned pin242[] = { 242, };
  2244. static const unsigned pin243[] = { 243, };
  2245. static const unsigned pin244[] = { 244, };
  2246. static const unsigned pin245[] = { 245, };
  2247. static const unsigned pin_grp0[] = { 173, 174, };
  2248. static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };
  2249. static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,
  2250. 190, 191, 192, };
  2251. static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };
  2252. static const unsigned pin_grp4[] = { 199, 200, };
  2253. static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
  2254. 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
  2255. static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };
  2256. static const unsigned pin_grp7[] = { 98, 99, };
  2257. static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,
  2258. 166, 167, 168, 169, 170, 171, 172, };
  2259. /* Define muxreg arrays */
  2260. DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);
  2261. DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);
  2262. DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);
  2263. DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);
  2264. DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);
  2265. DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);
  2266. DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);
  2267. DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);
  2268. DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);
  2269. DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);
  2270. DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);
  2271. DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);
  2272. DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);
  2273. DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);
  2274. DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);
  2275. DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);
  2276. DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);
  2277. DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);
  2278. DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);
  2279. DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);
  2280. DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);
  2281. DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);
  2282. DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);
  2283. DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);
  2284. DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);
  2285. DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);
  2286. DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);
  2287. DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);
  2288. DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);
  2289. DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);
  2290. DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);
  2291. DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);
  2292. DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);
  2293. DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);
  2294. DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);
  2295. DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);
  2296. DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);
  2297. DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);
  2298. DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);
  2299. DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);
  2300. DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);
  2301. DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);
  2302. DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);
  2303. DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);
  2304. DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);
  2305. DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);
  2306. DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);
  2307. DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);
  2308. DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);
  2309. DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);
  2310. DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);
  2311. DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);
  2312. DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);
  2313. DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);
  2314. DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);
  2315. DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);
  2316. DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);
  2317. DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);
  2318. DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);
  2319. DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);
  2320. DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);
  2321. DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);
  2322. DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);
  2323. DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);
  2324. DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);
  2325. DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);
  2326. DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);
  2327. DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);
  2328. DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);
  2329. DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);
  2330. DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);
  2331. DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);
  2332. DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);
  2333. DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);
  2334. DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);
  2335. DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);
  2336. DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);
  2337. DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);
  2338. DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);
  2339. DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);
  2340. DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);
  2341. DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);
  2342. DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);
  2343. DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);
  2344. DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);
  2345. DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);
  2346. DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);
  2347. DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);
  2348. DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);
  2349. DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);
  2350. static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {
  2351. GPIO_PINGROUP(i2c0_pins),
  2352. GPIO_PINGROUP(ssp0_pins),
  2353. GPIO_PINGROUP(ssp0_cs0_pins),
  2354. GPIO_PINGROUP(ssp0_cs1_2_pins),
  2355. GPIO_PINGROUP(i2s0_pins),
  2356. GPIO_PINGROUP(i2s1_pins),
  2357. GPIO_PINGROUP(clcd_pins),
  2358. GPIO_PINGROUP(clcd_high_res_pins),
  2359. GPIO_PINGROUP(pin18),
  2360. GPIO_PINGROUP(pin19),
  2361. GPIO_PINGROUP(pin20),
  2362. GPIO_PINGROUP(pin21),
  2363. GPIO_PINGROUP(pin22),
  2364. GPIO_PINGROUP(pin23),
  2365. GPIO_PINGROUP(pin143),
  2366. GPIO_PINGROUP(pin144),
  2367. GPIO_PINGROUP(pin145),
  2368. GPIO_PINGROUP(pin146),
  2369. GPIO_PINGROUP(pin147),
  2370. GPIO_PINGROUP(pin148),
  2371. GPIO_PINGROUP(pin149),
  2372. GPIO_PINGROUP(pin150),
  2373. GPIO_PINGROUP(pin151),
  2374. GPIO_PINGROUP(pin152),
  2375. GPIO_PINGROUP(smi_2_chips_pins),
  2376. GPIO_PINGROUP(pin54),
  2377. GPIO_PINGROUP(pin55),
  2378. GPIO_PINGROUP(pin56),
  2379. GPIO_PINGROUP(pin57),
  2380. GPIO_PINGROUP(pin58),
  2381. GPIO_PINGROUP(pin59),
  2382. GPIO_PINGROUP(pin60),
  2383. GPIO_PINGROUP(pin61),
  2384. GPIO_PINGROUP(pin62),
  2385. GPIO_PINGROUP(pin63),
  2386. GPIO_PINGROUP(pin_grp0),
  2387. GPIO_PINGROUP(pin_grp1),
  2388. GPIO_PINGROUP(pin_grp2),
  2389. GPIO_PINGROUP(pin_grp3),
  2390. GPIO_PINGROUP(pin_grp4),
  2391. GPIO_PINGROUP(pin_grp5),
  2392. GPIO_PINGROUP(pin_grp6),
  2393. GPIO_PINGROUP(pin_grp7),
  2394. GPIO_PINGROUP(pin_grp8),
  2395. GPIO_PINGROUP(nand_16bit_pins),
  2396. GPIO_PINGROUP(pin205),
  2397. GPIO_PINGROUP(pin206),
  2398. GPIO_PINGROUP(pin211),
  2399. GPIO_PINGROUP(pin212),
  2400. GPIO_PINGROUP(pin213),
  2401. GPIO_PINGROUP(pin214),
  2402. GPIO_PINGROUP(pin215),
  2403. GPIO_PINGROUP(pin216),
  2404. GPIO_PINGROUP(pin217),
  2405. GPIO_PINGROUP(pin218),
  2406. GPIO_PINGROUP(pin219),
  2407. GPIO_PINGROUP(pin220),
  2408. GPIO_PINGROUP(pin221),
  2409. GPIO_PINGROUP(pin222),
  2410. GPIO_PINGROUP(pin223),
  2411. GPIO_PINGROUP(pin224),
  2412. GPIO_PINGROUP(pin225),
  2413. GPIO_PINGROUP(pin226),
  2414. GPIO_PINGROUP(pin227),
  2415. GPIO_PINGROUP(pin228),
  2416. GPIO_PINGROUP(pin229),
  2417. GPIO_PINGROUP(pin230),
  2418. GPIO_PINGROUP(pin231),
  2419. GPIO_PINGROUP(pin232),
  2420. GPIO_PINGROUP(pin233),
  2421. GPIO_PINGROUP(pin234),
  2422. GPIO_PINGROUP(pin235),
  2423. GPIO_PINGROUP(pin236),
  2424. GPIO_PINGROUP(pin237),
  2425. GPIO_PINGROUP(pin238),
  2426. GPIO_PINGROUP(pin239),
  2427. GPIO_PINGROUP(pin240),
  2428. GPIO_PINGROUP(pin241),
  2429. GPIO_PINGROUP(pin242),
  2430. GPIO_PINGROUP(pin243),
  2431. GPIO_PINGROUP(pin244),
  2432. GPIO_PINGROUP(pin245),
  2433. GPIO_PINGROUP(keyboard_rowcol6_8_pins),
  2434. GPIO_PINGROUP(uart0_pins),
  2435. GPIO_PINGROUP(uart0_modem_pins),
  2436. GPIO_PINGROUP(gpt0_tmr0_pins),
  2437. GPIO_PINGROUP(gpt0_tmr1_pins),
  2438. GPIO_PINGROUP(gpt1_tmr0_pins),
  2439. GPIO_PINGROUP(gpt1_tmr1_pins),
  2440. GPIO_PINGROUP(touch_xy_pins),
  2441. };
  2442. static struct spear_pinctrl_machdata spear1310_machdata = {
  2443. .pins = spear1310_pins,
  2444. .npins = ARRAY_SIZE(spear1310_pins),
  2445. .groups = spear1310_pingroups,
  2446. .ngroups = ARRAY_SIZE(spear1310_pingroups),
  2447. .functions = spear1310_functions,
  2448. .nfunctions = ARRAY_SIZE(spear1310_functions),
  2449. .gpio_pingroups = spear1310_gpio_pingroup,
  2450. .ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),
  2451. .modes_supported = false,
  2452. };
  2453. static const struct of_device_id spear1310_pinctrl_of_match[] = {
  2454. {
  2455. .compatible = "st,spear1310-pinmux",
  2456. },
  2457. {},
  2458. };
  2459. static int spear1310_pinctrl_probe(struct platform_device *pdev)
  2460. {
  2461. return spear_pinctrl_probe(pdev, &spear1310_machdata);
  2462. }
  2463. static struct platform_driver spear1310_pinctrl_driver = {
  2464. .driver = {
  2465. .name = DRIVER_NAME,
  2466. .of_match_table = spear1310_pinctrl_of_match,
  2467. },
  2468. .probe = spear1310_pinctrl_probe,
  2469. };
  2470. static int __init spear1310_pinctrl_init(void)
  2471. {
  2472. return platform_driver_register(&spear1310_pinctrl_driver);
  2473. }
  2474. arch_initcall(spear1310_pinctrl_init);