pinctrl-plgpio.c 18 KB

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  1. /*
  2. * SPEAr platform PLGPIO driver
  3. *
  4. * Copyright (C) 2012 ST Microelectronics
  5. * Viresh Kumar <viresh.kumar@linaro.org>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without any
  9. * warranty of any kind, whether express or implied.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/err.h>
  13. #include <linux/gpio/driver.h>
  14. #include <linux/io.h>
  15. #include <linux/init.h>
  16. #include <linux/of.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/pinctrl/consumer.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm.h>
  21. #include <linux/spinlock.h>
  22. #define MAX_GPIO_PER_REG 32
  23. #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
  24. #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
  25. * sizeof(int *))
  26. /*
  27. * plgpio pins in all machines are not one to one mapped, bitwise with registers
  28. * bits. These set of macros define register masks for which below functions
  29. * (pin_to_offset and offset_to_pin) are required to be called.
  30. */
  31. #define PTO_ENB_REG 0x001
  32. #define PTO_WDATA_REG 0x002
  33. #define PTO_DIR_REG 0x004
  34. #define PTO_IE_REG 0x008
  35. #define PTO_RDATA_REG 0x010
  36. #define PTO_MIS_REG 0x020
  37. struct plgpio_regs {
  38. u32 enb; /* enable register */
  39. u32 wdata; /* write data register */
  40. u32 dir; /* direction set register */
  41. u32 rdata; /* read data register */
  42. u32 ie; /* interrupt enable register */
  43. u32 mis; /* mask interrupt status register */
  44. u32 eit; /* edge interrupt type */
  45. };
  46. /*
  47. * struct plgpio: plgpio driver specific structure
  48. *
  49. * lock: lock for guarding gpio registers
  50. * base: base address of plgpio block
  51. * chip: gpio framework specific chip information structure
  52. * p2o: function ptr for pin to offset conversion. This is required only for
  53. * machines where mapping b/w pin and offset is not 1-to-1.
  54. * o2p: function ptr for offset to pin conversion. This is required only for
  55. * machines where mapping b/w pin and offset is not 1-to-1.
  56. * p2o_regs: mask of registers for which p2o and o2p are applicable
  57. * regs: register offsets
  58. * csave_regs: context save registers for standby/sleep/hibernate cases
  59. */
  60. struct plgpio {
  61. spinlock_t lock;
  62. void __iomem *base;
  63. struct clk *clk;
  64. struct gpio_chip chip;
  65. int (*p2o)(int pin); /* pin_to_offset */
  66. int (*o2p)(int offset); /* offset_to_pin */
  67. u32 p2o_regs;
  68. struct plgpio_regs regs;
  69. #ifdef CONFIG_PM_SLEEP
  70. struct plgpio_regs *csave_regs;
  71. #endif
  72. };
  73. /* register manipulation inline functions */
  74. static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
  75. {
  76. u32 offset = PIN_OFFSET(pin);
  77. void __iomem *reg_off = REG_OFFSET(base, reg, pin);
  78. u32 val = readl_relaxed(reg_off);
  79. return !!(val & (1 << offset));
  80. }
  81. static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
  82. {
  83. u32 offset = PIN_OFFSET(pin);
  84. void __iomem *reg_off = REG_OFFSET(base, reg, pin);
  85. u32 val = readl_relaxed(reg_off);
  86. writel_relaxed(val | (1 << offset), reg_off);
  87. }
  88. static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
  89. {
  90. u32 offset = PIN_OFFSET(pin);
  91. void __iomem *reg_off = REG_OFFSET(base, reg, pin);
  92. u32 val = readl_relaxed(reg_off);
  93. writel_relaxed(val & ~(1 << offset), reg_off);
  94. }
  95. /* gpio framework specific routines */
  96. static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
  97. {
  98. struct plgpio *plgpio = gpiochip_get_data(chip);
  99. unsigned long flags;
  100. /* get correct offset for "offset" pin */
  101. if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
  102. offset = plgpio->p2o(offset);
  103. if (offset == -1)
  104. return -EINVAL;
  105. }
  106. spin_lock_irqsave(&plgpio->lock, flags);
  107. plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
  108. spin_unlock_irqrestore(&plgpio->lock, flags);
  109. return 0;
  110. }
  111. static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
  112. int value)
  113. {
  114. struct plgpio *plgpio = gpiochip_get_data(chip);
  115. unsigned long flags;
  116. unsigned dir_offset = offset, wdata_offset = offset, tmp;
  117. /* get correct offset for "offset" pin */
  118. if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
  119. tmp = plgpio->p2o(offset);
  120. if (tmp == -1)
  121. return -EINVAL;
  122. if (plgpio->p2o_regs & PTO_DIR_REG)
  123. dir_offset = tmp;
  124. if (plgpio->p2o_regs & PTO_WDATA_REG)
  125. wdata_offset = tmp;
  126. }
  127. spin_lock_irqsave(&plgpio->lock, flags);
  128. if (value)
  129. plgpio_reg_set(plgpio->base, wdata_offset,
  130. plgpio->regs.wdata);
  131. else
  132. plgpio_reg_reset(plgpio->base, wdata_offset,
  133. plgpio->regs.wdata);
  134. plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
  135. spin_unlock_irqrestore(&plgpio->lock, flags);
  136. return 0;
  137. }
  138. static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
  139. {
  140. struct plgpio *plgpio = gpiochip_get_data(chip);
  141. if (offset >= chip->ngpio)
  142. return -EINVAL;
  143. /* get correct offset for "offset" pin */
  144. if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
  145. offset = plgpio->p2o(offset);
  146. if (offset == -1)
  147. return -EINVAL;
  148. }
  149. return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
  150. }
  151. static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
  152. {
  153. struct plgpio *plgpio = gpiochip_get_data(chip);
  154. if (offset >= chip->ngpio)
  155. return;
  156. /* get correct offset for "offset" pin */
  157. if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
  158. offset = plgpio->p2o(offset);
  159. if (offset == -1)
  160. return;
  161. }
  162. if (value)
  163. plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
  164. else
  165. plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
  166. }
  167. static int plgpio_request(struct gpio_chip *chip, unsigned offset)
  168. {
  169. struct plgpio *plgpio = gpiochip_get_data(chip);
  170. int gpio = chip->base + offset;
  171. unsigned long flags;
  172. int ret = 0;
  173. if (offset >= chip->ngpio)
  174. return -EINVAL;
  175. ret = pinctrl_gpio_request(gpio);
  176. if (ret)
  177. return ret;
  178. if (!IS_ERR(plgpio->clk)) {
  179. ret = clk_enable(plgpio->clk);
  180. if (ret)
  181. goto err0;
  182. }
  183. if (plgpio->regs.enb == -1)
  184. return 0;
  185. /*
  186. * put gpio in IN mode before enabling it. This make enabling gpio safe
  187. */
  188. ret = plgpio_direction_input(chip, offset);
  189. if (ret)
  190. goto err1;
  191. /* get correct offset for "offset" pin */
  192. if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
  193. offset = plgpio->p2o(offset);
  194. if (offset == -1) {
  195. ret = -EINVAL;
  196. goto err1;
  197. }
  198. }
  199. spin_lock_irqsave(&plgpio->lock, flags);
  200. plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
  201. spin_unlock_irqrestore(&plgpio->lock, flags);
  202. return 0;
  203. err1:
  204. if (!IS_ERR(plgpio->clk))
  205. clk_disable(plgpio->clk);
  206. err0:
  207. pinctrl_gpio_free(gpio);
  208. return ret;
  209. }
  210. static void plgpio_free(struct gpio_chip *chip, unsigned offset)
  211. {
  212. struct plgpio *plgpio = gpiochip_get_data(chip);
  213. int gpio = chip->base + offset;
  214. unsigned long flags;
  215. if (offset >= chip->ngpio)
  216. return;
  217. if (plgpio->regs.enb == -1)
  218. goto disable_clk;
  219. /* get correct offset for "offset" pin */
  220. if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
  221. offset = plgpio->p2o(offset);
  222. if (offset == -1)
  223. return;
  224. }
  225. spin_lock_irqsave(&plgpio->lock, flags);
  226. plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
  227. spin_unlock_irqrestore(&plgpio->lock, flags);
  228. disable_clk:
  229. if (!IS_ERR(plgpio->clk))
  230. clk_disable(plgpio->clk);
  231. pinctrl_gpio_free(gpio);
  232. }
  233. /* PLGPIO IRQ */
  234. static void plgpio_irq_disable(struct irq_data *d)
  235. {
  236. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  237. struct plgpio *plgpio = gpiochip_get_data(gc);
  238. int offset = d->hwirq;
  239. unsigned long flags;
  240. /* get correct offset for "offset" pin */
  241. if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
  242. offset = plgpio->p2o(offset);
  243. if (offset == -1)
  244. return;
  245. }
  246. spin_lock_irqsave(&plgpio->lock, flags);
  247. plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
  248. spin_unlock_irqrestore(&plgpio->lock, flags);
  249. }
  250. static void plgpio_irq_enable(struct irq_data *d)
  251. {
  252. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  253. struct plgpio *plgpio = gpiochip_get_data(gc);
  254. int offset = d->hwirq;
  255. unsigned long flags;
  256. /* get correct offset for "offset" pin */
  257. if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
  258. offset = plgpio->p2o(offset);
  259. if (offset == -1)
  260. return;
  261. }
  262. spin_lock_irqsave(&plgpio->lock, flags);
  263. plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
  264. spin_unlock_irqrestore(&plgpio->lock, flags);
  265. }
  266. static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
  267. {
  268. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  269. struct plgpio *plgpio = gpiochip_get_data(gc);
  270. int offset = d->hwirq;
  271. void __iomem *reg_off;
  272. unsigned int supported_type = 0, val;
  273. if (offset >= plgpio->chip.ngpio)
  274. return -EINVAL;
  275. if (plgpio->regs.eit == -1)
  276. supported_type = IRQ_TYPE_LEVEL_HIGH;
  277. else
  278. supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
  279. if (!(trigger & supported_type))
  280. return -EINVAL;
  281. if (plgpio->regs.eit == -1)
  282. return 0;
  283. reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
  284. val = readl_relaxed(reg_off);
  285. offset = PIN_OFFSET(offset);
  286. if (trigger & IRQ_TYPE_EDGE_RISING)
  287. writel_relaxed(val | (1 << offset), reg_off);
  288. else
  289. writel_relaxed(val & ~(1 << offset), reg_off);
  290. return 0;
  291. }
  292. static struct irq_chip plgpio_irqchip = {
  293. .name = "PLGPIO",
  294. .irq_enable = plgpio_irq_enable,
  295. .irq_disable = plgpio_irq_disable,
  296. .irq_set_type = plgpio_irq_set_type,
  297. };
  298. static void plgpio_irq_handler(struct irq_desc *desc)
  299. {
  300. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  301. struct plgpio *plgpio = gpiochip_get_data(gc);
  302. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  303. int regs_count, count, pin, offset, i = 0;
  304. unsigned long pending;
  305. count = plgpio->chip.ngpio;
  306. regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
  307. chained_irq_enter(irqchip, desc);
  308. /* check all plgpio MIS registers for a possible interrupt */
  309. for (; i < regs_count; i++) {
  310. pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
  311. i * sizeof(int *));
  312. if (!pending)
  313. continue;
  314. /* clear interrupts */
  315. writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
  316. i * sizeof(int *));
  317. /*
  318. * clear extra bits in last register having gpios < MAX/REG
  319. * ex: Suppose there are max 102 plgpios. then last register
  320. * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
  321. * so, we must not take other 28 bits into consideration for
  322. * checking interrupt. so clear those bits.
  323. */
  324. count = count - i * MAX_GPIO_PER_REG;
  325. if (count < MAX_GPIO_PER_REG)
  326. pending &= (1 << count) - 1;
  327. for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
  328. /* get correct pin for "offset" */
  329. if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
  330. pin = plgpio->o2p(offset);
  331. if (pin == -1)
  332. continue;
  333. } else
  334. pin = offset;
  335. /* get correct irq line number */
  336. pin = i * MAX_GPIO_PER_REG + pin;
  337. generic_handle_irq(
  338. irq_find_mapping(gc->irq.domain, pin));
  339. }
  340. }
  341. chained_irq_exit(irqchip, desc);
  342. }
  343. /*
  344. * pin to offset and offset to pin converter functions
  345. *
  346. * In spear310 there is inconsistency among bit positions in plgpio regiseters,
  347. * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
  348. * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
  349. */
  350. static int spear310_p2o(int pin)
  351. {
  352. int offset = pin;
  353. if (pin <= 27)
  354. offset += 4;
  355. else if (pin <= 33)
  356. offset = -1;
  357. else if (pin <= 97)
  358. offset -= 2;
  359. else if (pin <= 101)
  360. offset = 101 - pin;
  361. else
  362. offset = -1;
  363. return offset;
  364. }
  365. static int spear310_o2p(int offset)
  366. {
  367. if (offset <= 3)
  368. return 101 - offset;
  369. else if (offset <= 31)
  370. return offset - 4;
  371. else
  372. return offset + 2;
  373. }
  374. static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio)
  375. {
  376. struct device_node *np = pdev->dev.of_node;
  377. int ret = -EINVAL;
  378. u32 val;
  379. if (of_machine_is_compatible("st,spear310")) {
  380. plgpio->p2o = spear310_p2o;
  381. plgpio->o2p = spear310_o2p;
  382. plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
  383. PTO_RDATA_REG | PTO_MIS_REG;
  384. }
  385. if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
  386. plgpio->chip.ngpio = val;
  387. } else {
  388. dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
  389. goto end;
  390. }
  391. if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
  392. plgpio->regs.enb = val;
  393. else
  394. plgpio->regs.enb = -1;
  395. if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
  396. plgpio->regs.wdata = val;
  397. } else {
  398. dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
  399. goto end;
  400. }
  401. if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
  402. plgpio->regs.dir = val;
  403. } else {
  404. dev_err(&pdev->dev, "DT: Invalid dir reg\n");
  405. goto end;
  406. }
  407. if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
  408. plgpio->regs.ie = val;
  409. } else {
  410. dev_err(&pdev->dev, "DT: Invalid ie reg\n");
  411. goto end;
  412. }
  413. if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
  414. plgpio->regs.rdata = val;
  415. } else {
  416. dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
  417. goto end;
  418. }
  419. if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
  420. plgpio->regs.mis = val;
  421. } else {
  422. dev_err(&pdev->dev, "DT: Invalid mis reg\n");
  423. goto end;
  424. }
  425. if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
  426. plgpio->regs.eit = val;
  427. else
  428. plgpio->regs.eit = -1;
  429. return 0;
  430. end:
  431. return ret;
  432. }
  433. static int plgpio_probe(struct platform_device *pdev)
  434. {
  435. struct plgpio *plgpio;
  436. int ret, irq;
  437. plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
  438. if (!plgpio)
  439. return -ENOMEM;
  440. plgpio->base = devm_platform_ioremap_resource(pdev, 0);
  441. if (IS_ERR(plgpio->base))
  442. return PTR_ERR(plgpio->base);
  443. ret = plgpio_probe_dt(pdev, plgpio);
  444. if (ret) {
  445. dev_err(&pdev->dev, "DT probe failed\n");
  446. return ret;
  447. }
  448. plgpio->clk = devm_clk_get(&pdev->dev, NULL);
  449. if (IS_ERR(plgpio->clk))
  450. dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
  451. #ifdef CONFIG_PM_SLEEP
  452. plgpio->csave_regs = devm_kcalloc(&pdev->dev,
  453. DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
  454. sizeof(*plgpio->csave_regs),
  455. GFP_KERNEL);
  456. if (!plgpio->csave_regs)
  457. return -ENOMEM;
  458. #endif
  459. platform_set_drvdata(pdev, plgpio);
  460. spin_lock_init(&plgpio->lock);
  461. plgpio->chip.base = -1;
  462. plgpio->chip.request = plgpio_request;
  463. plgpio->chip.free = plgpio_free;
  464. plgpio->chip.direction_input = plgpio_direction_input;
  465. plgpio->chip.direction_output = plgpio_direction_output;
  466. plgpio->chip.get = plgpio_get_value;
  467. plgpio->chip.set = plgpio_set_value;
  468. plgpio->chip.label = dev_name(&pdev->dev);
  469. plgpio->chip.parent = &pdev->dev;
  470. plgpio->chip.owner = THIS_MODULE;
  471. plgpio->chip.of_node = pdev->dev.of_node;
  472. if (!IS_ERR(plgpio->clk)) {
  473. ret = clk_prepare(plgpio->clk);
  474. if (ret) {
  475. dev_err(&pdev->dev, "clk prepare failed\n");
  476. return ret;
  477. }
  478. }
  479. irq = platform_get_irq(pdev, 0);
  480. if (irq > 0) {
  481. struct gpio_irq_chip *girq;
  482. girq = &plgpio->chip.irq;
  483. girq->chip = &plgpio_irqchip;
  484. girq->parent_handler = plgpio_irq_handler;
  485. girq->num_parents = 1;
  486. girq->parents = devm_kcalloc(&pdev->dev, 1,
  487. sizeof(*girq->parents),
  488. GFP_KERNEL);
  489. if (!girq->parents)
  490. return -ENOMEM;
  491. girq->parents[0] = irq;
  492. girq->default_type = IRQ_TYPE_NONE;
  493. girq->handler = handle_simple_irq;
  494. dev_info(&pdev->dev, "PLGPIO registering with IRQs\n");
  495. } else {
  496. dev_info(&pdev->dev, "PLGPIO registering without IRQs\n");
  497. }
  498. ret = gpiochip_add_data(&plgpio->chip, plgpio);
  499. if (ret) {
  500. dev_err(&pdev->dev, "unable to add gpio chip\n");
  501. goto unprepare_clk;
  502. }
  503. return 0;
  504. unprepare_clk:
  505. if (!IS_ERR(plgpio->clk))
  506. clk_unprepare(plgpio->clk);
  507. return ret;
  508. }
  509. #ifdef CONFIG_PM_SLEEP
  510. static int plgpio_suspend(struct device *dev)
  511. {
  512. struct plgpio *plgpio = dev_get_drvdata(dev);
  513. int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
  514. void __iomem *off;
  515. for (i = 0; i < reg_count; i++) {
  516. off = plgpio->base + i * sizeof(int *);
  517. if (plgpio->regs.enb != -1)
  518. plgpio->csave_regs[i].enb =
  519. readl_relaxed(plgpio->regs.enb + off);
  520. if (plgpio->regs.eit != -1)
  521. plgpio->csave_regs[i].eit =
  522. readl_relaxed(plgpio->regs.eit + off);
  523. plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
  524. off);
  525. plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
  526. off);
  527. plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
  528. }
  529. return 0;
  530. }
  531. /*
  532. * This is used to correct the values in end registers. End registers contain
  533. * extra bits that might be used for other purpose in platform. So, we shouldn't
  534. * overwrite these bits. This macro, reads given register again, preserves other
  535. * bit values (non-plgpio bits), and retain captured value (plgpio bits).
  536. */
  537. #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
  538. { \
  539. _tmp = readl_relaxed(plgpio->regs.__reg + _off); \
  540. _tmp &= ~_mask; \
  541. plgpio->csave_regs[i].__reg = \
  542. _tmp | (plgpio->csave_regs[i].__reg & _mask); \
  543. }
  544. static int plgpio_resume(struct device *dev)
  545. {
  546. struct plgpio *plgpio = dev_get_drvdata(dev);
  547. int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
  548. void __iomem *off;
  549. u32 mask, tmp;
  550. for (i = 0; i < reg_count; i++) {
  551. off = plgpio->base + i * sizeof(int *);
  552. if (i == reg_count - 1) {
  553. mask = (1 << (plgpio->chip.ngpio - i *
  554. MAX_GPIO_PER_REG)) - 1;
  555. if (plgpio->regs.enb != -1)
  556. plgpio_prepare_reg(enb, off, mask, tmp);
  557. if (plgpio->regs.eit != -1)
  558. plgpio_prepare_reg(eit, off, mask, tmp);
  559. plgpio_prepare_reg(wdata, off, mask, tmp);
  560. plgpio_prepare_reg(dir, off, mask, tmp);
  561. plgpio_prepare_reg(ie, off, mask, tmp);
  562. }
  563. writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
  564. off);
  565. writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
  566. off);
  567. if (plgpio->regs.eit != -1)
  568. writel_relaxed(plgpio->csave_regs[i].eit,
  569. plgpio->regs.eit + off);
  570. writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
  571. if (plgpio->regs.enb != -1)
  572. writel_relaxed(plgpio->csave_regs[i].enb,
  573. plgpio->regs.enb + off);
  574. }
  575. return 0;
  576. }
  577. #endif
  578. static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
  579. static const struct of_device_id plgpio_of_match[] = {
  580. { .compatible = "st,spear-plgpio" },
  581. {}
  582. };
  583. static struct platform_driver plgpio_driver = {
  584. .probe = plgpio_probe,
  585. .driver = {
  586. .name = "spear-plgpio",
  587. .pm = &plgpio_dev_pm_ops,
  588. .of_match_table = plgpio_of_match,
  589. },
  590. };
  591. static int __init plgpio_init(void)
  592. {
  593. return platform_driver_register(&plgpio_driver);
  594. }
  595. subsys_initcall(plgpio_init);