pinctrl-pxa2xx.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Marvell PXA2xx family pin control
  4. *
  5. * Copyright (C) 2015 Robert Jarzmik
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/io.h>
  9. #include <linux/of.h>
  10. #include <linux/of_address.h>
  11. #include <linux/module.h>
  12. #include <linux/pinctrl/machine.h>
  13. #include <linux/pinctrl/pinconf.h>
  14. #include <linux/pinctrl/pinconf-generic.h>
  15. #include <linux/pinctrl/pinmux.h>
  16. #include <linux/pinctrl/pinctrl.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/slab.h>
  19. #include "../pinctrl-utils.h"
  20. #include "pinctrl-pxa2xx.h"
  21. static int pxa2xx_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
  22. {
  23. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  24. return pctl->ngroups;
  25. }
  26. static const char *pxa2xx_pctrl_get_group_name(struct pinctrl_dev *pctldev,
  27. unsigned tgroup)
  28. {
  29. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  30. struct pxa_pinctrl_group *group = pctl->groups + tgroup;
  31. return group->name;
  32. }
  33. static int pxa2xx_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
  34. unsigned tgroup,
  35. const unsigned **pins,
  36. unsigned *num_pins)
  37. {
  38. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  39. struct pxa_pinctrl_group *group = pctl->groups + tgroup;
  40. *pins = (unsigned *)&group->pin;
  41. *num_pins = 1;
  42. return 0;
  43. }
  44. static const struct pinctrl_ops pxa2xx_pctl_ops = {
  45. #ifdef CONFIG_OF
  46. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  47. .dt_free_map = pinctrl_utils_free_map,
  48. #endif
  49. .get_groups_count = pxa2xx_pctrl_get_groups_count,
  50. .get_group_name = pxa2xx_pctrl_get_group_name,
  51. .get_group_pins = pxa2xx_pctrl_get_group_pins,
  52. };
  53. static struct pxa_desc_function *
  54. pxa_desc_by_func_group(struct pxa_pinctrl *pctl, const char *pin_name,
  55. const char *func_name)
  56. {
  57. int i;
  58. struct pxa_desc_function *df;
  59. for (i = 0; i < pctl->npins; i++) {
  60. const struct pxa_desc_pin *pin = pctl->ppins + i;
  61. if (!strcmp(pin->pin.name, pin_name))
  62. for (df = pin->functions; df->name; df++)
  63. if (!strcmp(df->name, func_name))
  64. return df;
  65. }
  66. return NULL;
  67. }
  68. static int pxa2xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  69. struct pinctrl_gpio_range *range,
  70. unsigned pin,
  71. bool input)
  72. {
  73. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  74. unsigned long flags;
  75. uint32_t val;
  76. void __iomem *gpdr;
  77. gpdr = pctl->base_gpdr[pin / 32];
  78. dev_dbg(pctl->dev, "set_direction(pin=%d): dir=%d\n",
  79. pin, !input);
  80. spin_lock_irqsave(&pctl->lock, flags);
  81. val = readl_relaxed(gpdr);
  82. val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32));
  83. writel_relaxed(val, gpdr);
  84. spin_unlock_irqrestore(&pctl->lock, flags);
  85. return 0;
  86. }
  87. static const char *pxa2xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
  88. unsigned function)
  89. {
  90. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  91. struct pxa_pinctrl_function *pf = pctl->functions + function;
  92. return pf->name;
  93. }
  94. static int pxa2xx_get_functions_count(struct pinctrl_dev *pctldev)
  95. {
  96. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  97. return pctl->nfuncs;
  98. }
  99. static int pxa2xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
  100. unsigned function,
  101. const char * const **groups,
  102. unsigned * const num_groups)
  103. {
  104. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  105. struct pxa_pinctrl_function *pf = pctl->functions + function;
  106. *groups = pf->groups;
  107. *num_groups = pf->ngroups;
  108. return 0;
  109. }
  110. static int pxa2xx_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned function,
  111. unsigned tgroup)
  112. {
  113. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  114. struct pxa_pinctrl_group *group = pctl->groups + tgroup;
  115. struct pxa_desc_function *df;
  116. int pin, shift;
  117. unsigned long flags;
  118. void __iomem *gafr, *gpdr;
  119. u32 val;
  120. df = pxa_desc_by_func_group(pctl, group->name,
  121. (pctl->functions + function)->name);
  122. if (!df)
  123. return -EINVAL;
  124. pin = group->pin;
  125. gafr = pctl->base_gafr[pin / 16];
  126. gpdr = pctl->base_gpdr[pin / 32];
  127. shift = (pin % 16) << 1;
  128. dev_dbg(pctl->dev, "set_mux(pin=%d): af=%d dir=%d\n",
  129. pin, df->muxval >> 1, df->muxval & 0x1);
  130. spin_lock_irqsave(&pctl->lock, flags);
  131. val = readl_relaxed(gafr);
  132. val = (val & ~(0x3 << shift)) | ((df->muxval >> 1) << shift);
  133. writel_relaxed(val, gafr);
  134. val = readl_relaxed(gpdr);
  135. val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0);
  136. writel_relaxed(val, gpdr);
  137. spin_unlock_irqrestore(&pctl->lock, flags);
  138. return 0;
  139. }
  140. static const struct pinmux_ops pxa2xx_pinmux_ops = {
  141. .get_functions_count = pxa2xx_get_functions_count,
  142. .get_function_name = pxa2xx_pmx_get_func_name,
  143. .get_function_groups = pxa2xx_pmx_get_func_groups,
  144. .set_mux = pxa2xx_pmx_set_mux,
  145. .gpio_set_direction = pxa2xx_pmx_gpio_set_direction,
  146. };
  147. static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev,
  148. unsigned group,
  149. unsigned long *config)
  150. {
  151. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  152. struct pxa_pinctrl_group *g = pctl->groups + group;
  153. unsigned long flags;
  154. unsigned pin = g->pin;
  155. void __iomem *pgsr = pctl->base_pgsr[pin / 32];
  156. u32 val;
  157. spin_lock_irqsave(&pctl->lock, flags);
  158. val = readl_relaxed(pgsr) & BIT(pin % 32);
  159. *config = val ? PIN_CONFIG_LOW_POWER_MODE : 0;
  160. spin_unlock_irqrestore(&pctl->lock, flags);
  161. dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n",
  162. pin, !!val);
  163. return 0;
  164. }
  165. static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev,
  166. unsigned group,
  167. unsigned long *configs,
  168. unsigned num_configs)
  169. {
  170. struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  171. struct pxa_pinctrl_group *g = pctl->groups + group;
  172. unsigned long flags;
  173. unsigned pin = g->pin;
  174. void __iomem *pgsr = pctl->base_pgsr[pin / 32];
  175. int i, is_set = 0;
  176. u32 val;
  177. for (i = 0; i < num_configs; i++) {
  178. switch (pinconf_to_config_param(configs[i])) {
  179. case PIN_CONFIG_LOW_POWER_MODE:
  180. is_set = pinconf_to_config_argument(configs[i]);
  181. break;
  182. default:
  183. return -EINVAL;
  184. }
  185. }
  186. dev_dbg(pctl->dev, "set sleep gpio state(pin=%d) %d\n",
  187. pin, is_set);
  188. spin_lock_irqsave(&pctl->lock, flags);
  189. val = readl_relaxed(pgsr);
  190. val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0);
  191. writel_relaxed(val, pgsr);
  192. spin_unlock_irqrestore(&pctl->lock, flags);
  193. return 0;
  194. }
  195. static const struct pinconf_ops pxa2xx_pconf_ops = {
  196. .pin_config_group_get = pxa2xx_pconf_group_get,
  197. .pin_config_group_set = pxa2xx_pconf_group_set,
  198. .is_generic = true,
  199. };
  200. static struct pinctrl_desc pxa2xx_pinctrl_desc = {
  201. .confops = &pxa2xx_pconf_ops,
  202. .pctlops = &pxa2xx_pctl_ops,
  203. .pmxops = &pxa2xx_pinmux_ops,
  204. };
  205. static const struct pxa_pinctrl_function *
  206. pxa2xx_find_function(struct pxa_pinctrl *pctl, const char *fname,
  207. const struct pxa_pinctrl_function *functions)
  208. {
  209. const struct pxa_pinctrl_function *func;
  210. for (func = functions; func->name; func++)
  211. if (!strcmp(fname, func->name))
  212. return func;
  213. return NULL;
  214. }
  215. static int pxa2xx_build_functions(struct pxa_pinctrl *pctl)
  216. {
  217. int i;
  218. struct pxa_pinctrl_function *functions;
  219. struct pxa_desc_function *df;
  220. /*
  221. * Each pin can have at most 6 alternate functions, and 2 gpio functions
  222. * which are common to each pin. As there are more than 2 pins without
  223. * alternate function, 6 * npins is an absolute high limit of the number
  224. * of functions.
  225. */
  226. functions = devm_kcalloc(pctl->dev, pctl->npins * 6,
  227. sizeof(*functions), GFP_KERNEL);
  228. if (!functions)
  229. return -ENOMEM;
  230. for (i = 0; i < pctl->npins; i++)
  231. for (df = pctl->ppins[i].functions; df->name; df++)
  232. if (!pxa2xx_find_function(pctl, df->name, functions))
  233. (functions + pctl->nfuncs++)->name = df->name;
  234. pctl->functions = devm_kmemdup(pctl->dev, functions,
  235. pctl->nfuncs * sizeof(*functions),
  236. GFP_KERNEL);
  237. if (!pctl->functions)
  238. return -ENOMEM;
  239. devm_kfree(pctl->dev, functions);
  240. return 0;
  241. }
  242. static int pxa2xx_build_groups(struct pxa_pinctrl *pctl)
  243. {
  244. int i, j, ngroups;
  245. struct pxa_pinctrl_function *func;
  246. struct pxa_desc_function *df;
  247. char **gtmp;
  248. gtmp = devm_kmalloc_array(pctl->dev, pctl->npins, sizeof(*gtmp),
  249. GFP_KERNEL);
  250. if (!gtmp)
  251. return -ENOMEM;
  252. for (i = 0; i < pctl->nfuncs; i++) {
  253. ngroups = 0;
  254. for (j = 0; j < pctl->npins; j++)
  255. for (df = pctl->ppins[j].functions; df->name;
  256. df++)
  257. if (!strcmp(pctl->functions[i].name,
  258. df->name))
  259. gtmp[ngroups++] = (char *)
  260. pctl->ppins[j].pin.name;
  261. func = pctl->functions + i;
  262. func->ngroups = ngroups;
  263. func->groups =
  264. devm_kmalloc_array(pctl->dev, ngroups,
  265. sizeof(char *), GFP_KERNEL);
  266. if (!func->groups)
  267. return -ENOMEM;
  268. memcpy(func->groups, gtmp, ngroups * sizeof(*gtmp));
  269. }
  270. devm_kfree(pctl->dev, gtmp);
  271. return 0;
  272. }
  273. static int pxa2xx_build_state(struct pxa_pinctrl *pctl,
  274. const struct pxa_desc_pin *ppins, int npins)
  275. {
  276. struct pxa_pinctrl_group *group;
  277. struct pinctrl_pin_desc *pins;
  278. int ret, i;
  279. pctl->npins = npins;
  280. pctl->ppins = ppins;
  281. pctl->ngroups = npins;
  282. pctl->desc.npins = npins;
  283. pins = devm_kcalloc(pctl->dev, npins, sizeof(*pins), GFP_KERNEL);
  284. if (!pins)
  285. return -ENOMEM;
  286. pctl->desc.pins = pins;
  287. for (i = 0; i < npins; i++)
  288. pins[i] = ppins[i].pin;
  289. pctl->groups = devm_kmalloc_array(pctl->dev, pctl->ngroups,
  290. sizeof(*pctl->groups), GFP_KERNEL);
  291. if (!pctl->groups)
  292. return -ENOMEM;
  293. for (i = 0; i < npins; i++) {
  294. group = pctl->groups + i;
  295. group->name = ppins[i].pin.name;
  296. group->pin = ppins[i].pin.number;
  297. }
  298. ret = pxa2xx_build_functions(pctl);
  299. if (ret)
  300. return ret;
  301. ret = pxa2xx_build_groups(pctl);
  302. if (ret)
  303. return ret;
  304. return 0;
  305. }
  306. int pxa2xx_pinctrl_init(struct platform_device *pdev,
  307. const struct pxa_desc_pin *ppins, int npins,
  308. void __iomem *base_gafr[], void __iomem *base_gpdr[],
  309. void __iomem *base_pgsr[])
  310. {
  311. struct pxa_pinctrl *pctl;
  312. int ret, i, maxpin = 0;
  313. for (i = 0; i < npins; i++)
  314. maxpin = max_t(int, ppins[i].pin.number, maxpin);
  315. pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
  316. if (!pctl)
  317. return -ENOMEM;
  318. pctl->base_gafr = devm_kcalloc(&pdev->dev, roundup(maxpin, 16),
  319. sizeof(*pctl->base_gafr), GFP_KERNEL);
  320. pctl->base_gpdr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
  321. sizeof(*pctl->base_gpdr), GFP_KERNEL);
  322. pctl->base_pgsr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
  323. sizeof(*pctl->base_pgsr), GFP_KERNEL);
  324. if (!pctl->base_gafr || !pctl->base_gpdr || !pctl->base_pgsr)
  325. return -ENOMEM;
  326. platform_set_drvdata(pdev, pctl);
  327. spin_lock_init(&pctl->lock);
  328. pctl->dev = &pdev->dev;
  329. pctl->desc = pxa2xx_pinctrl_desc;
  330. pctl->desc.name = dev_name(&pdev->dev);
  331. pctl->desc.owner = THIS_MODULE;
  332. for (i = 0; i < roundup(maxpin, 16); i += 16)
  333. pctl->base_gafr[i / 16] = base_gafr[i / 16];
  334. for (i = 0; i < roundup(maxpin, 32); i += 32) {
  335. pctl->base_gpdr[i / 32] = base_gpdr[i / 32];
  336. pctl->base_pgsr[i / 32] = base_pgsr[i / 32];
  337. }
  338. ret = pxa2xx_build_state(pctl, ppins, npins);
  339. if (ret)
  340. return ret;
  341. pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->desc, pctl);
  342. if (IS_ERR(pctl->pctl_dev)) {
  343. dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
  344. return PTR_ERR(pctl->pctl_dev);
  345. }
  346. dev_info(&pdev->dev, "initialized pxa2xx pinctrl driver\n");
  347. return 0;
  348. }
  349. EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init);
  350. MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
  351. MODULE_DESCRIPTION("Marvell PXA2xx pinctrl driver");
  352. MODULE_LICENSE("GPL v2");