pinctrl-zynq.c 42 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Zynq pin controller
  4. *
  5. * Copyright (C) 2014 Xilinx
  6. *
  7. * Sören Brinkmann <soren.brinkmann@xilinx.com>
  8. */
  9. #include <linux/io.h>
  10. #include <linux/mfd/syscon.h>
  11. #include <linux/init.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pinctrl/pinctrl.h>
  15. #include <linux/pinctrl/pinmux.h>
  16. #include <linux/pinctrl/pinconf.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include <linux/regmap.h>
  19. #include "pinctrl-utils.h"
  20. #include "core.h"
  21. #define ZYNQ_NUM_MIOS 54
  22. #define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
  23. #define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
  24. #define ZYNQ_PINMUX_MUX_SHIFT 1
  25. #define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
  26. /**
  27. * struct zynq_pinctrl - driver data
  28. * @pctrl: Pinctrl device
  29. * @syscon: Syscon regmap
  30. * @pctrl_offset: Offset for pinctrl into the @syscon space
  31. * @groups: Pingroups
  32. * @ngroups: Number of @groups
  33. * @funcs: Pinmux functions
  34. * @nfuncs: Number of @funcs
  35. */
  36. struct zynq_pinctrl {
  37. struct pinctrl_dev *pctrl;
  38. struct regmap *syscon;
  39. u32 pctrl_offset;
  40. const struct zynq_pctrl_group *groups;
  41. unsigned int ngroups;
  42. const struct zynq_pinmux_function *funcs;
  43. unsigned int nfuncs;
  44. };
  45. struct zynq_pctrl_group {
  46. const char *name;
  47. const unsigned int *pins;
  48. const unsigned int npins;
  49. };
  50. /**
  51. * struct zynq_pinmux_function - a pinmux function
  52. * @name: Name of the pinmux function.
  53. * @groups: List of pingroups for this function.
  54. * @ngroups: Number of entries in @groups.
  55. * @mux_val: Selector for this function
  56. * @mux: Offset of function specific mux
  57. * @mux_mask: Mask for function specific selector
  58. * @mux_shift: Shift for function specific selector
  59. */
  60. struct zynq_pinmux_function {
  61. const char *name;
  62. const char * const *groups;
  63. unsigned int ngroups;
  64. unsigned int mux_val;
  65. u32 mux;
  66. u32 mux_mask;
  67. u8 mux_shift;
  68. };
  69. enum zynq_pinmux_functions {
  70. ZYNQ_PMUX_can0,
  71. ZYNQ_PMUX_can1,
  72. ZYNQ_PMUX_ethernet0,
  73. ZYNQ_PMUX_ethernet1,
  74. ZYNQ_PMUX_gpio0,
  75. ZYNQ_PMUX_i2c0,
  76. ZYNQ_PMUX_i2c1,
  77. ZYNQ_PMUX_mdio0,
  78. ZYNQ_PMUX_mdio1,
  79. ZYNQ_PMUX_qspi0,
  80. ZYNQ_PMUX_qspi1,
  81. ZYNQ_PMUX_qspi_fbclk,
  82. ZYNQ_PMUX_qspi_cs1,
  83. ZYNQ_PMUX_spi0,
  84. ZYNQ_PMUX_spi1,
  85. ZYNQ_PMUX_spi0_ss,
  86. ZYNQ_PMUX_spi1_ss,
  87. ZYNQ_PMUX_sdio0,
  88. ZYNQ_PMUX_sdio0_pc,
  89. ZYNQ_PMUX_sdio0_cd,
  90. ZYNQ_PMUX_sdio0_wp,
  91. ZYNQ_PMUX_sdio1,
  92. ZYNQ_PMUX_sdio1_pc,
  93. ZYNQ_PMUX_sdio1_cd,
  94. ZYNQ_PMUX_sdio1_wp,
  95. ZYNQ_PMUX_smc0_nor,
  96. ZYNQ_PMUX_smc0_nor_cs1,
  97. ZYNQ_PMUX_smc0_nor_addr25,
  98. ZYNQ_PMUX_smc0_nand,
  99. ZYNQ_PMUX_ttc0,
  100. ZYNQ_PMUX_ttc1,
  101. ZYNQ_PMUX_uart0,
  102. ZYNQ_PMUX_uart1,
  103. ZYNQ_PMUX_usb0,
  104. ZYNQ_PMUX_usb1,
  105. ZYNQ_PMUX_swdt0,
  106. ZYNQ_PMUX_MAX_FUNC
  107. };
  108. static const struct pinctrl_pin_desc zynq_pins[] = {
  109. PINCTRL_PIN(0, "MIO0"),
  110. PINCTRL_PIN(1, "MIO1"),
  111. PINCTRL_PIN(2, "MIO2"),
  112. PINCTRL_PIN(3, "MIO3"),
  113. PINCTRL_PIN(4, "MIO4"),
  114. PINCTRL_PIN(5, "MIO5"),
  115. PINCTRL_PIN(6, "MIO6"),
  116. PINCTRL_PIN(7, "MIO7"),
  117. PINCTRL_PIN(8, "MIO8"),
  118. PINCTRL_PIN(9, "MIO9"),
  119. PINCTRL_PIN(10, "MIO10"),
  120. PINCTRL_PIN(11, "MIO11"),
  121. PINCTRL_PIN(12, "MIO12"),
  122. PINCTRL_PIN(13, "MIO13"),
  123. PINCTRL_PIN(14, "MIO14"),
  124. PINCTRL_PIN(15, "MIO15"),
  125. PINCTRL_PIN(16, "MIO16"),
  126. PINCTRL_PIN(17, "MIO17"),
  127. PINCTRL_PIN(18, "MIO18"),
  128. PINCTRL_PIN(19, "MIO19"),
  129. PINCTRL_PIN(20, "MIO20"),
  130. PINCTRL_PIN(21, "MIO21"),
  131. PINCTRL_PIN(22, "MIO22"),
  132. PINCTRL_PIN(23, "MIO23"),
  133. PINCTRL_PIN(24, "MIO24"),
  134. PINCTRL_PIN(25, "MIO25"),
  135. PINCTRL_PIN(26, "MIO26"),
  136. PINCTRL_PIN(27, "MIO27"),
  137. PINCTRL_PIN(28, "MIO28"),
  138. PINCTRL_PIN(29, "MIO29"),
  139. PINCTRL_PIN(30, "MIO30"),
  140. PINCTRL_PIN(31, "MIO31"),
  141. PINCTRL_PIN(32, "MIO32"),
  142. PINCTRL_PIN(33, "MIO33"),
  143. PINCTRL_PIN(34, "MIO34"),
  144. PINCTRL_PIN(35, "MIO35"),
  145. PINCTRL_PIN(36, "MIO36"),
  146. PINCTRL_PIN(37, "MIO37"),
  147. PINCTRL_PIN(38, "MIO38"),
  148. PINCTRL_PIN(39, "MIO39"),
  149. PINCTRL_PIN(40, "MIO40"),
  150. PINCTRL_PIN(41, "MIO41"),
  151. PINCTRL_PIN(42, "MIO42"),
  152. PINCTRL_PIN(43, "MIO43"),
  153. PINCTRL_PIN(44, "MIO44"),
  154. PINCTRL_PIN(45, "MIO45"),
  155. PINCTRL_PIN(46, "MIO46"),
  156. PINCTRL_PIN(47, "MIO47"),
  157. PINCTRL_PIN(48, "MIO48"),
  158. PINCTRL_PIN(49, "MIO49"),
  159. PINCTRL_PIN(50, "MIO50"),
  160. PINCTRL_PIN(51, "MIO51"),
  161. PINCTRL_PIN(52, "MIO52"),
  162. PINCTRL_PIN(53, "MIO53"),
  163. PINCTRL_PIN(54, "EMIO_SD0_WP"),
  164. PINCTRL_PIN(55, "EMIO_SD0_CD"),
  165. PINCTRL_PIN(56, "EMIO_SD1_WP"),
  166. PINCTRL_PIN(57, "EMIO_SD1_CD"),
  167. };
  168. /* pin groups */
  169. static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
  170. 24, 25, 26, 27};
  171. static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
  172. 36, 37, 38, 39};
  173. static const unsigned int mdio0_0_pins[] = {52, 53};
  174. static const unsigned int mdio1_0_pins[] = {52, 53};
  175. static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
  176. static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
  177. static const unsigned int qspi_cs1_pins[] = {0};
  178. static const unsigned int qspi_fbclk_pins[] = {8};
  179. static const unsigned int spi0_0_pins[] = {16, 17, 21};
  180. static const unsigned int spi0_0_ss0_pins[] = {18};
  181. static const unsigned int spi0_0_ss1_pins[] = {19};
  182. static const unsigned int spi0_0_ss2_pins[] = {20,};
  183. static const unsigned int spi0_1_pins[] = {28, 29, 33};
  184. static const unsigned int spi0_1_ss0_pins[] = {30};
  185. static const unsigned int spi0_1_ss1_pins[] = {31};
  186. static const unsigned int spi0_1_ss2_pins[] = {32};
  187. static const unsigned int spi0_2_pins[] = {40, 41, 45};
  188. static const unsigned int spi0_2_ss0_pins[] = {42};
  189. static const unsigned int spi0_2_ss1_pins[] = {43};
  190. static const unsigned int spi0_2_ss2_pins[] = {44};
  191. static const unsigned int spi1_0_pins[] = {10, 11, 12};
  192. static const unsigned int spi1_0_ss0_pins[] = {13};
  193. static const unsigned int spi1_0_ss1_pins[] = {14};
  194. static const unsigned int spi1_0_ss2_pins[] = {15};
  195. static const unsigned int spi1_1_pins[] = {22, 23, 24};
  196. static const unsigned int spi1_1_ss0_pins[] = {25};
  197. static const unsigned int spi1_1_ss1_pins[] = {26};
  198. static const unsigned int spi1_1_ss2_pins[] = {27};
  199. static const unsigned int spi1_2_pins[] = {34, 35, 36};
  200. static const unsigned int spi1_2_ss0_pins[] = {37};
  201. static const unsigned int spi1_2_ss1_pins[] = {38};
  202. static const unsigned int spi1_2_ss2_pins[] = {39};
  203. static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
  204. static const unsigned int spi1_3_ss0_pins[] = {49};
  205. static const unsigned int spi1_3_ss1_pins[] = {50};
  206. static const unsigned int spi1_3_ss2_pins[] = {51};
  207. static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
  208. static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
  209. static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
  210. static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
  211. static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
  212. static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
  213. static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51};
  214. static const unsigned int sdio0_emio_wp_pins[] = {54};
  215. static const unsigned int sdio0_emio_cd_pins[] = {55};
  216. static const unsigned int sdio1_emio_wp_pins[] = {56};
  217. static const unsigned int sdio1_emio_cd_pins[] = {57};
  218. static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
  219. 15, 16, 17, 18, 19, 20, 21, 22, 23,
  220. 24, 25, 26, 27, 28, 29, 30, 31, 32,
  221. 33, 34, 35, 36, 37, 38, 39};
  222. static const unsigned int smc0_nor_cs1_pins[] = {1};
  223. static const unsigned int smc0_nor_addr25_pins[] = {1};
  224. static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
  225. 12, 13, 14, 16, 17, 18, 19, 20,
  226. 21, 22, 23};
  227. static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7,
  228. 8, 9, 10, 11, 12, 13, 14};
  229. /* Note: CAN MIO clock inputs are modeled in the clock framework */
  230. static const unsigned int can0_0_pins[] = {10, 11};
  231. static const unsigned int can0_1_pins[] = {14, 15};
  232. static const unsigned int can0_2_pins[] = {18, 19};
  233. static const unsigned int can0_3_pins[] = {22, 23};
  234. static const unsigned int can0_4_pins[] = {26, 27};
  235. static const unsigned int can0_5_pins[] = {30, 31};
  236. static const unsigned int can0_6_pins[] = {34, 35};
  237. static const unsigned int can0_7_pins[] = {38, 39};
  238. static const unsigned int can0_8_pins[] = {42, 43};
  239. static const unsigned int can0_9_pins[] = {46, 47};
  240. static const unsigned int can0_10_pins[] = {50, 51};
  241. static const unsigned int can1_0_pins[] = {8, 9};
  242. static const unsigned int can1_1_pins[] = {12, 13};
  243. static const unsigned int can1_2_pins[] = {16, 17};
  244. static const unsigned int can1_3_pins[] = {20, 21};
  245. static const unsigned int can1_4_pins[] = {24, 25};
  246. static const unsigned int can1_5_pins[] = {28, 29};
  247. static const unsigned int can1_6_pins[] = {32, 33};
  248. static const unsigned int can1_7_pins[] = {36, 37};
  249. static const unsigned int can1_8_pins[] = {40, 41};
  250. static const unsigned int can1_9_pins[] = {44, 45};
  251. static const unsigned int can1_10_pins[] = {48, 49};
  252. static const unsigned int can1_11_pins[] = {52, 53};
  253. static const unsigned int uart0_0_pins[] = {10, 11};
  254. static const unsigned int uart0_1_pins[] = {14, 15};
  255. static const unsigned int uart0_2_pins[] = {18, 19};
  256. static const unsigned int uart0_3_pins[] = {22, 23};
  257. static const unsigned int uart0_4_pins[] = {26, 27};
  258. static const unsigned int uart0_5_pins[] = {30, 31};
  259. static const unsigned int uart0_6_pins[] = {34, 35};
  260. static const unsigned int uart0_7_pins[] = {38, 39};
  261. static const unsigned int uart0_8_pins[] = {42, 43};
  262. static const unsigned int uart0_9_pins[] = {46, 47};
  263. static const unsigned int uart0_10_pins[] = {50, 51};
  264. static const unsigned int uart1_0_pins[] = {8, 9};
  265. static const unsigned int uart1_1_pins[] = {12, 13};
  266. static const unsigned int uart1_2_pins[] = {16, 17};
  267. static const unsigned int uart1_3_pins[] = {20, 21};
  268. static const unsigned int uart1_4_pins[] = {24, 25};
  269. static const unsigned int uart1_5_pins[] = {28, 29};
  270. static const unsigned int uart1_6_pins[] = {32, 33};
  271. static const unsigned int uart1_7_pins[] = {36, 37};
  272. static const unsigned int uart1_8_pins[] = {40, 41};
  273. static const unsigned int uart1_9_pins[] = {44, 45};
  274. static const unsigned int uart1_10_pins[] = {48, 49};
  275. static const unsigned int uart1_11_pins[] = {52, 53};
  276. static const unsigned int i2c0_0_pins[] = {10, 11};
  277. static const unsigned int i2c0_1_pins[] = {14, 15};
  278. static const unsigned int i2c0_2_pins[] = {18, 19};
  279. static const unsigned int i2c0_3_pins[] = {22, 23};
  280. static const unsigned int i2c0_4_pins[] = {26, 27};
  281. static const unsigned int i2c0_5_pins[] = {30, 31};
  282. static const unsigned int i2c0_6_pins[] = {34, 35};
  283. static const unsigned int i2c0_7_pins[] = {38, 39};
  284. static const unsigned int i2c0_8_pins[] = {42, 43};
  285. static const unsigned int i2c0_9_pins[] = {46, 47};
  286. static const unsigned int i2c0_10_pins[] = {50, 51};
  287. static const unsigned int i2c1_0_pins[] = {12, 13};
  288. static const unsigned int i2c1_1_pins[] = {16, 17};
  289. static const unsigned int i2c1_2_pins[] = {20, 21};
  290. static const unsigned int i2c1_3_pins[] = {24, 25};
  291. static const unsigned int i2c1_4_pins[] = {28, 29};
  292. static const unsigned int i2c1_5_pins[] = {32, 33};
  293. static const unsigned int i2c1_6_pins[] = {36, 37};
  294. static const unsigned int i2c1_7_pins[] = {40, 41};
  295. static const unsigned int i2c1_8_pins[] = {44, 45};
  296. static const unsigned int i2c1_9_pins[] = {48, 49};
  297. static const unsigned int i2c1_10_pins[] = {52, 53};
  298. static const unsigned int ttc0_0_pins[] = {18, 19};
  299. static const unsigned int ttc0_1_pins[] = {30, 31};
  300. static const unsigned int ttc0_2_pins[] = {42, 43};
  301. static const unsigned int ttc1_0_pins[] = {16, 17};
  302. static const unsigned int ttc1_1_pins[] = {28, 29};
  303. static const unsigned int ttc1_2_pins[] = {40, 41};
  304. static const unsigned int swdt0_0_pins[] = {14, 15};
  305. static const unsigned int swdt0_1_pins[] = {26, 27};
  306. static const unsigned int swdt0_2_pins[] = {38, 39};
  307. static const unsigned int swdt0_3_pins[] = {50, 51};
  308. static const unsigned int swdt0_4_pins[] = {52, 53};
  309. static const unsigned int gpio0_0_pins[] = {0};
  310. static const unsigned int gpio0_1_pins[] = {1};
  311. static const unsigned int gpio0_2_pins[] = {2};
  312. static const unsigned int gpio0_3_pins[] = {3};
  313. static const unsigned int gpio0_4_pins[] = {4};
  314. static const unsigned int gpio0_5_pins[] = {5};
  315. static const unsigned int gpio0_6_pins[] = {6};
  316. static const unsigned int gpio0_7_pins[] = {7};
  317. static const unsigned int gpio0_8_pins[] = {8};
  318. static const unsigned int gpio0_9_pins[] = {9};
  319. static const unsigned int gpio0_10_pins[] = {10};
  320. static const unsigned int gpio0_11_pins[] = {11};
  321. static const unsigned int gpio0_12_pins[] = {12};
  322. static const unsigned int gpio0_13_pins[] = {13};
  323. static const unsigned int gpio0_14_pins[] = {14};
  324. static const unsigned int gpio0_15_pins[] = {15};
  325. static const unsigned int gpio0_16_pins[] = {16};
  326. static const unsigned int gpio0_17_pins[] = {17};
  327. static const unsigned int gpio0_18_pins[] = {18};
  328. static const unsigned int gpio0_19_pins[] = {19};
  329. static const unsigned int gpio0_20_pins[] = {20};
  330. static const unsigned int gpio0_21_pins[] = {21};
  331. static const unsigned int gpio0_22_pins[] = {22};
  332. static const unsigned int gpio0_23_pins[] = {23};
  333. static const unsigned int gpio0_24_pins[] = {24};
  334. static const unsigned int gpio0_25_pins[] = {25};
  335. static const unsigned int gpio0_26_pins[] = {26};
  336. static const unsigned int gpio0_27_pins[] = {27};
  337. static const unsigned int gpio0_28_pins[] = {28};
  338. static const unsigned int gpio0_29_pins[] = {29};
  339. static const unsigned int gpio0_30_pins[] = {30};
  340. static const unsigned int gpio0_31_pins[] = {31};
  341. static const unsigned int gpio0_32_pins[] = {32};
  342. static const unsigned int gpio0_33_pins[] = {33};
  343. static const unsigned int gpio0_34_pins[] = {34};
  344. static const unsigned int gpio0_35_pins[] = {35};
  345. static const unsigned int gpio0_36_pins[] = {36};
  346. static const unsigned int gpio0_37_pins[] = {37};
  347. static const unsigned int gpio0_38_pins[] = {38};
  348. static const unsigned int gpio0_39_pins[] = {39};
  349. static const unsigned int gpio0_40_pins[] = {40};
  350. static const unsigned int gpio0_41_pins[] = {41};
  351. static const unsigned int gpio0_42_pins[] = {42};
  352. static const unsigned int gpio0_43_pins[] = {43};
  353. static const unsigned int gpio0_44_pins[] = {44};
  354. static const unsigned int gpio0_45_pins[] = {45};
  355. static const unsigned int gpio0_46_pins[] = {46};
  356. static const unsigned int gpio0_47_pins[] = {47};
  357. static const unsigned int gpio0_48_pins[] = {48};
  358. static const unsigned int gpio0_49_pins[] = {49};
  359. static const unsigned int gpio0_50_pins[] = {50};
  360. static const unsigned int gpio0_51_pins[] = {51};
  361. static const unsigned int gpio0_52_pins[] = {52};
  362. static const unsigned int gpio0_53_pins[] = {53};
  363. static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
  364. 37, 38, 39};
  365. static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
  366. 49, 50, 51};
  367. #define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
  368. { \
  369. .name = #nm "_grp", \
  370. .pins = nm ## _pins, \
  371. .npins = ARRAY_SIZE(nm ## _pins), \
  372. }
  373. static const struct zynq_pctrl_group zynq_pctrl_groups[] = {
  374. DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
  375. DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
  376. DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
  377. DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
  378. DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
  379. DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
  380. DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
  381. DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
  382. DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
  383. DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
  384. DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
  385. DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
  386. DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
  387. DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
  388. DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
  389. DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
  390. DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
  391. DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
  392. DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
  393. DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
  394. DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
  395. DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
  396. DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
  397. DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
  398. DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
  399. DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
  400. DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
  401. DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
  402. DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
  403. DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
  404. DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
  405. DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
  406. DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
  407. DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
  408. DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
  409. DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
  410. DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
  411. DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
  412. DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
  413. DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
  414. DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
  415. DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
  416. DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
  417. DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
  418. DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
  419. DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
  420. DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
  421. DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
  422. DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
  423. DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
  424. DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
  425. DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8),
  426. DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
  427. DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
  428. DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
  429. DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
  430. DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
  431. DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
  432. DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
  433. DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
  434. DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
  435. DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
  436. DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
  437. DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
  438. DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
  439. DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
  440. DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
  441. DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
  442. DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
  443. DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
  444. DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
  445. DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
  446. DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
  447. DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
  448. DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
  449. DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
  450. DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
  451. DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
  452. DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
  453. DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
  454. DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
  455. DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
  456. DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
  457. DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
  458. DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
  459. DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
  460. DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
  461. DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
  462. DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
  463. DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
  464. DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
  465. DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
  466. DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
  467. DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
  468. DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
  469. DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
  470. DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
  471. DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
  472. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
  473. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
  474. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
  475. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
  476. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
  477. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
  478. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
  479. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
  480. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
  481. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
  482. DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
  483. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
  484. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
  485. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
  486. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
  487. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
  488. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
  489. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
  490. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
  491. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
  492. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
  493. DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
  494. DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
  495. DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
  496. DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
  497. DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
  498. DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
  499. DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
  500. DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
  501. DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
  502. DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
  503. DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
  504. DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
  505. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
  506. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
  507. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
  508. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
  509. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
  510. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
  511. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
  512. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
  513. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
  514. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
  515. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
  516. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
  517. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
  518. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
  519. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
  520. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
  521. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
  522. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
  523. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
  524. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
  525. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
  526. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
  527. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
  528. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
  529. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
  530. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
  531. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
  532. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
  533. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
  534. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
  535. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
  536. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
  537. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
  538. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
  539. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
  540. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
  541. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
  542. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
  543. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
  544. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
  545. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
  546. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
  547. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
  548. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
  549. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
  550. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
  551. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
  552. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
  553. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
  554. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
  555. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
  556. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
  557. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
  558. DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
  559. DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
  560. DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
  561. };
  562. /* function groups */
  563. static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
  564. static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
  565. static const char * const usb0_groups[] = {"usb0_0_grp"};
  566. static const char * const usb1_groups[] = {"usb1_0_grp"};
  567. static const char * const mdio0_groups[] = {"mdio0_0_grp"};
  568. static const char * const mdio1_groups[] = {"mdio1_0_grp"};
  569. static const char * const qspi0_groups[] = {"qspi0_0_grp"};
  570. static const char * const qspi1_groups[] = {"qspi1_0_grp"};
  571. static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
  572. static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
  573. static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
  574. "spi0_2_grp"};
  575. static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
  576. "spi1_2_grp", "spi1_3_grp"};
  577. static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
  578. "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
  579. "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
  580. "spi0_2_ss1_grp", "spi0_2_ss2_grp"};
  581. static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
  582. "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
  583. "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
  584. "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
  585. "spi1_3_ss1_grp", "spi1_3_ss2_grp"};
  586. static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
  587. "sdio0_2_grp"};
  588. static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
  589. "sdio1_2_grp", "sdio1_3_grp"};
  590. static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
  591. "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
  592. "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
  593. "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
  594. "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
  595. "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
  596. "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
  597. "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
  598. "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
  599. "gpio0_50_grp", "gpio0_52_grp"};
  600. static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
  601. "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
  602. "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
  603. "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
  604. "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
  605. "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
  606. "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
  607. "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
  608. "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
  609. "gpio0_51_grp", "gpio0_53_grp"};
  610. static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
  611. "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
  612. "gpio0_10_grp", "gpio0_12_grp",
  613. "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
  614. "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
  615. "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
  616. "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
  617. "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
  618. "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
  619. "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
  620. "gpio0_3_grp", "gpio0_5_grp",
  621. "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
  622. "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
  623. "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
  624. "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
  625. "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
  626. "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
  627. "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
  628. "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
  629. static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
  630. "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
  631. "gpio0_10_grp", "gpio0_12_grp",
  632. "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
  633. "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
  634. "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
  635. "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
  636. "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
  637. "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
  638. "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
  639. "gpio0_3_grp", "gpio0_5_grp",
  640. "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
  641. "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
  642. "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
  643. "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
  644. "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
  645. "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
  646. "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
  647. "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
  648. static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
  649. "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
  650. "gpio0_10_grp", "gpio0_12_grp",
  651. "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
  652. "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
  653. "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
  654. "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
  655. "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
  656. "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
  657. "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
  658. "gpio0_3_grp", "gpio0_5_grp",
  659. "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
  660. "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
  661. "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
  662. "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
  663. "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
  664. "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
  665. "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
  666. "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
  667. static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
  668. "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
  669. "gpio0_10_grp", "gpio0_12_grp",
  670. "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
  671. "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
  672. "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
  673. "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
  674. "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
  675. "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
  676. "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
  677. "gpio0_3_grp", "gpio0_5_grp",
  678. "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
  679. "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
  680. "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
  681. "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
  682. "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
  683. "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
  684. "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
  685. "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
  686. static const char * const smc0_nor_groups[] = {"smc0_nor_grp"};
  687. static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
  688. static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
  689. static const char * const smc0_nand_groups[] = {"smc0_nand_grp",
  690. "smc0_nand8_grp"};
  691. static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
  692. "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
  693. "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
  694. "can0_10_grp"};
  695. static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
  696. "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
  697. "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
  698. "can1_10_grp", "can1_11_grp"};
  699. static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
  700. "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
  701. "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
  702. "uart0_10_grp"};
  703. static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
  704. "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
  705. "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
  706. "uart1_10_grp", "uart1_11_grp"};
  707. static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
  708. "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
  709. "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
  710. "i2c0_10_grp"};
  711. static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
  712. "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
  713. "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
  714. "i2c1_10_grp"};
  715. static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
  716. "ttc0_2_grp"};
  717. static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
  718. "ttc1_2_grp"};
  719. static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
  720. "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
  721. static const char * const gpio0_groups[] = {"gpio0_0_grp",
  722. "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
  723. "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
  724. "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
  725. "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
  726. "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
  727. "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
  728. "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
  729. "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
  730. "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
  731. "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
  732. "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
  733. "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
  734. "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
  735. "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
  736. "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
  737. "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
  738. "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
  739. "gpio0_51_grp", "gpio0_53_grp"};
  740. #define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \
  741. [ZYNQ_PMUX_##fname] = { \
  742. .name = #fname, \
  743. .groups = fname##_groups, \
  744. .ngroups = ARRAY_SIZE(fname##_groups), \
  745. .mux_val = mval, \
  746. }
  747. #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
  748. [ZYNQ_PMUX_##fname] = { \
  749. .name = #fname, \
  750. .groups = fname##_groups, \
  751. .ngroups = ARRAY_SIZE(fname##_groups), \
  752. .mux_val = mval, \
  753. .mux = offset, \
  754. .mux_mask = mask, \
  755. .mux_shift = shift, \
  756. }
  757. #define ZYNQ_SDIO_WP_SHIFT 0
  758. #define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT)
  759. #define ZYNQ_SDIO_CD_SHIFT 16
  760. #define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT)
  761. static const struct zynq_pinmux_function zynq_pmux_functions[] = {
  762. DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
  763. DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
  764. DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
  765. DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
  766. DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
  767. DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
  768. DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
  769. DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
  770. DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
  771. DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
  772. DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
  773. DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
  774. DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
  775. DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
  776. DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
  777. DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
  778. DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
  779. ZYNQ_SDIO_WP_SHIFT),
  780. DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
  781. ZYNQ_SDIO_CD_SHIFT),
  782. DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
  783. DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
  784. DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
  785. ZYNQ_SDIO_WP_SHIFT),
  786. DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
  787. ZYNQ_SDIO_CD_SHIFT),
  788. DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
  789. DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
  790. DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
  791. DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
  792. DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
  793. DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
  794. DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
  795. DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
  796. DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
  797. DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
  798. DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
  799. DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
  800. DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
  801. DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
  802. };
  803. /* pinctrl */
  804. static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
  805. {
  806. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  807. return pctrl->ngroups;
  808. }
  809. static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
  810. unsigned int selector)
  811. {
  812. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  813. return pctrl->groups[selector].name;
  814. }
  815. static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
  816. unsigned int selector,
  817. const unsigned int **pins,
  818. unsigned int *num_pins)
  819. {
  820. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  821. *pins = pctrl->groups[selector].pins;
  822. *num_pins = pctrl->groups[selector].npins;
  823. return 0;
  824. }
  825. static const struct pinctrl_ops zynq_pctrl_ops = {
  826. .get_groups_count = zynq_pctrl_get_groups_count,
  827. .get_group_name = zynq_pctrl_get_group_name,
  828. .get_group_pins = zynq_pctrl_get_group_pins,
  829. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  830. .dt_free_map = pinctrl_utils_free_map,
  831. };
  832. /* pinmux */
  833. static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
  834. {
  835. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  836. return pctrl->nfuncs;
  837. }
  838. static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
  839. unsigned int selector)
  840. {
  841. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  842. return pctrl->funcs[selector].name;
  843. }
  844. static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
  845. unsigned int selector,
  846. const char * const **groups,
  847. unsigned * const num_groups)
  848. {
  849. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  850. *groups = pctrl->funcs[selector].groups;
  851. *num_groups = pctrl->funcs[selector].ngroups;
  852. return 0;
  853. }
  854. static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
  855. unsigned int function,
  856. unsigned int group)
  857. {
  858. int i, ret;
  859. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  860. const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
  861. const struct zynq_pinmux_function *func = &pctrl->funcs[function];
  862. /*
  863. * SD WP & CD are special. They have dedicated registers
  864. * to mux them in
  865. */
  866. if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
  867. function == ZYNQ_PMUX_sdio1_cd ||
  868. function == ZYNQ_PMUX_sdio1_wp) {
  869. u32 reg;
  870. ret = regmap_read(pctrl->syscon,
  871. pctrl->pctrl_offset + func->mux, &reg);
  872. if (ret)
  873. return ret;
  874. reg &= ~func->mux_mask;
  875. reg |= pgrp->pins[0] << func->mux_shift;
  876. ret = regmap_write(pctrl->syscon,
  877. pctrl->pctrl_offset + func->mux, reg);
  878. if (ret)
  879. return ret;
  880. } else {
  881. for (i = 0; i < pgrp->npins; i++) {
  882. unsigned int pin = pgrp->pins[i];
  883. u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
  884. ret = regmap_read(pctrl->syscon, addr, &reg);
  885. if (ret)
  886. return ret;
  887. reg &= ~ZYNQ_PINMUX_MUX_MASK;
  888. reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
  889. ret = regmap_write(pctrl->syscon, addr, reg);
  890. if (ret)
  891. return ret;
  892. }
  893. }
  894. return 0;
  895. }
  896. static const struct pinmux_ops zynq_pinmux_ops = {
  897. .get_functions_count = zynq_pmux_get_functions_count,
  898. .get_function_name = zynq_pmux_get_function_name,
  899. .get_function_groups = zynq_pmux_get_function_groups,
  900. .set_mux = zynq_pinmux_set_mux,
  901. };
  902. /* pinconfig */
  903. #define ZYNQ_PINCONF_TRISTATE BIT(0)
  904. #define ZYNQ_PINCONF_SPEED BIT(8)
  905. #define ZYNQ_PINCONF_PULLUP BIT(12)
  906. #define ZYNQ_PINCONF_DISABLE_RECVR BIT(13)
  907. #define ZYNQ_PINCONF_IOTYPE_SHIFT 9
  908. #define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
  909. enum zynq_io_standards {
  910. zynq_iostd_min,
  911. zynq_iostd_lvcmos18,
  912. zynq_iostd_lvcmos25,
  913. zynq_iostd_lvcmos33,
  914. zynq_iostd_hstl,
  915. zynq_iostd_max
  916. };
  917. /*
  918. * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
  919. * this parameter (on a custom format) tells the driver which alternative
  920. * IO standard to use.
  921. */
  922. #define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1)
  923. static const struct pinconf_generic_params zynq_dt_params[] = {
  924. {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
  925. };
  926. #ifdef CONFIG_DEBUG_FS
  927. static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)]
  928. = { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
  929. };
  930. #endif
  931. static unsigned int zynq_pinconf_iostd_get(u32 reg)
  932. {
  933. return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
  934. }
  935. static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
  936. unsigned int pin,
  937. unsigned long *config)
  938. {
  939. u32 reg;
  940. int ret;
  941. unsigned int arg = 0;
  942. unsigned int param = pinconf_to_config_param(*config);
  943. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  944. if (pin >= ZYNQ_NUM_MIOS)
  945. return -ENOTSUPP;
  946. ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
  947. if (ret)
  948. return -EIO;
  949. switch (param) {
  950. case PIN_CONFIG_BIAS_PULL_UP:
  951. if (!(reg & ZYNQ_PINCONF_PULLUP))
  952. return -EINVAL;
  953. arg = 1;
  954. break;
  955. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  956. if (!(reg & ZYNQ_PINCONF_TRISTATE))
  957. return -EINVAL;
  958. arg = 1;
  959. break;
  960. case PIN_CONFIG_BIAS_DISABLE:
  961. if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
  962. return -EINVAL;
  963. break;
  964. case PIN_CONFIG_SLEW_RATE:
  965. arg = !!(reg & ZYNQ_PINCONF_SPEED);
  966. break;
  967. case PIN_CONFIG_LOW_POWER_MODE:
  968. {
  969. enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
  970. if (iostd != zynq_iostd_hstl)
  971. return -EINVAL;
  972. if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
  973. return -EINVAL;
  974. arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
  975. break;
  976. }
  977. case PIN_CONFIG_IOSTANDARD:
  978. arg = zynq_pinconf_iostd_get(reg);
  979. break;
  980. default:
  981. return -ENOTSUPP;
  982. }
  983. *config = pinconf_to_config_packed(param, arg);
  984. return 0;
  985. }
  986. static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
  987. unsigned int pin,
  988. unsigned long *configs,
  989. unsigned int num_configs)
  990. {
  991. int i, ret;
  992. u32 reg;
  993. u32 pullup = 0;
  994. u32 tristate = 0;
  995. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  996. if (pin >= ZYNQ_NUM_MIOS)
  997. return -ENOTSUPP;
  998. ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), &reg);
  999. if (ret)
  1000. return -EIO;
  1001. for (i = 0; i < num_configs; i++) {
  1002. unsigned int param = pinconf_to_config_param(configs[i]);
  1003. unsigned int arg = pinconf_to_config_argument(configs[i]);
  1004. switch (param) {
  1005. case PIN_CONFIG_BIAS_PULL_UP:
  1006. pullup = ZYNQ_PINCONF_PULLUP;
  1007. break;
  1008. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  1009. tristate = ZYNQ_PINCONF_TRISTATE;
  1010. break;
  1011. case PIN_CONFIG_BIAS_DISABLE:
  1012. reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
  1013. break;
  1014. case PIN_CONFIG_SLEW_RATE:
  1015. if (arg)
  1016. reg |= ZYNQ_PINCONF_SPEED;
  1017. else
  1018. reg &= ~ZYNQ_PINCONF_SPEED;
  1019. break;
  1020. case PIN_CONFIG_IOSTANDARD:
  1021. if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
  1022. dev_warn(pctldev->dev,
  1023. "unsupported IO standard '%u'\n",
  1024. param);
  1025. break;
  1026. }
  1027. reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
  1028. reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
  1029. break;
  1030. case PIN_CONFIG_LOW_POWER_MODE:
  1031. if (arg)
  1032. reg |= ZYNQ_PINCONF_DISABLE_RECVR;
  1033. else
  1034. reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
  1035. break;
  1036. default:
  1037. dev_warn(pctldev->dev,
  1038. "unsupported configuration parameter '%u'\n",
  1039. param);
  1040. continue;
  1041. }
  1042. }
  1043. if (tristate || pullup) {
  1044. reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
  1045. reg |= tristate | pullup;
  1046. }
  1047. ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
  1048. if (ret)
  1049. return -EIO;
  1050. return 0;
  1051. }
  1052. static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
  1053. unsigned int selector,
  1054. unsigned long *configs,
  1055. unsigned int num_configs)
  1056. {
  1057. int i, ret;
  1058. struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  1059. const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
  1060. for (i = 0; i < pgrp->npins; i++) {
  1061. ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
  1062. num_configs);
  1063. if (ret)
  1064. return ret;
  1065. }
  1066. return 0;
  1067. }
  1068. static const struct pinconf_ops zynq_pinconf_ops = {
  1069. .is_generic = true,
  1070. .pin_config_get = zynq_pinconf_cfg_get,
  1071. .pin_config_set = zynq_pinconf_cfg_set,
  1072. .pin_config_group_set = zynq_pinconf_group_set,
  1073. };
  1074. static struct pinctrl_desc zynq_desc = {
  1075. .name = "zynq_pinctrl",
  1076. .pins = zynq_pins,
  1077. .npins = ARRAY_SIZE(zynq_pins),
  1078. .pctlops = &zynq_pctrl_ops,
  1079. .pmxops = &zynq_pinmux_ops,
  1080. .confops = &zynq_pinconf_ops,
  1081. .num_custom_params = ARRAY_SIZE(zynq_dt_params),
  1082. .custom_params = zynq_dt_params,
  1083. #ifdef CONFIG_DEBUG_FS
  1084. .custom_conf_items = zynq_conf_items,
  1085. #endif
  1086. .owner = THIS_MODULE,
  1087. };
  1088. static int zynq_pinctrl_probe(struct platform_device *pdev)
  1089. {
  1090. struct resource *res;
  1091. struct zynq_pinctrl *pctrl;
  1092. pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
  1093. if (!pctrl)
  1094. return -ENOMEM;
  1095. pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  1096. "syscon");
  1097. if (IS_ERR(pctrl->syscon)) {
  1098. dev_err(&pdev->dev, "unable to get syscon\n");
  1099. return PTR_ERR(pctrl->syscon);
  1100. }
  1101. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1102. if (!res) {
  1103. dev_err(&pdev->dev, "missing IO resource\n");
  1104. return -ENODEV;
  1105. }
  1106. pctrl->pctrl_offset = res->start;
  1107. pctrl->groups = zynq_pctrl_groups;
  1108. pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
  1109. pctrl->funcs = zynq_pmux_functions;
  1110. pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
  1111. pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl);
  1112. if (IS_ERR(pctrl->pctrl))
  1113. return PTR_ERR(pctrl->pctrl);
  1114. platform_set_drvdata(pdev, pctrl);
  1115. dev_info(&pdev->dev, "zynq pinctrl initialized\n");
  1116. return 0;
  1117. }
  1118. static const struct of_device_id zynq_pinctrl_of_match[] = {
  1119. { .compatible = "xlnx,pinctrl-zynq" },
  1120. { }
  1121. };
  1122. static struct platform_driver zynq_pinctrl_driver = {
  1123. .driver = {
  1124. .name = "zynq-pinctrl",
  1125. .of_match_table = zynq_pinctrl_of_match,
  1126. },
  1127. .probe = zynq_pinctrl_probe,
  1128. };
  1129. static int __init zynq_pinctrl_init(void)
  1130. {
  1131. return platform_driver_register(&zynq_pinctrl_driver);
  1132. }
  1133. arch_initcall(zynq_pinctrl_init);