pinctrl-sx150x.c 29 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. *
  6. * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
  7. *
  8. * Driver for Semtech SX150X I2C GPIO Expanders
  9. * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
  10. *
  11. * Author: Gregory Bean <gbean@codeaurora.org>
  12. */
  13. #include <linux/regmap.h>
  14. #include <linux/i2c.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/irq.h>
  18. #include <linux/mutex.h>
  19. #include <linux/slab.h>
  20. #include <linux/of.h>
  21. #include <linux/of_device.h>
  22. #include <linux/gpio/driver.h>
  23. #include <linux/pinctrl/pinconf.h>
  24. #include <linux/pinctrl/pinctrl.h>
  25. #include <linux/pinctrl/pinmux.h>
  26. #include <linux/pinctrl/pinconf-generic.h>
  27. #include "core.h"
  28. #include "pinconf.h"
  29. #include "pinctrl-utils.h"
  30. /* The chip models of sx150x */
  31. enum {
  32. SX150X_123 = 0,
  33. SX150X_456,
  34. SX150X_789,
  35. };
  36. enum {
  37. SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
  38. SX150X_MAX_REGISTER = 0xad,
  39. SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
  40. SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
  41. SX150X_789_RESET_KEY1 = 0x12,
  42. SX150X_789_RESET_KEY2 = 0x34,
  43. };
  44. struct sx150x_123_pri {
  45. u8 reg_pld_mode;
  46. u8 reg_pld_table0;
  47. u8 reg_pld_table1;
  48. u8 reg_pld_table2;
  49. u8 reg_pld_table3;
  50. u8 reg_pld_table4;
  51. u8 reg_advanced;
  52. };
  53. struct sx150x_456_pri {
  54. u8 reg_pld_mode;
  55. u8 reg_pld_table0;
  56. u8 reg_pld_table1;
  57. u8 reg_pld_table2;
  58. u8 reg_pld_table3;
  59. u8 reg_pld_table4;
  60. u8 reg_advanced;
  61. };
  62. struct sx150x_789_pri {
  63. u8 reg_drain;
  64. u8 reg_polarity;
  65. u8 reg_clock;
  66. u8 reg_misc;
  67. u8 reg_reset;
  68. u8 ngpios;
  69. };
  70. struct sx150x_device_data {
  71. u8 model;
  72. u8 reg_pullup;
  73. u8 reg_pulldn;
  74. u8 reg_dir;
  75. u8 reg_data;
  76. u8 reg_irq_mask;
  77. u8 reg_irq_src;
  78. u8 reg_sense;
  79. u8 ngpios;
  80. union {
  81. struct sx150x_123_pri x123;
  82. struct sx150x_456_pri x456;
  83. struct sx150x_789_pri x789;
  84. } pri;
  85. const struct pinctrl_pin_desc *pins;
  86. unsigned int npins;
  87. };
  88. struct sx150x_pinctrl {
  89. struct device *dev;
  90. struct i2c_client *client;
  91. struct pinctrl_dev *pctldev;
  92. struct pinctrl_desc pinctrl_desc;
  93. struct gpio_chip gpio;
  94. struct irq_chip irq_chip;
  95. struct regmap *regmap;
  96. struct {
  97. u32 sense;
  98. u32 masked;
  99. } irq;
  100. struct mutex lock;
  101. const struct sx150x_device_data *data;
  102. };
  103. static const struct pinctrl_pin_desc sx150x_4_pins[] = {
  104. PINCTRL_PIN(0, "gpio0"),
  105. PINCTRL_PIN(1, "gpio1"),
  106. PINCTRL_PIN(2, "gpio2"),
  107. PINCTRL_PIN(3, "gpio3"),
  108. PINCTRL_PIN(4, "oscio"),
  109. };
  110. static const struct pinctrl_pin_desc sx150x_8_pins[] = {
  111. PINCTRL_PIN(0, "gpio0"),
  112. PINCTRL_PIN(1, "gpio1"),
  113. PINCTRL_PIN(2, "gpio2"),
  114. PINCTRL_PIN(3, "gpio3"),
  115. PINCTRL_PIN(4, "gpio4"),
  116. PINCTRL_PIN(5, "gpio5"),
  117. PINCTRL_PIN(6, "gpio6"),
  118. PINCTRL_PIN(7, "gpio7"),
  119. PINCTRL_PIN(8, "oscio"),
  120. };
  121. static const struct pinctrl_pin_desc sx150x_16_pins[] = {
  122. PINCTRL_PIN(0, "gpio0"),
  123. PINCTRL_PIN(1, "gpio1"),
  124. PINCTRL_PIN(2, "gpio2"),
  125. PINCTRL_PIN(3, "gpio3"),
  126. PINCTRL_PIN(4, "gpio4"),
  127. PINCTRL_PIN(5, "gpio5"),
  128. PINCTRL_PIN(6, "gpio6"),
  129. PINCTRL_PIN(7, "gpio7"),
  130. PINCTRL_PIN(8, "gpio8"),
  131. PINCTRL_PIN(9, "gpio9"),
  132. PINCTRL_PIN(10, "gpio10"),
  133. PINCTRL_PIN(11, "gpio11"),
  134. PINCTRL_PIN(12, "gpio12"),
  135. PINCTRL_PIN(13, "gpio13"),
  136. PINCTRL_PIN(14, "gpio14"),
  137. PINCTRL_PIN(15, "gpio15"),
  138. PINCTRL_PIN(16, "oscio"),
  139. };
  140. static const struct sx150x_device_data sx1501q_device_data = {
  141. .model = SX150X_123,
  142. .reg_pullup = 0x02,
  143. .reg_pulldn = 0x03,
  144. .reg_dir = 0x01,
  145. .reg_data = 0x00,
  146. .reg_irq_mask = 0x05,
  147. .reg_irq_src = 0x08,
  148. .reg_sense = 0x07,
  149. .pri.x123 = {
  150. .reg_pld_mode = 0x10,
  151. .reg_pld_table0 = 0x11,
  152. .reg_pld_table2 = 0x13,
  153. .reg_advanced = 0xad,
  154. },
  155. .ngpios = 4,
  156. .pins = sx150x_4_pins,
  157. .npins = 4, /* oscio not available */
  158. };
  159. static const struct sx150x_device_data sx1502q_device_data = {
  160. .model = SX150X_123,
  161. .reg_pullup = 0x02,
  162. .reg_pulldn = 0x03,
  163. .reg_dir = 0x01,
  164. .reg_data = 0x00,
  165. .reg_irq_mask = 0x05,
  166. .reg_irq_src = 0x08,
  167. .reg_sense = 0x06,
  168. .pri.x123 = {
  169. .reg_pld_mode = 0x10,
  170. .reg_pld_table0 = 0x11,
  171. .reg_pld_table1 = 0x12,
  172. .reg_pld_table2 = 0x13,
  173. .reg_pld_table3 = 0x14,
  174. .reg_pld_table4 = 0x15,
  175. .reg_advanced = 0xad,
  176. },
  177. .ngpios = 8,
  178. .pins = sx150x_8_pins,
  179. .npins = 8, /* oscio not available */
  180. };
  181. static const struct sx150x_device_data sx1503q_device_data = {
  182. .model = SX150X_123,
  183. .reg_pullup = 0x04,
  184. .reg_pulldn = 0x06,
  185. .reg_dir = 0x02,
  186. .reg_data = 0x00,
  187. .reg_irq_mask = 0x08,
  188. .reg_irq_src = 0x0e,
  189. .reg_sense = 0x0a,
  190. .pri.x123 = {
  191. .reg_pld_mode = 0x20,
  192. .reg_pld_table0 = 0x22,
  193. .reg_pld_table1 = 0x24,
  194. .reg_pld_table2 = 0x26,
  195. .reg_pld_table3 = 0x28,
  196. .reg_pld_table4 = 0x2a,
  197. .reg_advanced = 0xad,
  198. },
  199. .ngpios = 16,
  200. .pins = sx150x_16_pins,
  201. .npins = 16, /* oscio not available */
  202. };
  203. static const struct sx150x_device_data sx1504q_device_data = {
  204. .model = SX150X_456,
  205. .reg_pullup = 0x02,
  206. .reg_pulldn = 0x03,
  207. .reg_dir = 0x01,
  208. .reg_data = 0x00,
  209. .reg_irq_mask = 0x05,
  210. .reg_irq_src = 0x08,
  211. .reg_sense = 0x07,
  212. .pri.x456 = {
  213. .reg_pld_mode = 0x10,
  214. .reg_pld_table0 = 0x11,
  215. .reg_pld_table2 = 0x13,
  216. },
  217. .ngpios = 4,
  218. .pins = sx150x_4_pins,
  219. .npins = 4, /* oscio not available */
  220. };
  221. static const struct sx150x_device_data sx1505q_device_data = {
  222. .model = SX150X_456,
  223. .reg_pullup = 0x02,
  224. .reg_pulldn = 0x03,
  225. .reg_dir = 0x01,
  226. .reg_data = 0x00,
  227. .reg_irq_mask = 0x05,
  228. .reg_irq_src = 0x08,
  229. .reg_sense = 0x06,
  230. .pri.x456 = {
  231. .reg_pld_mode = 0x10,
  232. .reg_pld_table0 = 0x11,
  233. .reg_pld_table1 = 0x12,
  234. .reg_pld_table2 = 0x13,
  235. .reg_pld_table3 = 0x14,
  236. .reg_pld_table4 = 0x15,
  237. },
  238. .ngpios = 8,
  239. .pins = sx150x_8_pins,
  240. .npins = 8, /* oscio not available */
  241. };
  242. static const struct sx150x_device_data sx1506q_device_data = {
  243. .model = SX150X_456,
  244. .reg_pullup = 0x04,
  245. .reg_pulldn = 0x06,
  246. .reg_dir = 0x02,
  247. .reg_data = 0x00,
  248. .reg_irq_mask = 0x08,
  249. .reg_irq_src = 0x0e,
  250. .reg_sense = 0x0a,
  251. .pri.x456 = {
  252. .reg_pld_mode = 0x20,
  253. .reg_pld_table0 = 0x22,
  254. .reg_pld_table1 = 0x24,
  255. .reg_pld_table2 = 0x26,
  256. .reg_pld_table3 = 0x28,
  257. .reg_pld_table4 = 0x2a,
  258. .reg_advanced = 0xad,
  259. },
  260. .ngpios = 16,
  261. .pins = sx150x_16_pins,
  262. .npins = 16, /* oscio not available */
  263. };
  264. static const struct sx150x_device_data sx1507q_device_data = {
  265. .model = SX150X_789,
  266. .reg_pullup = 0x03,
  267. .reg_pulldn = 0x04,
  268. .reg_dir = 0x07,
  269. .reg_data = 0x08,
  270. .reg_irq_mask = 0x09,
  271. .reg_irq_src = 0x0b,
  272. .reg_sense = 0x0a,
  273. .pri.x789 = {
  274. .reg_drain = 0x05,
  275. .reg_polarity = 0x06,
  276. .reg_clock = 0x0d,
  277. .reg_misc = 0x0e,
  278. .reg_reset = 0x7d,
  279. },
  280. .ngpios = 4,
  281. .pins = sx150x_4_pins,
  282. .npins = ARRAY_SIZE(sx150x_4_pins),
  283. };
  284. static const struct sx150x_device_data sx1508q_device_data = {
  285. .model = SX150X_789,
  286. .reg_pullup = 0x03,
  287. .reg_pulldn = 0x04,
  288. .reg_dir = 0x07,
  289. .reg_data = 0x08,
  290. .reg_irq_mask = 0x09,
  291. .reg_irq_src = 0x0c,
  292. .reg_sense = 0x0a,
  293. .pri.x789 = {
  294. .reg_drain = 0x05,
  295. .reg_polarity = 0x06,
  296. .reg_clock = 0x0f,
  297. .reg_misc = 0x10,
  298. .reg_reset = 0x7d,
  299. },
  300. .ngpios = 8,
  301. .pins = sx150x_8_pins,
  302. .npins = ARRAY_SIZE(sx150x_8_pins),
  303. };
  304. static const struct sx150x_device_data sx1509q_device_data = {
  305. .model = SX150X_789,
  306. .reg_pullup = 0x06,
  307. .reg_pulldn = 0x08,
  308. .reg_dir = 0x0e,
  309. .reg_data = 0x10,
  310. .reg_irq_mask = 0x12,
  311. .reg_irq_src = 0x18,
  312. .reg_sense = 0x14,
  313. .pri.x789 = {
  314. .reg_drain = 0x0a,
  315. .reg_polarity = 0x0c,
  316. .reg_clock = 0x1e,
  317. .reg_misc = 0x1f,
  318. .reg_reset = 0x7d,
  319. },
  320. .ngpios = 16,
  321. .pins = sx150x_16_pins,
  322. .npins = ARRAY_SIZE(sx150x_16_pins),
  323. };
  324. static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  325. {
  326. return 0;
  327. }
  328. static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  329. unsigned int group)
  330. {
  331. return NULL;
  332. }
  333. static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  334. unsigned int group,
  335. const unsigned int **pins,
  336. unsigned int *num_pins)
  337. {
  338. return -ENOTSUPP;
  339. }
  340. static const struct pinctrl_ops sx150x_pinctrl_ops = {
  341. .get_groups_count = sx150x_pinctrl_get_groups_count,
  342. .get_group_name = sx150x_pinctrl_get_group_name,
  343. .get_group_pins = sx150x_pinctrl_get_group_pins,
  344. #ifdef CONFIG_OF
  345. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  346. .dt_free_map = pinctrl_utils_free_map,
  347. #endif
  348. };
  349. static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
  350. {
  351. if (pin >= pctl->data->npins)
  352. return false;
  353. /* OSCIO pin is only present in 789 devices */
  354. if (pctl->data->model != SX150X_789)
  355. return false;
  356. return !strcmp(pctl->data->pins[pin].name, "oscio");
  357. }
  358. static int sx150x_gpio_get_direction(struct gpio_chip *chip,
  359. unsigned int offset)
  360. {
  361. struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
  362. unsigned int value;
  363. int ret;
  364. if (sx150x_pin_is_oscio(pctl, offset))
  365. return GPIO_LINE_DIRECTION_OUT;
  366. ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
  367. if (ret < 0)
  368. return ret;
  369. if (value & BIT(offset))
  370. return GPIO_LINE_DIRECTION_IN;
  371. return GPIO_LINE_DIRECTION_OUT;
  372. }
  373. static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
  374. {
  375. struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
  376. unsigned int value;
  377. int ret;
  378. if (sx150x_pin_is_oscio(pctl, offset))
  379. return -EINVAL;
  380. ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
  381. if (ret < 0)
  382. return ret;
  383. return !!(value & BIT(offset));
  384. }
  385. static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
  386. int value)
  387. {
  388. return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
  389. BIT(offset), value ? BIT(offset) : 0);
  390. }
  391. static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
  392. int value)
  393. {
  394. return regmap_write(pctl->regmap,
  395. pctl->data->pri.x789.reg_clock,
  396. (value ? 0x1f : 0x10));
  397. }
  398. static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
  399. int value)
  400. {
  401. struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
  402. if (sx150x_pin_is_oscio(pctl, offset))
  403. sx150x_gpio_oscio_set(pctl, value);
  404. else
  405. __sx150x_gpio_set(pctl, offset, value);
  406. }
  407. static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
  408. unsigned long *mask,
  409. unsigned long *bits)
  410. {
  411. struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
  412. regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
  413. }
  414. static int sx150x_gpio_direction_input(struct gpio_chip *chip,
  415. unsigned int offset)
  416. {
  417. struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
  418. if (sx150x_pin_is_oscio(pctl, offset))
  419. return -EINVAL;
  420. return regmap_write_bits(pctl->regmap,
  421. pctl->data->reg_dir,
  422. BIT(offset), BIT(offset));
  423. }
  424. static int sx150x_gpio_direction_output(struct gpio_chip *chip,
  425. unsigned int offset, int value)
  426. {
  427. struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
  428. int ret;
  429. if (sx150x_pin_is_oscio(pctl, offset))
  430. return sx150x_gpio_oscio_set(pctl, value);
  431. ret = __sx150x_gpio_set(pctl, offset, value);
  432. if (ret < 0)
  433. return ret;
  434. return regmap_write_bits(pctl->regmap,
  435. pctl->data->reg_dir,
  436. BIT(offset), 0);
  437. }
  438. static void sx150x_irq_mask(struct irq_data *d)
  439. {
  440. struct sx150x_pinctrl *pctl =
  441. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  442. unsigned int n = d->hwirq;
  443. pctl->irq.masked |= BIT(n);
  444. }
  445. static void sx150x_irq_unmask(struct irq_data *d)
  446. {
  447. struct sx150x_pinctrl *pctl =
  448. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  449. unsigned int n = d->hwirq;
  450. pctl->irq.masked &= ~BIT(n);
  451. }
  452. static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
  453. unsigned int line, unsigned int sense)
  454. {
  455. /*
  456. * Every interrupt line is represented by two bits shifted
  457. * proportionally to the line number
  458. */
  459. const unsigned int n = line * 2;
  460. const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
  461. SX150X_IRQ_TYPE_EDGE_FALLING) << n);
  462. pctl->irq.sense &= mask;
  463. pctl->irq.sense |= sense << n;
  464. }
  465. static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
  466. {
  467. struct sx150x_pinctrl *pctl =
  468. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  469. unsigned int n, val = 0;
  470. if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
  471. return -EINVAL;
  472. n = d->hwirq;
  473. if (flow_type & IRQ_TYPE_EDGE_RISING)
  474. val |= SX150X_IRQ_TYPE_EDGE_RISING;
  475. if (flow_type & IRQ_TYPE_EDGE_FALLING)
  476. val |= SX150X_IRQ_TYPE_EDGE_FALLING;
  477. sx150x_irq_set_sense(pctl, n, val);
  478. return 0;
  479. }
  480. static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
  481. {
  482. struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
  483. unsigned long n, status;
  484. unsigned int val;
  485. int err;
  486. err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
  487. if (err < 0)
  488. return IRQ_NONE;
  489. err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
  490. if (err < 0)
  491. return IRQ_NONE;
  492. status = val;
  493. for_each_set_bit(n, &status, pctl->data->ngpios)
  494. handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
  495. return IRQ_HANDLED;
  496. }
  497. static void sx150x_irq_bus_lock(struct irq_data *d)
  498. {
  499. struct sx150x_pinctrl *pctl =
  500. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  501. mutex_lock(&pctl->lock);
  502. }
  503. static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
  504. {
  505. struct sx150x_pinctrl *pctl =
  506. gpiochip_get_data(irq_data_get_irq_chip_data(d));
  507. regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
  508. regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
  509. mutex_unlock(&pctl->lock);
  510. }
  511. static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
  512. unsigned long *config)
  513. {
  514. struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  515. unsigned int param = pinconf_to_config_param(*config);
  516. int ret;
  517. u32 arg;
  518. unsigned int data;
  519. if (sx150x_pin_is_oscio(pctl, pin)) {
  520. switch (param) {
  521. case PIN_CONFIG_DRIVE_PUSH_PULL:
  522. case PIN_CONFIG_OUTPUT:
  523. ret = regmap_read(pctl->regmap,
  524. pctl->data->pri.x789.reg_clock,
  525. &data);
  526. if (ret < 0)
  527. return ret;
  528. if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
  529. arg = (data & 0x1f) ? 1 : 0;
  530. else {
  531. if ((data & 0x1f) == 0x1f)
  532. arg = 1;
  533. else if ((data & 0x1f) == 0x10)
  534. arg = 0;
  535. else
  536. return -EINVAL;
  537. }
  538. break;
  539. default:
  540. return -ENOTSUPP;
  541. }
  542. goto out;
  543. }
  544. switch (param) {
  545. case PIN_CONFIG_BIAS_PULL_DOWN:
  546. ret = regmap_read(pctl->regmap,
  547. pctl->data->reg_pulldn,
  548. &data);
  549. data &= BIT(pin);
  550. if (ret < 0)
  551. return ret;
  552. if (!ret)
  553. return -EINVAL;
  554. arg = 1;
  555. break;
  556. case PIN_CONFIG_BIAS_PULL_UP:
  557. ret = regmap_read(pctl->regmap,
  558. pctl->data->reg_pullup,
  559. &data);
  560. data &= BIT(pin);
  561. if (ret < 0)
  562. return ret;
  563. if (!ret)
  564. return -EINVAL;
  565. arg = 1;
  566. break;
  567. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  568. if (pctl->data->model != SX150X_789)
  569. return -ENOTSUPP;
  570. ret = regmap_read(pctl->regmap,
  571. pctl->data->pri.x789.reg_drain,
  572. &data);
  573. data &= BIT(pin);
  574. if (ret < 0)
  575. return ret;
  576. if (!data)
  577. return -EINVAL;
  578. arg = 1;
  579. break;
  580. case PIN_CONFIG_DRIVE_PUSH_PULL:
  581. if (pctl->data->model != SX150X_789)
  582. arg = true;
  583. else {
  584. ret = regmap_read(pctl->regmap,
  585. pctl->data->pri.x789.reg_drain,
  586. &data);
  587. data &= BIT(pin);
  588. if (ret < 0)
  589. return ret;
  590. if (data)
  591. return -EINVAL;
  592. arg = 1;
  593. }
  594. break;
  595. case PIN_CONFIG_OUTPUT:
  596. ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
  597. if (ret < 0)
  598. return ret;
  599. if (ret == GPIO_LINE_DIRECTION_IN)
  600. return -EINVAL;
  601. ret = sx150x_gpio_get(&pctl->gpio, pin);
  602. if (ret < 0)
  603. return ret;
  604. arg = ret;
  605. break;
  606. default:
  607. return -ENOTSUPP;
  608. }
  609. out:
  610. *config = pinconf_to_config_packed(param, arg);
  611. return 0;
  612. }
  613. static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  614. unsigned long *configs, unsigned int num_configs)
  615. {
  616. struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  617. enum pin_config_param param;
  618. u32 arg;
  619. int i;
  620. int ret;
  621. for (i = 0; i < num_configs; i++) {
  622. param = pinconf_to_config_param(configs[i]);
  623. arg = pinconf_to_config_argument(configs[i]);
  624. if (sx150x_pin_is_oscio(pctl, pin)) {
  625. if (param == PIN_CONFIG_OUTPUT) {
  626. ret = sx150x_gpio_direction_output(&pctl->gpio,
  627. pin, arg);
  628. if (ret < 0)
  629. return ret;
  630. continue;
  631. } else
  632. return -ENOTSUPP;
  633. }
  634. switch (param) {
  635. case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
  636. case PIN_CONFIG_BIAS_DISABLE:
  637. ret = regmap_write_bits(pctl->regmap,
  638. pctl->data->reg_pulldn,
  639. BIT(pin), 0);
  640. if (ret < 0)
  641. return ret;
  642. ret = regmap_write_bits(pctl->regmap,
  643. pctl->data->reg_pullup,
  644. BIT(pin), 0);
  645. if (ret < 0)
  646. return ret;
  647. break;
  648. case PIN_CONFIG_BIAS_PULL_UP:
  649. ret = regmap_write_bits(pctl->regmap,
  650. pctl->data->reg_pullup,
  651. BIT(pin), BIT(pin));
  652. if (ret < 0)
  653. return ret;
  654. break;
  655. case PIN_CONFIG_BIAS_PULL_DOWN:
  656. ret = regmap_write_bits(pctl->regmap,
  657. pctl->data->reg_pulldn,
  658. BIT(pin), BIT(pin));
  659. if (ret < 0)
  660. return ret;
  661. break;
  662. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  663. if (pctl->data->model != SX150X_789 ||
  664. sx150x_pin_is_oscio(pctl, pin))
  665. return -ENOTSUPP;
  666. ret = regmap_write_bits(pctl->regmap,
  667. pctl->data->pri.x789.reg_drain,
  668. BIT(pin), BIT(pin));
  669. if (ret < 0)
  670. return ret;
  671. break;
  672. case PIN_CONFIG_DRIVE_PUSH_PULL:
  673. if (pctl->data->model != SX150X_789 ||
  674. sx150x_pin_is_oscio(pctl, pin))
  675. return 0;
  676. ret = regmap_write_bits(pctl->regmap,
  677. pctl->data->pri.x789.reg_drain,
  678. BIT(pin), 0);
  679. if (ret < 0)
  680. return ret;
  681. break;
  682. case PIN_CONFIG_OUTPUT:
  683. ret = sx150x_gpio_direction_output(&pctl->gpio,
  684. pin, arg);
  685. if (ret < 0)
  686. return ret;
  687. break;
  688. default:
  689. return -ENOTSUPP;
  690. }
  691. } /* for each config */
  692. return 0;
  693. }
  694. static const struct pinconf_ops sx150x_pinconf_ops = {
  695. .pin_config_get = sx150x_pinconf_get,
  696. .pin_config_set = sx150x_pinconf_set,
  697. .is_generic = true,
  698. };
  699. static const struct i2c_device_id sx150x_id[] = {
  700. {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
  701. {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
  702. {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
  703. {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
  704. {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
  705. {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
  706. {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
  707. {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
  708. {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
  709. {}
  710. };
  711. static const struct of_device_id sx150x_of_match[] = {
  712. { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
  713. { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
  714. { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
  715. { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
  716. { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
  717. { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
  718. { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
  719. { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
  720. { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
  721. {},
  722. };
  723. static int sx150x_reset(struct sx150x_pinctrl *pctl)
  724. {
  725. int err;
  726. err = i2c_smbus_write_byte_data(pctl->client,
  727. pctl->data->pri.x789.reg_reset,
  728. SX150X_789_RESET_KEY1);
  729. if (err < 0)
  730. return err;
  731. err = i2c_smbus_write_byte_data(pctl->client,
  732. pctl->data->pri.x789.reg_reset,
  733. SX150X_789_RESET_KEY2);
  734. return err;
  735. }
  736. static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
  737. {
  738. u8 reg, value;
  739. switch (pctl->data->model) {
  740. case SX150X_789:
  741. reg = pctl->data->pri.x789.reg_misc;
  742. value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
  743. break;
  744. case SX150X_456:
  745. reg = pctl->data->pri.x456.reg_advanced;
  746. value = 0x00;
  747. /*
  748. * Only SX1506 has RegAdvanced, SX1504/5 are expected
  749. * to initialize this offset to zero
  750. */
  751. if (!reg)
  752. return 0;
  753. break;
  754. case SX150X_123:
  755. reg = pctl->data->pri.x123.reg_advanced;
  756. value = 0x00;
  757. break;
  758. default:
  759. WARN(1, "Unknown chip model %d\n", pctl->data->model);
  760. return -EINVAL;
  761. }
  762. return regmap_write(pctl->regmap, reg, value);
  763. }
  764. static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
  765. {
  766. const u8 reg[] = {
  767. [SX150X_789] = pctl->data->pri.x789.reg_polarity,
  768. [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
  769. [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
  770. };
  771. int err;
  772. if (pctl->data->model == SX150X_789 &&
  773. of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
  774. err = sx150x_reset(pctl);
  775. if (err < 0)
  776. return err;
  777. }
  778. err = sx150x_init_misc(pctl);
  779. if (err < 0)
  780. return err;
  781. /* Set all pins to work in normal mode */
  782. return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
  783. }
  784. static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
  785. unsigned int reg)
  786. {
  787. const struct sx150x_device_data *data = pctl->data;
  788. if (reg == data->reg_sense) {
  789. /*
  790. * RegSense packs two bits of configuration per GPIO,
  791. * so we'd need to read twice as many bits as there
  792. * are GPIO in our chip
  793. */
  794. return 2 * data->ngpios;
  795. } else if ((data->model == SX150X_789 &&
  796. (reg == data->pri.x789.reg_misc ||
  797. reg == data->pri.x789.reg_clock ||
  798. reg == data->pri.x789.reg_reset))
  799. ||
  800. (data->model == SX150X_123 &&
  801. reg == data->pri.x123.reg_advanced)
  802. ||
  803. (data->model == SX150X_456 &&
  804. data->pri.x456.reg_advanced &&
  805. reg == data->pri.x456.reg_advanced)) {
  806. return 8;
  807. } else {
  808. return data->ngpios;
  809. }
  810. }
  811. static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
  812. unsigned int reg, unsigned int val)
  813. {
  814. unsigned int a, b;
  815. const struct sx150x_device_data *data = pctl->data;
  816. /*
  817. * Whereas SX1509 presents RegSense in a simple layout as such:
  818. * reg [ f f e e d d c c ]
  819. * reg + 1 [ b b a a 9 9 8 8 ]
  820. * reg + 2 [ 7 7 6 6 5 5 4 4 ]
  821. * reg + 3 [ 3 3 2 2 1 1 0 0 ]
  822. *
  823. * SX1503 and SX1506 deviate from that data layout, instead storing
  824. * their contents as follows:
  825. *
  826. * reg [ f f e e d d c c ]
  827. * reg + 1 [ 7 7 6 6 5 5 4 4 ]
  828. * reg + 2 [ b b a a 9 9 8 8 ]
  829. * reg + 3 [ 3 3 2 2 1 1 0 0 ]
  830. *
  831. * so, taking that into account, we swap two
  832. * inner bytes of a 4-byte result
  833. */
  834. if (reg == data->reg_sense &&
  835. data->ngpios == 16 &&
  836. (data->model == SX150X_123 ||
  837. data->model == SX150X_456)) {
  838. a = val & 0x00ff0000;
  839. b = val & 0x0000ff00;
  840. val &= 0xff0000ff;
  841. val |= b << 8;
  842. val |= a >> 8;
  843. }
  844. return val;
  845. }
  846. /*
  847. * In order to mask the differences between 16 and 8 bit expander
  848. * devices we set up a sligthly ficticious regmap that pretends to be
  849. * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
  850. * pair/quartet) registers and transparently reconstructs those
  851. * registers via multiple I2C/SMBus reads
  852. *
  853. * This way the rest of the driver code, interfacing with the chip via
  854. * regmap API, can work assuming that each GPIO pin is represented by
  855. * a group of bits at an offset proportional to GPIO number within a
  856. * given register.
  857. */
  858. static int sx150x_regmap_reg_read(void *context, unsigned int reg,
  859. unsigned int *result)
  860. {
  861. int ret, n;
  862. struct sx150x_pinctrl *pctl = context;
  863. struct i2c_client *i2c = pctl->client;
  864. const int width = sx150x_regmap_reg_width(pctl, reg);
  865. unsigned int idx, val;
  866. /*
  867. * There are four potential cases covered by this function:
  868. *
  869. * 1) 8-pin chip, single configuration bit register
  870. *
  871. * This is trivial the code below just needs to read:
  872. * reg [ 7 6 5 4 3 2 1 0 ]
  873. *
  874. * 2) 8-pin chip, double configuration bit register (RegSense)
  875. *
  876. * The read will be done as follows:
  877. * reg [ 7 7 6 6 5 5 4 4 ]
  878. * reg + 1 [ 3 3 2 2 1 1 0 0 ]
  879. *
  880. * 3) 16-pin chip, single configuration bit register
  881. *
  882. * The read will be done as follows:
  883. * reg [ f e d c b a 9 8 ]
  884. * reg + 1 [ 7 6 5 4 3 2 1 0 ]
  885. *
  886. * 4) 16-pin chip, double configuration bit register (RegSense)
  887. *
  888. * The read will be done as follows:
  889. * reg [ f f e e d d c c ]
  890. * reg + 1 [ b b a a 9 9 8 8 ]
  891. * reg + 2 [ 7 7 6 6 5 5 4 4 ]
  892. * reg + 3 [ 3 3 2 2 1 1 0 0 ]
  893. */
  894. for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
  895. val <<= 8;
  896. ret = i2c_smbus_read_byte_data(i2c, idx);
  897. if (ret < 0)
  898. return ret;
  899. val |= ret;
  900. }
  901. *result = sx150x_maybe_swizzle(pctl, reg, val);
  902. return 0;
  903. }
  904. static int sx150x_regmap_reg_write(void *context, unsigned int reg,
  905. unsigned int val)
  906. {
  907. int ret, n;
  908. struct sx150x_pinctrl *pctl = context;
  909. struct i2c_client *i2c = pctl->client;
  910. const int width = sx150x_regmap_reg_width(pctl, reg);
  911. val = sx150x_maybe_swizzle(pctl, reg, val);
  912. n = (width - 1) & ~7;
  913. do {
  914. const u8 byte = (val >> n) & 0xff;
  915. ret = i2c_smbus_write_byte_data(i2c, reg, byte);
  916. if (ret < 0)
  917. return ret;
  918. reg++;
  919. n -= 8;
  920. } while (n >= 0);
  921. return 0;
  922. }
  923. static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
  924. {
  925. struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
  926. return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
  927. }
  928. static const struct regmap_config sx150x_regmap_config = {
  929. .reg_bits = 8,
  930. .val_bits = 32,
  931. .cache_type = REGCACHE_RBTREE,
  932. .reg_read = sx150x_regmap_reg_read,
  933. .reg_write = sx150x_regmap_reg_write,
  934. .max_register = SX150X_MAX_REGISTER,
  935. .volatile_reg = sx150x_reg_volatile,
  936. };
  937. static int sx150x_probe(struct i2c_client *client,
  938. const struct i2c_device_id *id)
  939. {
  940. static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
  941. I2C_FUNC_SMBUS_WRITE_WORD_DATA;
  942. struct device *dev = &client->dev;
  943. struct sx150x_pinctrl *pctl;
  944. int ret;
  945. if (!i2c_check_functionality(client->adapter, i2c_funcs))
  946. return -ENOSYS;
  947. pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
  948. if (!pctl)
  949. return -ENOMEM;
  950. i2c_set_clientdata(client, pctl);
  951. pctl->dev = dev;
  952. pctl->client = client;
  953. if (dev->of_node)
  954. pctl->data = of_device_get_match_data(dev);
  955. else
  956. pctl->data = (struct sx150x_device_data *)id->driver_data;
  957. if (!pctl->data)
  958. return -EINVAL;
  959. pctl->regmap = devm_regmap_init(dev, NULL, pctl,
  960. &sx150x_regmap_config);
  961. if (IS_ERR(pctl->regmap)) {
  962. ret = PTR_ERR(pctl->regmap);
  963. dev_err(dev, "Failed to allocate register map: %d\n",
  964. ret);
  965. return ret;
  966. }
  967. mutex_init(&pctl->lock);
  968. ret = sx150x_init_hw(pctl);
  969. if (ret)
  970. return ret;
  971. /* Pinctrl_desc */
  972. pctl->pinctrl_desc.name = "sx150x-pinctrl";
  973. pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
  974. pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
  975. pctl->pinctrl_desc.pins = pctl->data->pins;
  976. pctl->pinctrl_desc.npins = pctl->data->npins;
  977. pctl->pinctrl_desc.owner = THIS_MODULE;
  978. ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
  979. pctl, &pctl->pctldev);
  980. if (ret) {
  981. dev_err(dev, "Failed to register pinctrl device\n");
  982. return ret;
  983. }
  984. /* Register GPIO controller */
  985. pctl->gpio.base = -1;
  986. pctl->gpio.ngpio = pctl->data->npins;
  987. pctl->gpio.get_direction = sx150x_gpio_get_direction;
  988. pctl->gpio.direction_input = sx150x_gpio_direction_input;
  989. pctl->gpio.direction_output = sx150x_gpio_direction_output;
  990. pctl->gpio.get = sx150x_gpio_get;
  991. pctl->gpio.set = sx150x_gpio_set;
  992. pctl->gpio.set_config = gpiochip_generic_config;
  993. pctl->gpio.parent = dev;
  994. #ifdef CONFIG_OF_GPIO
  995. pctl->gpio.of_node = dev->of_node;
  996. #endif
  997. pctl->gpio.can_sleep = true;
  998. pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
  999. if (!pctl->gpio.label)
  1000. return -ENOMEM;
  1001. /*
  1002. * Setting multiple pins is not safe when all pins are not
  1003. * handled by the same regmap register. The oscio pin (present
  1004. * on the SX150X_789 chips) lives in its own register, so
  1005. * would require locking that is not in place at this time.
  1006. */
  1007. if (pctl->data->model != SX150X_789)
  1008. pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
  1009. /* Add Interrupt support if an irq is specified */
  1010. if (client->irq > 0) {
  1011. struct gpio_irq_chip *girq;
  1012. pctl->irq_chip.irq_mask = sx150x_irq_mask;
  1013. pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
  1014. pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
  1015. pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
  1016. pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
  1017. pctl->irq_chip.name = devm_kstrdup(dev, client->name,
  1018. GFP_KERNEL);
  1019. if (!pctl->irq_chip.name)
  1020. return -ENOMEM;
  1021. pctl->irq.masked = ~0;
  1022. pctl->irq.sense = 0;
  1023. /*
  1024. * Because sx150x_irq_threaded_fn invokes all of the
  1025. * nested interrupt handlers via handle_nested_irq,
  1026. * any "handler" assigned to struct gpio_irq_chip
  1027. * below is going to be ignored, so the choice of the
  1028. * function does not matter that much.
  1029. *
  1030. * We set it to handle_bad_irq to avoid confusion,
  1031. * plus it will be instantly noticeable if it is ever
  1032. * called (should not happen)
  1033. */
  1034. girq = &pctl->gpio.irq;
  1035. girq->chip = &pctl->irq_chip;
  1036. /* This will let us handle the parent IRQ in the driver */
  1037. girq->parent_handler = NULL;
  1038. girq->num_parents = 0;
  1039. girq->parents = NULL;
  1040. girq->default_type = IRQ_TYPE_NONE;
  1041. girq->handler = handle_bad_irq;
  1042. girq->threaded = true;
  1043. ret = devm_request_threaded_irq(dev, client->irq, NULL,
  1044. sx150x_irq_thread_fn,
  1045. IRQF_ONESHOT | IRQF_SHARED |
  1046. IRQF_TRIGGER_FALLING,
  1047. pctl->irq_chip.name, pctl);
  1048. if (ret < 0)
  1049. return ret;
  1050. }
  1051. ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
  1052. if (ret)
  1053. return ret;
  1054. /*
  1055. * Pin control functions need to be enabled AFTER registering the
  1056. * GPIO chip because sx150x_pinconf_set() calls
  1057. * sx150x_gpio_direction_output().
  1058. */
  1059. ret = pinctrl_enable(pctl->pctldev);
  1060. if (ret) {
  1061. dev_err(dev, "Failed to enable pinctrl device\n");
  1062. return ret;
  1063. }
  1064. ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
  1065. 0, 0, pctl->data->npins);
  1066. if (ret)
  1067. return ret;
  1068. return 0;
  1069. }
  1070. static struct i2c_driver sx150x_driver = {
  1071. .driver = {
  1072. .name = "sx150x-pinctrl",
  1073. .of_match_table = of_match_ptr(sx150x_of_match),
  1074. },
  1075. .probe = sx150x_probe,
  1076. .id_table = sx150x_id,
  1077. };
  1078. static int __init sx150x_init(void)
  1079. {
  1080. return i2c_add_driver(&sx150x_driver);
  1081. }
  1082. subsys_initcall(sx150x_init);