pinctrl-ocelot.c 30 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi SoCs pinctrl driver
  4. *
  5. * Author: <alexandre.belloni@free-electrons.com>
  6. * License: Dual MIT/GPL
  7. * Copyright (c) 2017 Microsemi Corporation
  8. */
  9. #include <linux/gpio/driver.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/of_device.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/of_platform.h>
  15. #include <linux/pinctrl/pinctrl.h>
  16. #include <linux/pinctrl/pinmux.h>
  17. #include <linux/pinctrl/pinconf.h>
  18. #include <linux/pinctrl/pinconf-generic.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #include <linux/slab.h>
  22. #include "core.h"
  23. #include "pinconf.h"
  24. #include "pinmux.h"
  25. #define ocelot_clrsetbits(addr, clear, set) \
  26. writel((readl(addr) & ~(clear)) | (set), (addr))
  27. /* PINCONFIG bits (sparx5 only) */
  28. enum {
  29. PINCONF_BIAS,
  30. PINCONF_SCHMITT,
  31. PINCONF_DRIVE_STRENGTH,
  32. };
  33. #define BIAS_PD_BIT BIT(4)
  34. #define BIAS_PU_BIT BIT(3)
  35. #define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
  36. #define SCHMITT_BIT BIT(2)
  37. #define DRIVE_BITS GENMASK(1, 0)
  38. /* GPIO standard registers */
  39. #define OCELOT_GPIO_OUT_SET 0x0
  40. #define OCELOT_GPIO_OUT_CLR 0x4
  41. #define OCELOT_GPIO_OUT 0x8
  42. #define OCELOT_GPIO_IN 0xc
  43. #define OCELOT_GPIO_OE 0x10
  44. #define OCELOT_GPIO_INTR 0x14
  45. #define OCELOT_GPIO_INTR_ENA 0x18
  46. #define OCELOT_GPIO_INTR_IDENT 0x1c
  47. #define OCELOT_GPIO_ALT0 0x20
  48. #define OCELOT_GPIO_ALT1 0x24
  49. #define OCELOT_GPIO_SD_MAP 0x28
  50. #define OCELOT_FUNC_PER_PIN 4
  51. enum {
  52. FUNC_NONE,
  53. FUNC_GPIO,
  54. FUNC_IRQ0,
  55. FUNC_IRQ0_IN,
  56. FUNC_IRQ0_OUT,
  57. FUNC_IRQ1,
  58. FUNC_IRQ1_IN,
  59. FUNC_IRQ1_OUT,
  60. FUNC_EXT_IRQ,
  61. FUNC_MIIM,
  62. FUNC_PHY_LED,
  63. FUNC_PCI_WAKE,
  64. FUNC_MD,
  65. FUNC_PTP0,
  66. FUNC_PTP1,
  67. FUNC_PTP2,
  68. FUNC_PTP3,
  69. FUNC_PWM,
  70. FUNC_RECO_CLK,
  71. FUNC_SFP,
  72. FUNC_SG0,
  73. FUNC_SG1,
  74. FUNC_SG2,
  75. FUNC_SI,
  76. FUNC_SI2,
  77. FUNC_TACHO,
  78. FUNC_TWI,
  79. FUNC_TWI2,
  80. FUNC_TWI3,
  81. FUNC_TWI_SCL_M,
  82. FUNC_UART,
  83. FUNC_UART2,
  84. FUNC_UART3,
  85. FUNC_PLL_STAT,
  86. FUNC_EMMC,
  87. FUNC_REF_CLK,
  88. FUNC_RCVRD_CLK,
  89. FUNC_MAX
  90. };
  91. static const char *const ocelot_function_names[] = {
  92. [FUNC_NONE] = "none",
  93. [FUNC_GPIO] = "gpio",
  94. [FUNC_IRQ0] = "irq0",
  95. [FUNC_IRQ0_IN] = "irq0_in",
  96. [FUNC_IRQ0_OUT] = "irq0_out",
  97. [FUNC_IRQ1] = "irq1",
  98. [FUNC_IRQ1_IN] = "irq1_in",
  99. [FUNC_IRQ1_OUT] = "irq1_out",
  100. [FUNC_EXT_IRQ] = "ext_irq",
  101. [FUNC_MIIM] = "miim",
  102. [FUNC_PHY_LED] = "phy_led",
  103. [FUNC_PCI_WAKE] = "pci_wake",
  104. [FUNC_MD] = "md",
  105. [FUNC_PTP0] = "ptp0",
  106. [FUNC_PTP1] = "ptp1",
  107. [FUNC_PTP2] = "ptp2",
  108. [FUNC_PTP3] = "ptp3",
  109. [FUNC_PWM] = "pwm",
  110. [FUNC_RECO_CLK] = "reco_clk",
  111. [FUNC_SFP] = "sfp",
  112. [FUNC_SG0] = "sg0",
  113. [FUNC_SG1] = "sg1",
  114. [FUNC_SG2] = "sg2",
  115. [FUNC_SI] = "si",
  116. [FUNC_SI2] = "si2",
  117. [FUNC_TACHO] = "tacho",
  118. [FUNC_TWI] = "twi",
  119. [FUNC_TWI2] = "twi2",
  120. [FUNC_TWI3] = "twi3",
  121. [FUNC_TWI_SCL_M] = "twi_scl_m",
  122. [FUNC_UART] = "uart",
  123. [FUNC_UART2] = "uart2",
  124. [FUNC_UART3] = "uart3",
  125. [FUNC_PLL_STAT] = "pll_stat",
  126. [FUNC_EMMC] = "emmc",
  127. [FUNC_REF_CLK] = "ref_clk",
  128. [FUNC_RCVRD_CLK] = "rcvrd_clk",
  129. };
  130. struct ocelot_pmx_func {
  131. const char **groups;
  132. unsigned int ngroups;
  133. };
  134. struct ocelot_pin_caps {
  135. unsigned int pin;
  136. unsigned char functions[OCELOT_FUNC_PER_PIN];
  137. };
  138. struct ocelot_pinctrl {
  139. struct device *dev;
  140. struct pinctrl_dev *pctl;
  141. struct gpio_chip gpio_chip;
  142. struct regmap *map;
  143. void __iomem *pincfg;
  144. struct pinctrl_desc *desc;
  145. struct ocelot_pmx_func func[FUNC_MAX];
  146. u8 stride;
  147. };
  148. #define OCELOT_P(p, f0, f1, f2) \
  149. static struct ocelot_pin_caps ocelot_pin_##p = { \
  150. .pin = p, \
  151. .functions = { \
  152. FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
  153. }, \
  154. }
  155. OCELOT_P(0, SG0, NONE, NONE);
  156. OCELOT_P(1, SG0, NONE, NONE);
  157. OCELOT_P(2, SG0, NONE, NONE);
  158. OCELOT_P(3, SG0, NONE, NONE);
  159. OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
  160. OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
  161. OCELOT_P(6, UART, TWI_SCL_M, NONE);
  162. OCELOT_P(7, UART, TWI_SCL_M, NONE);
  163. OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
  164. OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
  165. OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
  166. OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
  167. OCELOT_P(12, UART2, TWI_SCL_M, SFP);
  168. OCELOT_P(13, UART2, TWI_SCL_M, SFP);
  169. OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
  170. OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
  171. OCELOT_P(16, TWI, NONE, SI);
  172. OCELOT_P(17, TWI, TWI_SCL_M, SI);
  173. OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
  174. OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
  175. OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
  176. OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
  177. #define OCELOT_PIN(n) { \
  178. .number = n, \
  179. .name = "GPIO_"#n, \
  180. .drv_data = &ocelot_pin_##n \
  181. }
  182. static const struct pinctrl_pin_desc ocelot_pins[] = {
  183. OCELOT_PIN(0),
  184. OCELOT_PIN(1),
  185. OCELOT_PIN(2),
  186. OCELOT_PIN(3),
  187. OCELOT_PIN(4),
  188. OCELOT_PIN(5),
  189. OCELOT_PIN(6),
  190. OCELOT_PIN(7),
  191. OCELOT_PIN(8),
  192. OCELOT_PIN(9),
  193. OCELOT_PIN(10),
  194. OCELOT_PIN(11),
  195. OCELOT_PIN(12),
  196. OCELOT_PIN(13),
  197. OCELOT_PIN(14),
  198. OCELOT_PIN(15),
  199. OCELOT_PIN(16),
  200. OCELOT_PIN(17),
  201. OCELOT_PIN(18),
  202. OCELOT_PIN(19),
  203. OCELOT_PIN(20),
  204. OCELOT_PIN(21),
  205. };
  206. #define JAGUAR2_P(p, f0, f1) \
  207. static struct ocelot_pin_caps jaguar2_pin_##p = { \
  208. .pin = p, \
  209. .functions = { \
  210. FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
  211. }, \
  212. }
  213. JAGUAR2_P(0, SG0, NONE);
  214. JAGUAR2_P(1, SG0, NONE);
  215. JAGUAR2_P(2, SG0, NONE);
  216. JAGUAR2_P(3, SG0, NONE);
  217. JAGUAR2_P(4, SG1, NONE);
  218. JAGUAR2_P(5, SG1, NONE);
  219. JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
  220. JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
  221. JAGUAR2_P(8, PTP0, NONE);
  222. JAGUAR2_P(9, PTP1, NONE);
  223. JAGUAR2_P(10, UART, NONE);
  224. JAGUAR2_P(11, UART, NONE);
  225. JAGUAR2_P(12, SG1, NONE);
  226. JAGUAR2_P(13, SG1, NONE);
  227. JAGUAR2_P(14, TWI, TWI_SCL_M);
  228. JAGUAR2_P(15, TWI, NONE);
  229. JAGUAR2_P(16, SI, TWI_SCL_M);
  230. JAGUAR2_P(17, SI, TWI_SCL_M);
  231. JAGUAR2_P(18, SI, TWI_SCL_M);
  232. JAGUAR2_P(19, PCI_WAKE, NONE);
  233. JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
  234. JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
  235. JAGUAR2_P(22, TACHO, NONE);
  236. JAGUAR2_P(23, PWM, NONE);
  237. JAGUAR2_P(24, UART2, NONE);
  238. JAGUAR2_P(25, UART2, SI);
  239. JAGUAR2_P(26, PTP2, SI);
  240. JAGUAR2_P(27, PTP3, SI);
  241. JAGUAR2_P(28, TWI2, SI);
  242. JAGUAR2_P(29, TWI2, SI);
  243. JAGUAR2_P(30, SG2, SI);
  244. JAGUAR2_P(31, SG2, SI);
  245. JAGUAR2_P(32, SG2, SI);
  246. JAGUAR2_P(33, SG2, SI);
  247. JAGUAR2_P(34, NONE, TWI_SCL_M);
  248. JAGUAR2_P(35, NONE, TWI_SCL_M);
  249. JAGUAR2_P(36, NONE, TWI_SCL_M);
  250. JAGUAR2_P(37, NONE, TWI_SCL_M);
  251. JAGUAR2_P(38, NONE, TWI_SCL_M);
  252. JAGUAR2_P(39, NONE, TWI_SCL_M);
  253. JAGUAR2_P(40, NONE, TWI_SCL_M);
  254. JAGUAR2_P(41, NONE, TWI_SCL_M);
  255. JAGUAR2_P(42, NONE, TWI_SCL_M);
  256. JAGUAR2_P(43, NONE, TWI_SCL_M);
  257. JAGUAR2_P(44, NONE, SFP);
  258. JAGUAR2_P(45, NONE, SFP);
  259. JAGUAR2_P(46, NONE, SFP);
  260. JAGUAR2_P(47, NONE, SFP);
  261. JAGUAR2_P(48, SFP, NONE);
  262. JAGUAR2_P(49, SFP, SI);
  263. JAGUAR2_P(50, SFP, SI);
  264. JAGUAR2_P(51, SFP, SI);
  265. JAGUAR2_P(52, SFP, NONE);
  266. JAGUAR2_P(53, SFP, NONE);
  267. JAGUAR2_P(54, SFP, NONE);
  268. JAGUAR2_P(55, SFP, NONE);
  269. JAGUAR2_P(56, MIIM, SFP);
  270. JAGUAR2_P(57, MIIM, SFP);
  271. JAGUAR2_P(58, MIIM, SFP);
  272. JAGUAR2_P(59, MIIM, SFP);
  273. JAGUAR2_P(60, NONE, NONE);
  274. JAGUAR2_P(61, NONE, NONE);
  275. JAGUAR2_P(62, NONE, NONE);
  276. JAGUAR2_P(63, NONE, NONE);
  277. #define JAGUAR2_PIN(n) { \
  278. .number = n, \
  279. .name = "GPIO_"#n, \
  280. .drv_data = &jaguar2_pin_##n \
  281. }
  282. static const struct pinctrl_pin_desc jaguar2_pins[] = {
  283. JAGUAR2_PIN(0),
  284. JAGUAR2_PIN(1),
  285. JAGUAR2_PIN(2),
  286. JAGUAR2_PIN(3),
  287. JAGUAR2_PIN(4),
  288. JAGUAR2_PIN(5),
  289. JAGUAR2_PIN(6),
  290. JAGUAR2_PIN(7),
  291. JAGUAR2_PIN(8),
  292. JAGUAR2_PIN(9),
  293. JAGUAR2_PIN(10),
  294. JAGUAR2_PIN(11),
  295. JAGUAR2_PIN(12),
  296. JAGUAR2_PIN(13),
  297. JAGUAR2_PIN(14),
  298. JAGUAR2_PIN(15),
  299. JAGUAR2_PIN(16),
  300. JAGUAR2_PIN(17),
  301. JAGUAR2_PIN(18),
  302. JAGUAR2_PIN(19),
  303. JAGUAR2_PIN(20),
  304. JAGUAR2_PIN(21),
  305. JAGUAR2_PIN(22),
  306. JAGUAR2_PIN(23),
  307. JAGUAR2_PIN(24),
  308. JAGUAR2_PIN(25),
  309. JAGUAR2_PIN(26),
  310. JAGUAR2_PIN(27),
  311. JAGUAR2_PIN(28),
  312. JAGUAR2_PIN(29),
  313. JAGUAR2_PIN(30),
  314. JAGUAR2_PIN(31),
  315. JAGUAR2_PIN(32),
  316. JAGUAR2_PIN(33),
  317. JAGUAR2_PIN(34),
  318. JAGUAR2_PIN(35),
  319. JAGUAR2_PIN(36),
  320. JAGUAR2_PIN(37),
  321. JAGUAR2_PIN(38),
  322. JAGUAR2_PIN(39),
  323. JAGUAR2_PIN(40),
  324. JAGUAR2_PIN(41),
  325. JAGUAR2_PIN(42),
  326. JAGUAR2_PIN(43),
  327. JAGUAR2_PIN(44),
  328. JAGUAR2_PIN(45),
  329. JAGUAR2_PIN(46),
  330. JAGUAR2_PIN(47),
  331. JAGUAR2_PIN(48),
  332. JAGUAR2_PIN(49),
  333. JAGUAR2_PIN(50),
  334. JAGUAR2_PIN(51),
  335. JAGUAR2_PIN(52),
  336. JAGUAR2_PIN(53),
  337. JAGUAR2_PIN(54),
  338. JAGUAR2_PIN(55),
  339. JAGUAR2_PIN(56),
  340. JAGUAR2_PIN(57),
  341. JAGUAR2_PIN(58),
  342. JAGUAR2_PIN(59),
  343. JAGUAR2_PIN(60),
  344. JAGUAR2_PIN(61),
  345. JAGUAR2_PIN(62),
  346. JAGUAR2_PIN(63),
  347. };
  348. #define SPARX5_P(p, f0, f1, f2) \
  349. static struct ocelot_pin_caps sparx5_pin_##p = { \
  350. .pin = p, \
  351. .functions = { \
  352. FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
  353. }, \
  354. }
  355. SPARX5_P(0, SG0, PLL_STAT, NONE);
  356. SPARX5_P(1, SG0, NONE, NONE);
  357. SPARX5_P(2, SG0, NONE, NONE);
  358. SPARX5_P(3, SG0, NONE, NONE);
  359. SPARX5_P(4, SG1, NONE, NONE);
  360. SPARX5_P(5, SG1, NONE, NONE);
  361. SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
  362. SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
  363. SPARX5_P(8, PTP0, NONE, SFP);
  364. SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
  365. SPARX5_P(10, UART, NONE, NONE);
  366. SPARX5_P(11, UART, NONE, NONE);
  367. SPARX5_P(12, SG1, NONE, NONE);
  368. SPARX5_P(13, SG1, NONE, NONE);
  369. SPARX5_P(14, TWI, TWI_SCL_M, NONE);
  370. SPARX5_P(15, TWI, NONE, NONE);
  371. SPARX5_P(16, SI, TWI_SCL_M, SFP);
  372. SPARX5_P(17, SI, TWI_SCL_M, SFP);
  373. SPARX5_P(18, SI, TWI_SCL_M, SFP);
  374. SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
  375. SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
  376. SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
  377. SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
  378. SPARX5_P(23, PWM, UART3, TWI_SCL_M);
  379. SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
  380. SPARX5_P(25, PTP3, SI, TWI_SCL_M);
  381. SPARX5_P(26, UART2, SI, TWI_SCL_M);
  382. SPARX5_P(27, UART2, SI, TWI_SCL_M);
  383. SPARX5_P(28, TWI2, SI, SFP);
  384. SPARX5_P(29, TWI2, SI, SFP);
  385. SPARX5_P(30, SG2, SI, PWM);
  386. SPARX5_P(31, SG2, SI, TWI_SCL_M);
  387. SPARX5_P(32, SG2, SI, TWI_SCL_M);
  388. SPARX5_P(33, SG2, SI, SFP);
  389. SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
  390. SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
  391. SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
  392. SPARX5_P(37, SFP, NONE, EMMC);
  393. SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
  394. SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
  395. SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
  396. SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
  397. SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
  398. SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
  399. SPARX5_P(44, SI, SFP, EMMC);
  400. SPARX5_P(45, SI, SFP, EMMC);
  401. SPARX5_P(46, NONE, SFP, EMMC);
  402. SPARX5_P(47, NONE, SFP, EMMC);
  403. SPARX5_P(48, TWI3, SI, SFP);
  404. SPARX5_P(49, TWI3, NONE, SFP);
  405. SPARX5_P(50, SFP, NONE, TWI_SCL_M);
  406. SPARX5_P(51, SFP, SI, TWI_SCL_M);
  407. SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
  408. SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
  409. SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
  410. SPARX5_P(55, SFP, PTP3, PCI_WAKE);
  411. SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
  412. SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
  413. SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
  414. SPARX5_P(59, MIIM, SFP, NONE);
  415. SPARX5_P(60, RECO_CLK, NONE, NONE);
  416. SPARX5_P(61, RECO_CLK, NONE, NONE);
  417. SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
  418. SPARX5_P(63, RECO_CLK, NONE, NONE);
  419. #define SPARX5_PIN(n) { \
  420. .number = n, \
  421. .name = "GPIO_"#n, \
  422. .drv_data = &sparx5_pin_##n \
  423. }
  424. static const struct pinctrl_pin_desc sparx5_pins[] = {
  425. SPARX5_PIN(0),
  426. SPARX5_PIN(1),
  427. SPARX5_PIN(2),
  428. SPARX5_PIN(3),
  429. SPARX5_PIN(4),
  430. SPARX5_PIN(5),
  431. SPARX5_PIN(6),
  432. SPARX5_PIN(7),
  433. SPARX5_PIN(8),
  434. SPARX5_PIN(9),
  435. SPARX5_PIN(10),
  436. SPARX5_PIN(11),
  437. SPARX5_PIN(12),
  438. SPARX5_PIN(13),
  439. SPARX5_PIN(14),
  440. SPARX5_PIN(15),
  441. SPARX5_PIN(16),
  442. SPARX5_PIN(17),
  443. SPARX5_PIN(18),
  444. SPARX5_PIN(19),
  445. SPARX5_PIN(20),
  446. SPARX5_PIN(21),
  447. SPARX5_PIN(22),
  448. SPARX5_PIN(23),
  449. SPARX5_PIN(24),
  450. SPARX5_PIN(25),
  451. SPARX5_PIN(26),
  452. SPARX5_PIN(27),
  453. SPARX5_PIN(28),
  454. SPARX5_PIN(29),
  455. SPARX5_PIN(30),
  456. SPARX5_PIN(31),
  457. SPARX5_PIN(32),
  458. SPARX5_PIN(33),
  459. SPARX5_PIN(34),
  460. SPARX5_PIN(35),
  461. SPARX5_PIN(36),
  462. SPARX5_PIN(37),
  463. SPARX5_PIN(38),
  464. SPARX5_PIN(39),
  465. SPARX5_PIN(40),
  466. SPARX5_PIN(41),
  467. SPARX5_PIN(42),
  468. SPARX5_PIN(43),
  469. SPARX5_PIN(44),
  470. SPARX5_PIN(45),
  471. SPARX5_PIN(46),
  472. SPARX5_PIN(47),
  473. SPARX5_PIN(48),
  474. SPARX5_PIN(49),
  475. SPARX5_PIN(50),
  476. SPARX5_PIN(51),
  477. SPARX5_PIN(52),
  478. SPARX5_PIN(53),
  479. SPARX5_PIN(54),
  480. SPARX5_PIN(55),
  481. SPARX5_PIN(56),
  482. SPARX5_PIN(57),
  483. SPARX5_PIN(58),
  484. SPARX5_PIN(59),
  485. SPARX5_PIN(60),
  486. SPARX5_PIN(61),
  487. SPARX5_PIN(62),
  488. SPARX5_PIN(63),
  489. };
  490. static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
  491. {
  492. return ARRAY_SIZE(ocelot_function_names);
  493. }
  494. static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
  495. unsigned int function)
  496. {
  497. return ocelot_function_names[function];
  498. }
  499. static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
  500. unsigned int function,
  501. const char *const **groups,
  502. unsigned *const num_groups)
  503. {
  504. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  505. *groups = info->func[function].groups;
  506. *num_groups = info->func[function].ngroups;
  507. return 0;
  508. }
  509. static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
  510. unsigned int pin, unsigned int function)
  511. {
  512. struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
  513. int i;
  514. for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
  515. if (function == p->functions[i])
  516. return i;
  517. }
  518. return -1;
  519. }
  520. #define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
  521. static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
  522. unsigned int selector, unsigned int group)
  523. {
  524. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  525. struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
  526. unsigned int p = pin->pin % 32;
  527. int f;
  528. f = ocelot_pin_function_idx(info, group, selector);
  529. if (f < 0)
  530. return -EINVAL;
  531. /*
  532. * f is encoded on two bits.
  533. * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
  534. * ALT[1]
  535. * This is racy because both registers can't be updated at the same time
  536. * but it doesn't matter much for now.
  537. * Note: ALT0/ALT1 are organized specially for 64 gpio targets
  538. */
  539. regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
  540. BIT(p), f << p);
  541. regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
  542. BIT(p), f << (p - 1));
  543. return 0;
  544. }
  545. #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
  546. static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
  547. struct pinctrl_gpio_range *range,
  548. unsigned int pin, bool input)
  549. {
  550. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  551. unsigned int p = pin % 32;
  552. regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
  553. input ? 0 : BIT(p));
  554. return 0;
  555. }
  556. static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
  557. struct pinctrl_gpio_range *range,
  558. unsigned int offset)
  559. {
  560. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  561. unsigned int p = offset % 32;
  562. regmap_update_bits(info->map, REG_ALT(0, info, offset),
  563. BIT(p), 0);
  564. regmap_update_bits(info->map, REG_ALT(1, info, offset),
  565. BIT(p), 0);
  566. return 0;
  567. }
  568. static const struct pinmux_ops ocelot_pmx_ops = {
  569. .get_functions_count = ocelot_get_functions_count,
  570. .get_function_name = ocelot_get_function_name,
  571. .get_function_groups = ocelot_get_function_groups,
  572. .set_mux = ocelot_pinmux_set_mux,
  573. .gpio_set_direction = ocelot_gpio_set_direction,
  574. .gpio_request_enable = ocelot_gpio_request_enable,
  575. };
  576. static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  577. {
  578. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  579. return info->desc->npins;
  580. }
  581. static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
  582. unsigned int group)
  583. {
  584. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  585. return info->desc->pins[group].name;
  586. }
  587. static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  588. unsigned int group,
  589. const unsigned int **pins,
  590. unsigned int *num_pins)
  591. {
  592. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  593. *pins = &info->desc->pins[group].number;
  594. *num_pins = 1;
  595. return 0;
  596. }
  597. static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
  598. unsigned int pin,
  599. unsigned int reg,
  600. int *val)
  601. {
  602. int ret = -EOPNOTSUPP;
  603. if (info->pincfg) {
  604. u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
  605. ret = 0;
  606. switch (reg) {
  607. case PINCONF_BIAS:
  608. *val = regcfg & BIAS_BITS;
  609. break;
  610. case PINCONF_SCHMITT:
  611. *val = regcfg & SCHMITT_BIT;
  612. break;
  613. case PINCONF_DRIVE_STRENGTH:
  614. *val = regcfg & DRIVE_BITS;
  615. break;
  616. default:
  617. ret = -EOPNOTSUPP;
  618. break;
  619. }
  620. }
  621. return ret;
  622. }
  623. static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
  624. unsigned int pin,
  625. unsigned int reg,
  626. int val)
  627. {
  628. int ret = -EOPNOTSUPP;
  629. if (info->pincfg) {
  630. void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
  631. ret = 0;
  632. switch (reg) {
  633. case PINCONF_BIAS:
  634. ocelot_clrsetbits(regaddr, BIAS_BITS, val);
  635. break;
  636. case PINCONF_SCHMITT:
  637. ocelot_clrsetbits(regaddr, SCHMITT_BIT, val);
  638. break;
  639. case PINCONF_DRIVE_STRENGTH:
  640. if (val <= 3)
  641. ocelot_clrsetbits(regaddr, DRIVE_BITS, val);
  642. else
  643. ret = -EINVAL;
  644. break;
  645. default:
  646. ret = -EOPNOTSUPP;
  647. break;
  648. }
  649. }
  650. return ret;
  651. }
  652. static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
  653. unsigned int pin, unsigned long *config)
  654. {
  655. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  656. u32 param = pinconf_to_config_param(*config);
  657. int val, err;
  658. switch (param) {
  659. case PIN_CONFIG_BIAS_DISABLE:
  660. case PIN_CONFIG_BIAS_PULL_UP:
  661. case PIN_CONFIG_BIAS_PULL_DOWN:
  662. err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
  663. if (err)
  664. return err;
  665. if (param == PIN_CONFIG_BIAS_DISABLE)
  666. val = (val == 0 ? true : false);
  667. else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
  668. val = (val & BIAS_PD_BIT ? true : false);
  669. else /* PIN_CONFIG_BIAS_PULL_UP */
  670. val = (val & BIAS_PU_BIT ? true : false);
  671. break;
  672. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  673. err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
  674. if (err)
  675. return err;
  676. val = (val & SCHMITT_BIT ? true : false);
  677. break;
  678. case PIN_CONFIG_DRIVE_STRENGTH:
  679. err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
  680. &val);
  681. if (err)
  682. return err;
  683. break;
  684. case PIN_CONFIG_OUTPUT:
  685. err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
  686. &val);
  687. if (err)
  688. return err;
  689. val = !!(val & BIT(pin % 32));
  690. break;
  691. case PIN_CONFIG_INPUT_ENABLE:
  692. case PIN_CONFIG_OUTPUT_ENABLE:
  693. err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
  694. &val);
  695. if (err)
  696. return err;
  697. val = val & BIT(pin % 32);
  698. if (param == PIN_CONFIG_OUTPUT_ENABLE)
  699. val = !!val;
  700. else
  701. val = !val;
  702. break;
  703. default:
  704. return -EOPNOTSUPP;
  705. }
  706. *config = pinconf_to_config_packed(param, val);
  707. return 0;
  708. }
  709. static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  710. unsigned long *configs, unsigned int num_configs)
  711. {
  712. struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
  713. u32 param, arg, p;
  714. int cfg, err = 0;
  715. for (cfg = 0; cfg < num_configs; cfg++) {
  716. param = pinconf_to_config_param(configs[cfg]);
  717. arg = pinconf_to_config_argument(configs[cfg]);
  718. switch (param) {
  719. case PIN_CONFIG_BIAS_DISABLE:
  720. case PIN_CONFIG_BIAS_PULL_UP:
  721. case PIN_CONFIG_BIAS_PULL_DOWN:
  722. arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
  723. (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
  724. BIAS_PD_BIT;
  725. err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
  726. if (err)
  727. goto err;
  728. break;
  729. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  730. arg = arg ? SCHMITT_BIT : 0;
  731. err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
  732. arg);
  733. if (err)
  734. goto err;
  735. break;
  736. case PIN_CONFIG_DRIVE_STRENGTH:
  737. err = ocelot_hw_set_value(info, pin,
  738. PINCONF_DRIVE_STRENGTH,
  739. arg);
  740. if (err)
  741. goto err;
  742. break;
  743. case PIN_CONFIG_OUTPUT_ENABLE:
  744. case PIN_CONFIG_INPUT_ENABLE:
  745. case PIN_CONFIG_OUTPUT:
  746. p = pin % 32;
  747. if (arg)
  748. regmap_write(info->map,
  749. REG(OCELOT_GPIO_OUT_SET, info,
  750. pin),
  751. BIT(p));
  752. else
  753. regmap_write(info->map,
  754. REG(OCELOT_GPIO_OUT_CLR, info,
  755. pin),
  756. BIT(p));
  757. regmap_update_bits(info->map,
  758. REG(OCELOT_GPIO_OE, info, pin),
  759. BIT(p),
  760. param == PIN_CONFIG_INPUT_ENABLE ?
  761. 0 : BIT(p));
  762. break;
  763. default:
  764. err = -EOPNOTSUPP;
  765. }
  766. }
  767. err:
  768. return err;
  769. }
  770. static const struct pinconf_ops ocelot_confops = {
  771. .is_generic = true,
  772. .pin_config_get = ocelot_pinconf_get,
  773. .pin_config_set = ocelot_pinconf_set,
  774. .pin_config_config_dbg_show = pinconf_generic_dump_config,
  775. };
  776. static const struct pinctrl_ops ocelot_pctl_ops = {
  777. .get_groups_count = ocelot_pctl_get_groups_count,
  778. .get_group_name = ocelot_pctl_get_group_name,
  779. .get_group_pins = ocelot_pctl_get_group_pins,
  780. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  781. .dt_free_map = pinconf_generic_dt_free_map,
  782. };
  783. static struct pinctrl_desc ocelot_desc = {
  784. .name = "ocelot-pinctrl",
  785. .pins = ocelot_pins,
  786. .npins = ARRAY_SIZE(ocelot_pins),
  787. .pctlops = &ocelot_pctl_ops,
  788. .pmxops = &ocelot_pmx_ops,
  789. .owner = THIS_MODULE,
  790. };
  791. static struct pinctrl_desc jaguar2_desc = {
  792. .name = "jaguar2-pinctrl",
  793. .pins = jaguar2_pins,
  794. .npins = ARRAY_SIZE(jaguar2_pins),
  795. .pctlops = &ocelot_pctl_ops,
  796. .pmxops = &ocelot_pmx_ops,
  797. .owner = THIS_MODULE,
  798. };
  799. static struct pinctrl_desc sparx5_desc = {
  800. .name = "sparx5-pinctrl",
  801. .pins = sparx5_pins,
  802. .npins = ARRAY_SIZE(sparx5_pins),
  803. .pctlops = &ocelot_pctl_ops,
  804. .pmxops = &ocelot_pmx_ops,
  805. .confops = &ocelot_confops,
  806. .owner = THIS_MODULE,
  807. };
  808. static int ocelot_create_group_func_map(struct device *dev,
  809. struct ocelot_pinctrl *info)
  810. {
  811. int f, npins, i;
  812. u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
  813. if (!pins)
  814. return -ENOMEM;
  815. for (f = 0; f < FUNC_MAX; f++) {
  816. for (npins = 0, i = 0; i < info->desc->npins; i++) {
  817. if (ocelot_pin_function_idx(info, i, f) >= 0)
  818. pins[npins++] = i;
  819. }
  820. if (!npins)
  821. continue;
  822. info->func[f].ngroups = npins;
  823. info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
  824. GFP_KERNEL);
  825. if (!info->func[f].groups) {
  826. kfree(pins);
  827. return -ENOMEM;
  828. }
  829. for (i = 0; i < npins; i++)
  830. info->func[f].groups[i] =
  831. info->desc->pins[pins[i]].name;
  832. }
  833. kfree(pins);
  834. return 0;
  835. }
  836. static int ocelot_pinctrl_register(struct platform_device *pdev,
  837. struct ocelot_pinctrl *info)
  838. {
  839. int ret;
  840. ret = ocelot_create_group_func_map(&pdev->dev, info);
  841. if (ret) {
  842. dev_err(&pdev->dev, "Unable to create group func map.\n");
  843. return ret;
  844. }
  845. info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
  846. if (IS_ERR(info->pctl)) {
  847. dev_err(&pdev->dev, "Failed to register pinctrl\n");
  848. return PTR_ERR(info->pctl);
  849. }
  850. return 0;
  851. }
  852. static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
  853. {
  854. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  855. unsigned int val;
  856. regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
  857. return !!(val & BIT(offset % 32));
  858. }
  859. static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
  860. int value)
  861. {
  862. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  863. if (value)
  864. regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
  865. BIT(offset % 32));
  866. else
  867. regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
  868. BIT(offset % 32));
  869. }
  870. static int ocelot_gpio_get_direction(struct gpio_chip *chip,
  871. unsigned int offset)
  872. {
  873. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  874. unsigned int val;
  875. regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
  876. if (val & BIT(offset % 32))
  877. return GPIO_LINE_DIRECTION_OUT;
  878. return GPIO_LINE_DIRECTION_IN;
  879. }
  880. static int ocelot_gpio_direction_input(struct gpio_chip *chip,
  881. unsigned int offset)
  882. {
  883. return pinctrl_gpio_direction_input(chip->base + offset);
  884. }
  885. static int ocelot_gpio_direction_output(struct gpio_chip *chip,
  886. unsigned int offset, int value)
  887. {
  888. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  889. unsigned int pin = BIT(offset % 32);
  890. if (value)
  891. regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
  892. pin);
  893. else
  894. regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
  895. pin);
  896. return pinctrl_gpio_direction_output(chip->base + offset);
  897. }
  898. static const struct gpio_chip ocelot_gpiolib_chip = {
  899. .request = gpiochip_generic_request,
  900. .free = gpiochip_generic_free,
  901. .set = ocelot_gpio_set,
  902. .get = ocelot_gpio_get,
  903. .get_direction = ocelot_gpio_get_direction,
  904. .direction_input = ocelot_gpio_direction_input,
  905. .direction_output = ocelot_gpio_direction_output,
  906. .owner = THIS_MODULE,
  907. };
  908. static void ocelot_irq_mask(struct irq_data *data)
  909. {
  910. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  911. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  912. unsigned int gpio = irqd_to_hwirq(data);
  913. regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
  914. BIT(gpio % 32), 0);
  915. }
  916. static void ocelot_irq_unmask(struct irq_data *data)
  917. {
  918. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  919. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  920. unsigned int gpio = irqd_to_hwirq(data);
  921. regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
  922. BIT(gpio % 32), BIT(gpio % 32));
  923. }
  924. static void ocelot_irq_ack(struct irq_data *data)
  925. {
  926. struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
  927. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  928. unsigned int gpio = irqd_to_hwirq(data);
  929. regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
  930. BIT(gpio % 32), BIT(gpio % 32));
  931. }
  932. static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
  933. static struct irq_chip ocelot_eoi_irqchip = {
  934. .name = "gpio",
  935. .irq_mask = ocelot_irq_mask,
  936. .irq_eoi = ocelot_irq_ack,
  937. .irq_unmask = ocelot_irq_unmask,
  938. .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
  939. .irq_set_type = ocelot_irq_set_type,
  940. };
  941. static struct irq_chip ocelot_irqchip = {
  942. .name = "gpio",
  943. .irq_mask = ocelot_irq_mask,
  944. .irq_ack = ocelot_irq_ack,
  945. .irq_unmask = ocelot_irq_unmask,
  946. .irq_set_type = ocelot_irq_set_type,
  947. };
  948. static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
  949. {
  950. type &= IRQ_TYPE_SENSE_MASK;
  951. if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
  952. return -EINVAL;
  953. if (type & IRQ_TYPE_LEVEL_HIGH)
  954. irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
  955. handle_fasteoi_irq, NULL);
  956. if (type & IRQ_TYPE_EDGE_BOTH)
  957. irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
  958. handle_edge_irq, NULL);
  959. return 0;
  960. }
  961. static void ocelot_irq_handler(struct irq_desc *desc)
  962. {
  963. struct irq_chip *parent_chip = irq_desc_get_chip(desc);
  964. struct gpio_chip *chip = irq_desc_get_handler_data(desc);
  965. struct ocelot_pinctrl *info = gpiochip_get_data(chip);
  966. unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
  967. unsigned int reg = 0, irq, i;
  968. unsigned long irqs;
  969. for (i = 0; i < info->stride; i++) {
  970. regmap_read(info->map, id_reg + 4 * i, &reg);
  971. if (!reg)
  972. continue;
  973. chained_irq_enter(parent_chip, desc);
  974. irqs = reg;
  975. for_each_set_bit(irq, &irqs,
  976. min(32U, info->desc->npins - 32 * i))
  977. generic_handle_irq(irq_linear_revmap(chip->irq.domain,
  978. irq + 32 * i));
  979. chained_irq_exit(parent_chip, desc);
  980. }
  981. }
  982. static int ocelot_gpiochip_register(struct platform_device *pdev,
  983. struct ocelot_pinctrl *info)
  984. {
  985. struct gpio_chip *gc;
  986. struct gpio_irq_chip *girq;
  987. int irq;
  988. info->gpio_chip = ocelot_gpiolib_chip;
  989. gc = &info->gpio_chip;
  990. gc->ngpio = info->desc->npins;
  991. gc->parent = &pdev->dev;
  992. gc->base = 0;
  993. gc->of_node = info->dev->of_node;
  994. gc->label = "ocelot-gpio";
  995. irq = irq_of_parse_and_map(gc->of_node, 0);
  996. if (irq) {
  997. girq = &gc->irq;
  998. girq->chip = &ocelot_irqchip;
  999. girq->parent_handler = ocelot_irq_handler;
  1000. girq->num_parents = 1;
  1001. girq->parents = devm_kcalloc(&pdev->dev, 1,
  1002. sizeof(*girq->parents),
  1003. GFP_KERNEL);
  1004. if (!girq->parents)
  1005. return -ENOMEM;
  1006. girq->parents[0] = irq;
  1007. girq->default_type = IRQ_TYPE_NONE;
  1008. girq->handler = handle_edge_irq;
  1009. }
  1010. return devm_gpiochip_add_data(&pdev->dev, gc, info);
  1011. }
  1012. static const struct of_device_id ocelot_pinctrl_of_match[] = {
  1013. { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
  1014. { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
  1015. { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
  1016. {},
  1017. };
  1018. static int ocelot_pinctrl_probe(struct platform_device *pdev)
  1019. {
  1020. struct device *dev = &pdev->dev;
  1021. struct ocelot_pinctrl *info;
  1022. void __iomem *base;
  1023. struct resource *res;
  1024. int ret;
  1025. struct regmap_config regmap_config = {
  1026. .reg_bits = 32,
  1027. .val_bits = 32,
  1028. .reg_stride = 4,
  1029. };
  1030. info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
  1031. if (!info)
  1032. return -ENOMEM;
  1033. info->desc = (struct pinctrl_desc *)device_get_match_data(dev);
  1034. base = devm_ioremap_resource(dev,
  1035. platform_get_resource(pdev, IORESOURCE_MEM, 0));
  1036. if (IS_ERR(base)) {
  1037. dev_err(dev, "Failed to ioremap registers\n");
  1038. return PTR_ERR(base);
  1039. }
  1040. info->stride = 1 + (info->desc->npins - 1) / 32;
  1041. regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
  1042. info->map = devm_regmap_init_mmio(dev, base, &regmap_config);
  1043. if (IS_ERR(info->map)) {
  1044. dev_err(dev, "Failed to create regmap\n");
  1045. return PTR_ERR(info->map);
  1046. }
  1047. dev_set_drvdata(dev, info->map);
  1048. info->dev = dev;
  1049. /* Pinconf registers */
  1050. if (info->desc->confops) {
  1051. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1052. base = devm_ioremap_resource(dev, res);
  1053. if (IS_ERR(base))
  1054. dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
  1055. else
  1056. info->pincfg = base;
  1057. }
  1058. ret = ocelot_pinctrl_register(pdev, info);
  1059. if (ret)
  1060. return ret;
  1061. ret = ocelot_gpiochip_register(pdev, info);
  1062. if (ret)
  1063. return ret;
  1064. dev_info(dev, "driver registered\n");
  1065. return 0;
  1066. }
  1067. static struct platform_driver ocelot_pinctrl_driver = {
  1068. .driver = {
  1069. .name = "pinctrl-ocelot",
  1070. .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
  1071. .suppress_bind_attrs = true,
  1072. },
  1073. .probe = ocelot_pinctrl_probe,
  1074. };
  1075. builtin_platform_driver(ocelot_pinctrl_driver);