pinctrl-lpc18xx.c 42 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380
  1. /*
  2. * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
  3. *
  4. * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/clk.h>
  12. #include <linux/io.h>
  13. #include <linux/init.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/pinctrl/pinctrl.h>
  17. #include <linux/pinctrl/pinmux.h>
  18. #include <linux/pinctrl/pinconf-generic.h>
  19. #include "core.h"
  20. #include "pinctrl-utils.h"
  21. /* LPC18XX SCU analog function registers */
  22. #define LPC18XX_SCU_REG_ENAIO0 0xc88
  23. #define LPC18XX_SCU_REG_ENAIO1 0xc8c
  24. #define LPC18XX_SCU_REG_ENAIO2 0xc90
  25. #define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0)
  26. /* LPC18XX SCU pin register definitions */
  27. #define LPC18XX_SCU_PIN_MODE_MASK 0x7
  28. #define LPC18XX_SCU_PIN_EPD BIT(3)
  29. #define LPC18XX_SCU_PIN_EPUN BIT(4)
  30. #define LPC18XX_SCU_PIN_EHS BIT(5)
  31. #define LPC18XX_SCU_PIN_EZI BIT(6)
  32. #define LPC18XX_SCU_PIN_ZIF BIT(7)
  33. #define LPC18XX_SCU_PIN_EHD_MASK 0x300
  34. #define LPC18XX_SCU_PIN_EHD_POS 8
  35. #define LPC18XX_SCU_USB1_EPD BIT(2)
  36. #define LPC18XX_SCU_USB1_EPWR BIT(4)
  37. #define LPC18XX_SCU_I2C0_EFP BIT(0)
  38. #define LPC18XX_SCU_I2C0_EHD BIT(2)
  39. #define LPC18XX_SCU_I2C0_EZI BIT(3)
  40. #define LPC18XX_SCU_I2C0_ZIF BIT(7)
  41. #define LPC18XX_SCU_I2C0_SCL_SHIFT 0
  42. #define LPC18XX_SCU_I2C0_SDA_SHIFT 8
  43. #define LPC18XX_SCU_FUNC_PER_PIN 8
  44. /* LPC18XX SCU pin interrupt select registers */
  45. #define LPC18XX_SCU_PINTSEL0 0xe00
  46. #define LPC18XX_SCU_PINTSEL1 0xe04
  47. #define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
  48. #define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
  49. #define LPC18XX_SCU_IRQ_PER_PINTSEL 4
  50. #define LPC18XX_GPIO_PINS_PER_PORT 32
  51. #define LPC18XX_GPIO_PIN_INT_MAX 8
  52. #define LPC18XX_SCU_PINTSEL_VAL(val, n) \
  53. ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
  54. /* LPC18xx pin types */
  55. enum {
  56. TYPE_ND, /* Normal-drive */
  57. TYPE_HD, /* High-drive */
  58. TYPE_HS, /* High-speed */
  59. TYPE_I2C0,
  60. TYPE_USB1,
  61. };
  62. /* LPC18xx pin functions */
  63. enum {
  64. FUNC_R, /* Reserved */
  65. FUNC_ADC,
  66. FUNC_ADCTRIG,
  67. FUNC_CAN0,
  68. FUNC_CAN1,
  69. FUNC_CGU_OUT,
  70. FUNC_CLKIN,
  71. FUNC_CLKOUT,
  72. FUNC_CTIN,
  73. FUNC_CTOUT,
  74. FUNC_DAC,
  75. FUNC_EMC,
  76. FUNC_EMC_ALT,
  77. FUNC_ENET,
  78. FUNC_ENET_ALT,
  79. FUNC_GPIO,
  80. FUNC_I2C0,
  81. FUNC_I2C1,
  82. FUNC_I2S0_RX_MCLK,
  83. FUNC_I2S0_RX_SCK,
  84. FUNC_I2S0_RX_SDA,
  85. FUNC_I2S0_RX_WS,
  86. FUNC_I2S0_TX_MCLK,
  87. FUNC_I2S0_TX_SCK,
  88. FUNC_I2S0_TX_SDA,
  89. FUNC_I2S0_TX_WS,
  90. FUNC_I2S1,
  91. FUNC_LCD,
  92. FUNC_LCD_ALT,
  93. FUNC_MCTRL,
  94. FUNC_NMI,
  95. FUNC_QEI,
  96. FUNC_SDMMC,
  97. FUNC_SGPIO,
  98. FUNC_SPI,
  99. FUNC_SPIFI,
  100. FUNC_SSP0,
  101. FUNC_SSP0_ALT,
  102. FUNC_SSP1,
  103. FUNC_TIMER0,
  104. FUNC_TIMER1,
  105. FUNC_TIMER2,
  106. FUNC_TIMER3,
  107. FUNC_TRACE,
  108. FUNC_UART0,
  109. FUNC_UART1,
  110. FUNC_UART2,
  111. FUNC_UART3,
  112. FUNC_USB0,
  113. FUNC_USB1,
  114. FUNC_MAX
  115. };
  116. static const char *const lpc18xx_function_names[] = {
  117. [FUNC_R] = "reserved",
  118. [FUNC_ADC] = "adc",
  119. [FUNC_ADCTRIG] = "adctrig",
  120. [FUNC_CAN0] = "can0",
  121. [FUNC_CAN1] = "can1",
  122. [FUNC_CGU_OUT] = "cgu_out",
  123. [FUNC_CLKIN] = "clkin",
  124. [FUNC_CLKOUT] = "clkout",
  125. [FUNC_CTIN] = "ctin",
  126. [FUNC_CTOUT] = "ctout",
  127. [FUNC_DAC] = "dac",
  128. [FUNC_EMC] = "emc",
  129. [FUNC_EMC_ALT] = "emc_alt",
  130. [FUNC_ENET] = "enet",
  131. [FUNC_ENET_ALT] = "enet_alt",
  132. [FUNC_GPIO] = "gpio",
  133. [FUNC_I2C0] = "i2c0",
  134. [FUNC_I2C1] = "i2c1",
  135. [FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk",
  136. [FUNC_I2S0_RX_SCK] = "i2s0_rx_sck",
  137. [FUNC_I2S0_RX_SDA] = "i2s0_rx_sda",
  138. [FUNC_I2S0_RX_WS] = "i2s0_rx_ws",
  139. [FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk",
  140. [FUNC_I2S0_TX_SCK] = "i2s0_tx_sck",
  141. [FUNC_I2S0_TX_SDA] = "i2s0_tx_sda",
  142. [FUNC_I2S0_TX_WS] = "i2s0_tx_ws",
  143. [FUNC_I2S1] = "i2s1",
  144. [FUNC_LCD] = "lcd",
  145. [FUNC_LCD_ALT] = "lcd_alt",
  146. [FUNC_MCTRL] = "mctrl",
  147. [FUNC_NMI] = "nmi",
  148. [FUNC_QEI] = "qei",
  149. [FUNC_SDMMC] = "sdmmc",
  150. [FUNC_SGPIO] = "sgpio",
  151. [FUNC_SPI] = "spi",
  152. [FUNC_SPIFI] = "spifi",
  153. [FUNC_SSP0] = "ssp0",
  154. [FUNC_SSP0_ALT] = "ssp0_alt",
  155. [FUNC_SSP1] = "ssp1",
  156. [FUNC_TIMER0] = "timer0",
  157. [FUNC_TIMER1] = "timer1",
  158. [FUNC_TIMER2] = "timer2",
  159. [FUNC_TIMER3] = "timer3",
  160. [FUNC_TRACE] = "trace",
  161. [FUNC_UART0] = "uart0",
  162. [FUNC_UART1] = "uart1",
  163. [FUNC_UART2] = "uart2",
  164. [FUNC_UART3] = "uart3",
  165. [FUNC_USB0] = "usb0",
  166. [FUNC_USB1] = "usb1",
  167. };
  168. struct lpc18xx_pmx_func {
  169. const char **groups;
  170. unsigned ngroups;
  171. };
  172. struct lpc18xx_scu_data {
  173. struct pinctrl_dev *pctl;
  174. void __iomem *base;
  175. struct clk *clk;
  176. struct lpc18xx_pmx_func func[FUNC_MAX];
  177. };
  178. struct lpc18xx_pin_caps {
  179. unsigned int offset;
  180. unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
  181. unsigned char analog;
  182. unsigned char type;
  183. };
  184. /* Analog pins are required to have both bias and input disabled */
  185. #define LPC18XX_SCU_ANALOG_PIN_CFG 0x10
  186. /* Macros to maniupluate analog member in lpc18xx_pin_caps */
  187. #define LPC18XX_ANALOG_PIN BIT(7)
  188. #define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3)
  189. #define LPC18XX_ANALOG_BIT_MASK 0x1f
  190. #define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5))
  191. #define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5))
  192. #define DAC LPC18XX_ANALOG_PIN
  193. #define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
  194. static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \
  195. .offset = 0x##port * 32 * 4 + pin * 4, \
  196. .functions = { \
  197. FUNC_##f0, FUNC_##f1, FUNC_##f2, \
  198. FUNC_##f3, FUNC_##f4, FUNC_##f5, \
  199. FUNC_##f6, FUNC_##f7, \
  200. }, \
  201. .analog = a, \
  202. .type = TYPE_##t, \
  203. }
  204. #define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
  205. static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \
  206. .offset = off, \
  207. .functions = { \
  208. FUNC_##f0, FUNC_##f1, FUNC_##f2, \
  209. FUNC_##f3, FUNC_##f4, FUNC_##f5, \
  210. FUNC_##f6, FUNC_##f7, \
  211. }, \
  212. .analog = a, \
  213. .type = TYPE_##t, \
  214. }
  215. /* Pinmuxing table taken from data sheet */
  216. /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
  217. LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
  218. LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
  219. LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
  220. LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
  221. LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
  222. LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
  223. LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
  224. LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
  225. LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
  226. LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
  227. LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
  228. LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
  229. LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
  230. LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
  231. LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
  232. LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
  233. LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
  234. LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
  235. LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
  236. LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
  237. LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
  238. LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
  239. LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
  240. LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
  241. LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND);
  242. LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
  243. LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
  244. LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
  245. LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD);
  246. LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
  247. LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND);
  248. LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND);
  249. LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND);
  250. LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
  251. LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
  252. LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND);
  253. LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND);
  254. LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
  255. LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
  256. LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
  257. LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
  258. LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND);
  259. LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND);
  260. LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
  261. LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
  262. LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
  263. LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND);
  264. LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND);
  265. LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND);
  266. LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND);
  267. LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND);
  268. LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
  269. LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
  270. LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND);
  271. LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
  272. LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
  273. LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND);
  274. LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  275. LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  276. LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  277. LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  278. LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  279. LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  280. LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  281. LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
  282. LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND);
  283. LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND);
  284. LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND);
  285. LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND);
  286. LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND);
  287. LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND);
  288. LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND);
  289. LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
  290. LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
  291. LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
  292. LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND);
  293. LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
  294. LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND);
  295. LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND);
  296. LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
  297. LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
  298. LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND);
  299. LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND);
  300. LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND);
  301. LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND);
  302. LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND);
  303. LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
  304. LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
  305. LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
  306. LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
  307. LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
  308. LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
  309. LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
  310. LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
  311. LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND);
  312. LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
  313. LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
  314. LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND);
  315. LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND);
  316. LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND);
  317. LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND);
  318. LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND);
  319. LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND);
  320. LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
  321. LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
  322. LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD);
  323. LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND);
  324. LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND);
  325. LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
  326. LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
  327. LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
  328. LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND);
  329. LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND);
  330. LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND);
  331. LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND);
  332. LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
  333. LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND);
  334. LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND);
  335. LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
  336. LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
  337. LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
  338. LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
  339. LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
  340. LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
  341. LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND);
  342. LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND);
  343. LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND);
  344. LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND);
  345. LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND);
  346. LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  347. LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND);
  348. LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  349. LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  350. LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  351. LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  352. LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  353. LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  354. LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  355. LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
  356. LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND);
  357. LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND);
  358. LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
  359. LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND);
  360. LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
  361. LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
  362. LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
  363. LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
  364. LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
  365. LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND);
  366. LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND);
  367. LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND);
  368. LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
  369. LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
  370. LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
  371. LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
  372. LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
  373. LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
  374. LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
  375. LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
  376. LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
  377. LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND);
  378. LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
  379. LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND);
  380. LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
  381. LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
  382. LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
  383. LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
  384. LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
  385. LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
  386. LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND);
  387. LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND);
  388. LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND);
  389. LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND);
  390. LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND);
  391. /* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
  392. LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS);
  393. LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
  394. LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
  395. LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
  396. LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
  397. LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
  398. LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
  399. LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
  400. #define LPC18XX_PIN_P(port, pin) { \
  401. .number = 0x##port * 32 + pin, \
  402. .name = "p"#port"_"#pin, \
  403. .drv_data = &lpc18xx_pin_p##port##_##pin \
  404. }
  405. /* Pin numbers for special pins */
  406. enum {
  407. PIN_CLK0 = 600,
  408. PIN_CLK1,
  409. PIN_CLK2,
  410. PIN_CLK3,
  411. PIN_USB1_DM,
  412. PIN_USB1_DP,
  413. PIN_I2C0_SCL,
  414. PIN_I2C0_SDA,
  415. };
  416. #define LPC18XX_PIN(pname, n) { \
  417. .number = n, \
  418. .name = #pname, \
  419. .drv_data = &lpc18xx_pin_##pname \
  420. }
  421. static const struct pinctrl_pin_desc lpc18xx_pins[] = {
  422. LPC18XX_PIN_P(0,0),
  423. LPC18XX_PIN_P(0,1),
  424. LPC18XX_PIN_P(1,0),
  425. LPC18XX_PIN_P(1,1),
  426. LPC18XX_PIN_P(1,2),
  427. LPC18XX_PIN_P(1,3),
  428. LPC18XX_PIN_P(1,4),
  429. LPC18XX_PIN_P(1,5),
  430. LPC18XX_PIN_P(1,6),
  431. LPC18XX_PIN_P(1,7),
  432. LPC18XX_PIN_P(1,8),
  433. LPC18XX_PIN_P(1,9),
  434. LPC18XX_PIN_P(1,10),
  435. LPC18XX_PIN_P(1,11),
  436. LPC18XX_PIN_P(1,12),
  437. LPC18XX_PIN_P(1,13),
  438. LPC18XX_PIN_P(1,14),
  439. LPC18XX_PIN_P(1,15),
  440. LPC18XX_PIN_P(1,16),
  441. LPC18XX_PIN_P(1,17),
  442. LPC18XX_PIN_P(1,18),
  443. LPC18XX_PIN_P(1,19),
  444. LPC18XX_PIN_P(1,20),
  445. LPC18XX_PIN_P(2,0),
  446. LPC18XX_PIN_P(2,1),
  447. LPC18XX_PIN_P(2,2),
  448. LPC18XX_PIN_P(2,3),
  449. LPC18XX_PIN_P(2,4),
  450. LPC18XX_PIN_P(2,5),
  451. LPC18XX_PIN_P(2,6),
  452. LPC18XX_PIN_P(2,7),
  453. LPC18XX_PIN_P(2,8),
  454. LPC18XX_PIN_P(2,9),
  455. LPC18XX_PIN_P(2,10),
  456. LPC18XX_PIN_P(2,11),
  457. LPC18XX_PIN_P(2,12),
  458. LPC18XX_PIN_P(2,13),
  459. LPC18XX_PIN_P(3,0),
  460. LPC18XX_PIN_P(3,1),
  461. LPC18XX_PIN_P(3,2),
  462. LPC18XX_PIN_P(3,3),
  463. LPC18XX_PIN_P(3,4),
  464. LPC18XX_PIN_P(3,5),
  465. LPC18XX_PIN_P(3,6),
  466. LPC18XX_PIN_P(3,7),
  467. LPC18XX_PIN_P(3,8),
  468. LPC18XX_PIN_P(4,0),
  469. LPC18XX_PIN_P(4,1),
  470. LPC18XX_PIN_P(4,2),
  471. LPC18XX_PIN_P(4,3),
  472. LPC18XX_PIN_P(4,4),
  473. LPC18XX_PIN_P(4,5),
  474. LPC18XX_PIN_P(4,6),
  475. LPC18XX_PIN_P(4,7),
  476. LPC18XX_PIN_P(4,8),
  477. LPC18XX_PIN_P(4,9),
  478. LPC18XX_PIN_P(4,10),
  479. LPC18XX_PIN_P(5,0),
  480. LPC18XX_PIN_P(5,1),
  481. LPC18XX_PIN_P(5,2),
  482. LPC18XX_PIN_P(5,3),
  483. LPC18XX_PIN_P(5,4),
  484. LPC18XX_PIN_P(5,5),
  485. LPC18XX_PIN_P(5,6),
  486. LPC18XX_PIN_P(5,7),
  487. LPC18XX_PIN_P(6,0),
  488. LPC18XX_PIN_P(6,1),
  489. LPC18XX_PIN_P(6,2),
  490. LPC18XX_PIN_P(6,3),
  491. LPC18XX_PIN_P(6,4),
  492. LPC18XX_PIN_P(6,5),
  493. LPC18XX_PIN_P(6,6),
  494. LPC18XX_PIN_P(6,7),
  495. LPC18XX_PIN_P(6,8),
  496. LPC18XX_PIN_P(6,9),
  497. LPC18XX_PIN_P(6,10),
  498. LPC18XX_PIN_P(6,11),
  499. LPC18XX_PIN_P(6,12),
  500. LPC18XX_PIN_P(7,0),
  501. LPC18XX_PIN_P(7,1),
  502. LPC18XX_PIN_P(7,2),
  503. LPC18XX_PIN_P(7,3),
  504. LPC18XX_PIN_P(7,4),
  505. LPC18XX_PIN_P(7,5),
  506. LPC18XX_PIN_P(7,6),
  507. LPC18XX_PIN_P(7,7),
  508. LPC18XX_PIN_P(8,0),
  509. LPC18XX_PIN_P(8,1),
  510. LPC18XX_PIN_P(8,2),
  511. LPC18XX_PIN_P(8,3),
  512. LPC18XX_PIN_P(8,4),
  513. LPC18XX_PIN_P(8,5),
  514. LPC18XX_PIN_P(8,6),
  515. LPC18XX_PIN_P(8,7),
  516. LPC18XX_PIN_P(8,8),
  517. LPC18XX_PIN_P(9,0),
  518. LPC18XX_PIN_P(9,1),
  519. LPC18XX_PIN_P(9,2),
  520. LPC18XX_PIN_P(9,3),
  521. LPC18XX_PIN_P(9,4),
  522. LPC18XX_PIN_P(9,5),
  523. LPC18XX_PIN_P(9,6),
  524. LPC18XX_PIN_P(a,0),
  525. LPC18XX_PIN_P(a,1),
  526. LPC18XX_PIN_P(a,2),
  527. LPC18XX_PIN_P(a,3),
  528. LPC18XX_PIN_P(a,4),
  529. LPC18XX_PIN_P(b,0),
  530. LPC18XX_PIN_P(b,1),
  531. LPC18XX_PIN_P(b,2),
  532. LPC18XX_PIN_P(b,3),
  533. LPC18XX_PIN_P(b,4),
  534. LPC18XX_PIN_P(b,5),
  535. LPC18XX_PIN_P(b,6),
  536. LPC18XX_PIN_P(c,0),
  537. LPC18XX_PIN_P(c,1),
  538. LPC18XX_PIN_P(c,2),
  539. LPC18XX_PIN_P(c,3),
  540. LPC18XX_PIN_P(c,4),
  541. LPC18XX_PIN_P(c,5),
  542. LPC18XX_PIN_P(c,6),
  543. LPC18XX_PIN_P(c,7),
  544. LPC18XX_PIN_P(c,8),
  545. LPC18XX_PIN_P(c,9),
  546. LPC18XX_PIN_P(c,10),
  547. LPC18XX_PIN_P(c,11),
  548. LPC18XX_PIN_P(c,12),
  549. LPC18XX_PIN_P(c,13),
  550. LPC18XX_PIN_P(c,14),
  551. LPC18XX_PIN_P(d,0),
  552. LPC18XX_PIN_P(d,1),
  553. LPC18XX_PIN_P(d,2),
  554. LPC18XX_PIN_P(d,3),
  555. LPC18XX_PIN_P(d,4),
  556. LPC18XX_PIN_P(d,5),
  557. LPC18XX_PIN_P(d,6),
  558. LPC18XX_PIN_P(d,7),
  559. LPC18XX_PIN_P(d,8),
  560. LPC18XX_PIN_P(d,9),
  561. LPC18XX_PIN_P(d,10),
  562. LPC18XX_PIN_P(d,11),
  563. LPC18XX_PIN_P(d,12),
  564. LPC18XX_PIN_P(d,13),
  565. LPC18XX_PIN_P(d,14),
  566. LPC18XX_PIN_P(d,15),
  567. LPC18XX_PIN_P(d,16),
  568. LPC18XX_PIN_P(e,0),
  569. LPC18XX_PIN_P(e,1),
  570. LPC18XX_PIN_P(e,2),
  571. LPC18XX_PIN_P(e,3),
  572. LPC18XX_PIN_P(e,4),
  573. LPC18XX_PIN_P(e,5),
  574. LPC18XX_PIN_P(e,6),
  575. LPC18XX_PIN_P(e,7),
  576. LPC18XX_PIN_P(e,8),
  577. LPC18XX_PIN_P(e,9),
  578. LPC18XX_PIN_P(e,10),
  579. LPC18XX_PIN_P(e,11),
  580. LPC18XX_PIN_P(e,12),
  581. LPC18XX_PIN_P(e,13),
  582. LPC18XX_PIN_P(e,14),
  583. LPC18XX_PIN_P(e,15),
  584. LPC18XX_PIN_P(f,0),
  585. LPC18XX_PIN_P(f,1),
  586. LPC18XX_PIN_P(f,2),
  587. LPC18XX_PIN_P(f,3),
  588. LPC18XX_PIN_P(f,4),
  589. LPC18XX_PIN_P(f,5),
  590. LPC18XX_PIN_P(f,6),
  591. LPC18XX_PIN_P(f,7),
  592. LPC18XX_PIN_P(f,8),
  593. LPC18XX_PIN_P(f,9),
  594. LPC18XX_PIN_P(f,10),
  595. LPC18XX_PIN_P(f,11),
  596. LPC18XX_PIN(clk0, PIN_CLK0),
  597. LPC18XX_PIN(clk1, PIN_CLK1),
  598. LPC18XX_PIN(clk2, PIN_CLK2),
  599. LPC18XX_PIN(clk3, PIN_CLK3),
  600. LPC18XX_PIN(usb1_dm, PIN_USB1_DM),
  601. LPC18XX_PIN(usb1_dp, PIN_USB1_DP),
  602. LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
  603. LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
  604. };
  605. /* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
  606. #define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
  607. static const struct pinconf_generic_params lpc18xx_params[] = {
  608. {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
  609. };
  610. #ifdef CONFIG_DEBUG_FS
  611. static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
  612. PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
  613. };
  614. #endif
  615. static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
  616. {
  617. switch (param) {
  618. case PIN_CONFIG_LOW_POWER_MODE:
  619. if (reg & LPC18XX_SCU_USB1_EPWR)
  620. *arg = 0;
  621. else
  622. *arg = 1;
  623. break;
  624. case PIN_CONFIG_BIAS_DISABLE:
  625. if (reg & LPC18XX_SCU_USB1_EPD)
  626. return -EINVAL;
  627. break;
  628. case PIN_CONFIG_BIAS_PULL_DOWN:
  629. if (reg & LPC18XX_SCU_USB1_EPD)
  630. *arg = 1;
  631. else
  632. return -EINVAL;
  633. break;
  634. default:
  635. return -ENOTSUPP;
  636. }
  637. return 0;
  638. }
  639. static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
  640. unsigned pin)
  641. {
  642. u8 shift;
  643. if (pin == PIN_I2C0_SCL)
  644. shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
  645. else
  646. shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
  647. switch (param) {
  648. case PIN_CONFIG_INPUT_ENABLE:
  649. if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
  650. *arg = 1;
  651. else
  652. return -EINVAL;
  653. break;
  654. case PIN_CONFIG_SLEW_RATE:
  655. if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
  656. *arg = 1;
  657. else
  658. *arg = 0;
  659. break;
  660. case PIN_CONFIG_INPUT_SCHMITT:
  661. if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
  662. *arg = 3;
  663. else
  664. *arg = 50;
  665. break;
  666. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  667. if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
  668. return -EINVAL;
  669. else
  670. *arg = 1;
  671. break;
  672. default:
  673. return -ENOTSUPP;
  674. }
  675. return 0;
  676. }
  677. static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
  678. {
  679. struct pinctrl_gpio_range *range;
  680. range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
  681. if (!range)
  682. return -EINVAL;
  683. return pin - range->pin_base + range->base;
  684. }
  685. static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
  686. {
  687. u32 reg_val;
  688. int i;
  689. reg_val = readl(addr);
  690. for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
  691. if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
  692. return 0;
  693. reg_val >>= BITS_PER_BYTE;
  694. *arg += 1;
  695. }
  696. return -EINVAL;
  697. }
  698. static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
  699. {
  700. unsigned int gpio_port, gpio_pin;
  701. gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
  702. gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
  703. return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
  704. }
  705. static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
  706. int *arg, unsigned pin)
  707. {
  708. struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
  709. int gpio, ret;
  710. u32 val;
  711. gpio = lpc18xx_pin_to_gpio(pctldev, pin);
  712. if (gpio < 0)
  713. return -ENOTSUPP;
  714. val = lpc18xx_gpio_to_pintsel_val(gpio);
  715. /*
  716. * Check if this pin has been enabled as a interrupt in any of the two
  717. * PINTSEL registers. *arg indicates which interrupt number (0-7).
  718. */
  719. *arg = 0;
  720. ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
  721. if (ret == 0)
  722. return ret;
  723. return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
  724. }
  725. static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
  726. int *arg, u32 reg, unsigned pin,
  727. struct lpc18xx_pin_caps *pin_cap)
  728. {
  729. switch (param) {
  730. case PIN_CONFIG_BIAS_DISABLE:
  731. if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
  732. ;
  733. else
  734. return -EINVAL;
  735. break;
  736. case PIN_CONFIG_BIAS_PULL_UP:
  737. if (reg & LPC18XX_SCU_PIN_EPUN)
  738. return -EINVAL;
  739. else
  740. *arg = 1;
  741. break;
  742. case PIN_CONFIG_BIAS_PULL_DOWN:
  743. if (reg & LPC18XX_SCU_PIN_EPD)
  744. *arg = 1;
  745. else
  746. return -EINVAL;
  747. break;
  748. case PIN_CONFIG_INPUT_ENABLE:
  749. if (reg & LPC18XX_SCU_PIN_EZI)
  750. *arg = 1;
  751. else
  752. return -EINVAL;
  753. break;
  754. case PIN_CONFIG_SLEW_RATE:
  755. if (pin_cap->type == TYPE_HD)
  756. return -ENOTSUPP;
  757. if (reg & LPC18XX_SCU_PIN_EHS)
  758. *arg = 1;
  759. else
  760. *arg = 0;
  761. break;
  762. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  763. if (reg & LPC18XX_SCU_PIN_ZIF)
  764. return -EINVAL;
  765. else
  766. *arg = 1;
  767. break;
  768. case PIN_CONFIG_DRIVE_STRENGTH:
  769. if (pin_cap->type != TYPE_HD)
  770. return -ENOTSUPP;
  771. *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
  772. switch (*arg) {
  773. case 3: *arg += 5;
  774. fallthrough;
  775. case 2: *arg += 5;
  776. fallthrough;
  777. case 1: *arg += 3;
  778. fallthrough;
  779. case 0: *arg += 4;
  780. }
  781. break;
  782. case PIN_CONFIG_GPIO_PIN_INT:
  783. return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
  784. default:
  785. return -ENOTSUPP;
  786. }
  787. return 0;
  788. }
  789. static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin)
  790. {
  791. int i;
  792. for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
  793. if (lpc18xx_pins[i].number == pin)
  794. return lpc18xx_pins[i].drv_data;
  795. }
  796. return NULL;
  797. }
  798. static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
  799. unsigned long *config)
  800. {
  801. struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
  802. enum pin_config_param param = pinconf_to_config_param(*config);
  803. struct lpc18xx_pin_caps *pin_cap;
  804. int ret, arg = 0;
  805. u32 reg;
  806. pin_cap = lpc18xx_get_pin_caps(pin);
  807. if (!pin_cap)
  808. return -EINVAL;
  809. reg = readl(scu->base + pin_cap->offset);
  810. if (pin_cap->type == TYPE_I2C0)
  811. ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
  812. else if (pin_cap->type == TYPE_USB1)
  813. ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
  814. else
  815. ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
  816. if (ret < 0)
  817. return ret;
  818. *config = pinconf_to_config_packed(param, (u16)arg);
  819. return 0;
  820. }
  821. static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
  822. enum pin_config_param param,
  823. u32 param_val, u32 *reg)
  824. {
  825. switch (param) {
  826. case PIN_CONFIG_LOW_POWER_MODE:
  827. if (param_val)
  828. *reg &= ~LPC18XX_SCU_USB1_EPWR;
  829. else
  830. *reg |= LPC18XX_SCU_USB1_EPWR;
  831. break;
  832. case PIN_CONFIG_BIAS_DISABLE:
  833. *reg &= ~LPC18XX_SCU_USB1_EPD;
  834. break;
  835. case PIN_CONFIG_BIAS_PULL_DOWN:
  836. *reg |= LPC18XX_SCU_USB1_EPD;
  837. break;
  838. default:
  839. dev_err(pctldev->dev, "Property not supported\n");
  840. return -ENOTSUPP;
  841. }
  842. return 0;
  843. }
  844. static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
  845. enum pin_config_param param,
  846. u32 param_val, u32 *reg,
  847. unsigned pin)
  848. {
  849. u8 shift;
  850. if (pin == PIN_I2C0_SCL)
  851. shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
  852. else
  853. shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
  854. switch (param) {
  855. case PIN_CONFIG_INPUT_ENABLE:
  856. if (param_val)
  857. *reg |= (LPC18XX_SCU_I2C0_EZI << shift);
  858. else
  859. *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
  860. break;
  861. case PIN_CONFIG_SLEW_RATE:
  862. if (param_val)
  863. *reg |= (LPC18XX_SCU_I2C0_EHD << shift);
  864. else
  865. *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
  866. break;
  867. case PIN_CONFIG_INPUT_SCHMITT:
  868. if (param_val == 3)
  869. *reg |= (LPC18XX_SCU_I2C0_EFP << shift);
  870. else if (param_val == 50)
  871. *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
  872. else
  873. return -ENOTSUPP;
  874. break;
  875. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  876. if (param_val)
  877. *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
  878. else
  879. *reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
  880. break;
  881. default:
  882. dev_err(pctldev->dev, "Property not supported\n");
  883. return -ENOTSUPP;
  884. }
  885. return 0;
  886. }
  887. static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
  888. u32 param_val, unsigned pin)
  889. {
  890. struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
  891. u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
  892. int gpio;
  893. if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
  894. return -EINVAL;
  895. gpio = lpc18xx_pin_to_gpio(pctldev, pin);
  896. if (gpio < 0)
  897. return -ENOTSUPP;
  898. val = lpc18xx_gpio_to_pintsel_val(gpio);
  899. reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
  900. reg_val = readl(scu->base + reg_offset);
  901. reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
  902. reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
  903. writel(reg_val, scu->base + reg_offset);
  904. return 0;
  905. }
  906. static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
  907. u32 param_val, u32 *reg, unsigned pin,
  908. struct lpc18xx_pin_caps *pin_cap)
  909. {
  910. switch (param) {
  911. case PIN_CONFIG_BIAS_DISABLE:
  912. *reg &= ~LPC18XX_SCU_PIN_EPD;
  913. *reg |= LPC18XX_SCU_PIN_EPUN;
  914. break;
  915. case PIN_CONFIG_BIAS_PULL_UP:
  916. *reg &= ~LPC18XX_SCU_PIN_EPUN;
  917. break;
  918. case PIN_CONFIG_BIAS_PULL_DOWN:
  919. *reg |= LPC18XX_SCU_PIN_EPD;
  920. break;
  921. case PIN_CONFIG_INPUT_ENABLE:
  922. if (param_val)
  923. *reg |= LPC18XX_SCU_PIN_EZI;
  924. else
  925. *reg &= ~LPC18XX_SCU_PIN_EZI;
  926. break;
  927. case PIN_CONFIG_SLEW_RATE:
  928. if (pin_cap->type == TYPE_HD) {
  929. dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
  930. return -ENOTSUPP;
  931. }
  932. if (param_val == 0)
  933. *reg &= ~LPC18XX_SCU_PIN_EHS;
  934. else
  935. *reg |= LPC18XX_SCU_PIN_EHS;
  936. break;
  937. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  938. if (param_val)
  939. *reg &= ~LPC18XX_SCU_PIN_ZIF;
  940. else
  941. *reg |= LPC18XX_SCU_PIN_ZIF;
  942. break;
  943. case PIN_CONFIG_DRIVE_STRENGTH:
  944. if (pin_cap->type != TYPE_HD) {
  945. dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
  946. return -ENOTSUPP;
  947. }
  948. *reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
  949. switch (param_val) {
  950. case 20: param_val -= 5;
  951. fallthrough;
  952. case 14: param_val -= 5;
  953. fallthrough;
  954. case 8: param_val -= 3;
  955. fallthrough;
  956. case 4: param_val -= 4;
  957. break;
  958. default:
  959. dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
  960. return -ENOTSUPP;
  961. }
  962. *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
  963. break;
  964. case PIN_CONFIG_GPIO_PIN_INT:
  965. return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
  966. default:
  967. dev_err(pctldev->dev, "Property not supported\n");
  968. return -ENOTSUPP;
  969. }
  970. return 0;
  971. }
  972. static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
  973. unsigned long *configs, unsigned num_configs)
  974. {
  975. struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
  976. struct lpc18xx_pin_caps *pin_cap;
  977. enum pin_config_param param;
  978. u32 param_val;
  979. u32 reg;
  980. int ret;
  981. int i;
  982. pin_cap = lpc18xx_get_pin_caps(pin);
  983. if (!pin_cap)
  984. return -EINVAL;
  985. reg = readl(scu->base + pin_cap->offset);
  986. for (i = 0; i < num_configs; i++) {
  987. param = pinconf_to_config_param(configs[i]);
  988. param_val = pinconf_to_config_argument(configs[i]);
  989. if (pin_cap->type == TYPE_I2C0)
  990. ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, &reg, pin);
  991. else if (pin_cap->type == TYPE_USB1)
  992. ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, &reg);
  993. else
  994. ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, &reg, pin, pin_cap);
  995. if (ret)
  996. return ret;
  997. }
  998. writel(reg, scu->base + pin_cap->offset);
  999. return 0;
  1000. }
  1001. static const struct pinconf_ops lpc18xx_pconf_ops = {
  1002. .is_generic = true,
  1003. .pin_config_get = lpc18xx_pconf_get,
  1004. .pin_config_set = lpc18xx_pconf_set,
  1005. };
  1006. static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
  1007. {
  1008. return ARRAY_SIZE(lpc18xx_function_names);
  1009. }
  1010. static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
  1011. unsigned function)
  1012. {
  1013. return lpc18xx_function_names[function];
  1014. }
  1015. static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
  1016. unsigned function,
  1017. const char *const **groups,
  1018. unsigned *const num_groups)
  1019. {
  1020. struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
  1021. *groups = scu->func[function].groups;
  1022. *num_groups = scu->func[function].ngroups;
  1023. return 0;
  1024. }
  1025. static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
  1026. unsigned group)
  1027. {
  1028. struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
  1029. struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
  1030. int func;
  1031. u32 reg;
  1032. /* Dedicated USB1 and I2C0 pins doesn't support muxing */
  1033. if (pin->type == TYPE_USB1) {
  1034. if (function == FUNC_USB1)
  1035. return 0;
  1036. goto fail;
  1037. }
  1038. if (pin->type == TYPE_I2C0) {
  1039. if (function == FUNC_I2C0)
  1040. return 0;
  1041. goto fail;
  1042. }
  1043. if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
  1044. u32 offset;
  1045. writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
  1046. if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
  1047. offset = LPC18XX_SCU_REG_ENAIO0;
  1048. else
  1049. offset = LPC18XX_SCU_REG_ENAIO1;
  1050. reg = readl(scu->base + offset);
  1051. reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
  1052. writel(reg, scu->base + offset);
  1053. return 0;
  1054. }
  1055. if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
  1056. writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
  1057. reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
  1058. reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
  1059. writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
  1060. return 0;
  1061. }
  1062. for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
  1063. if (function == pin->functions[func])
  1064. break;
  1065. }
  1066. if (func >= LPC18XX_SCU_FUNC_PER_PIN)
  1067. goto fail;
  1068. reg = readl(scu->base + pin->offset);
  1069. reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
  1070. writel(reg | func, scu->base + pin->offset);
  1071. return 0;
  1072. fail:
  1073. dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
  1074. lpc18xx_function_names[function]);
  1075. return -EINVAL;
  1076. }
  1077. static const struct pinmux_ops lpc18xx_pmx_ops = {
  1078. .get_functions_count = lpc18xx_pmx_get_funcs_count,
  1079. .get_function_name = lpc18xx_pmx_get_func_name,
  1080. .get_function_groups = lpc18xx_pmx_get_func_groups,
  1081. .set_mux = lpc18xx_pmx_set,
  1082. };
  1083. static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
  1084. {
  1085. return ARRAY_SIZE(lpc18xx_pins);
  1086. }
  1087. static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
  1088. unsigned group)
  1089. {
  1090. return lpc18xx_pins[group].name;
  1091. }
  1092. static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
  1093. unsigned group,
  1094. const unsigned **pins,
  1095. unsigned *num_pins)
  1096. {
  1097. *pins = &lpc18xx_pins[group].number;
  1098. *num_pins = 1;
  1099. return 0;
  1100. }
  1101. static const struct pinctrl_ops lpc18xx_pctl_ops = {
  1102. .get_groups_count = lpc18xx_pctl_get_groups_count,
  1103. .get_group_name = lpc18xx_pctl_get_group_name,
  1104. .get_group_pins = lpc18xx_pctl_get_group_pins,
  1105. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  1106. .dt_free_map = pinctrl_utils_free_map,
  1107. };
  1108. static struct pinctrl_desc lpc18xx_scu_desc = {
  1109. .name = "lpc18xx/43xx-scu",
  1110. .pins = lpc18xx_pins,
  1111. .npins = ARRAY_SIZE(lpc18xx_pins),
  1112. .pctlops = &lpc18xx_pctl_ops,
  1113. .pmxops = &lpc18xx_pmx_ops,
  1114. .confops = &lpc18xx_pconf_ops,
  1115. .num_custom_params = ARRAY_SIZE(lpc18xx_params),
  1116. .custom_params = lpc18xx_params,
  1117. #ifdef CONFIG_DEBUG_FS
  1118. .custom_conf_items = lpc18xx_conf_items,
  1119. #endif
  1120. .owner = THIS_MODULE,
  1121. };
  1122. static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function)
  1123. {
  1124. struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data;
  1125. int i;
  1126. if (function == FUNC_DAC && p->analog == DAC)
  1127. return true;
  1128. if (function == FUNC_ADC && p->analog)
  1129. return true;
  1130. if (function == FUNC_I2C0 && p->type == TYPE_I2C0)
  1131. return true;
  1132. if (function == FUNC_USB1 && p->type == TYPE_USB1)
  1133. return true;
  1134. for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) {
  1135. if (function == p->functions[i])
  1136. return true;
  1137. }
  1138. return false;
  1139. }
  1140. static int lpc18xx_create_group_func_map(struct device *dev,
  1141. struct lpc18xx_scu_data *scu)
  1142. {
  1143. u16 pins[ARRAY_SIZE(lpc18xx_pins)];
  1144. int func, ngroups, i;
  1145. for (func = 0; func < FUNC_MAX; func++) {
  1146. for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
  1147. if (lpc18xx_valid_pin_function(i, func))
  1148. pins[ngroups++] = i;
  1149. }
  1150. scu->func[func].ngroups = ngroups;
  1151. scu->func[func].groups = devm_kcalloc(dev,
  1152. ngroups, sizeof(char *),
  1153. GFP_KERNEL);
  1154. if (!scu->func[func].groups)
  1155. return -ENOMEM;
  1156. for (i = 0; i < ngroups; i++)
  1157. scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name;
  1158. }
  1159. return 0;
  1160. }
  1161. static int lpc18xx_scu_probe(struct platform_device *pdev)
  1162. {
  1163. struct lpc18xx_scu_data *scu;
  1164. int ret;
  1165. scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
  1166. if (!scu)
  1167. return -ENOMEM;
  1168. scu->base = devm_platform_ioremap_resource(pdev, 0);
  1169. if (IS_ERR(scu->base))
  1170. return PTR_ERR(scu->base);
  1171. scu->clk = devm_clk_get(&pdev->dev, NULL);
  1172. if (IS_ERR(scu->clk)) {
  1173. dev_err(&pdev->dev, "Input clock not found.\n");
  1174. return PTR_ERR(scu->clk);
  1175. }
  1176. ret = lpc18xx_create_group_func_map(&pdev->dev, scu);
  1177. if (ret) {
  1178. dev_err(&pdev->dev, "Unable to create group func map.\n");
  1179. return ret;
  1180. }
  1181. ret = clk_prepare_enable(scu->clk);
  1182. if (ret) {
  1183. dev_err(&pdev->dev, "Unable to enable clock.\n");
  1184. return ret;
  1185. }
  1186. platform_set_drvdata(pdev, scu);
  1187. scu->pctl = devm_pinctrl_register(&pdev->dev, &lpc18xx_scu_desc, scu);
  1188. if (IS_ERR(scu->pctl)) {
  1189. dev_err(&pdev->dev, "Could not register pinctrl driver\n");
  1190. clk_disable_unprepare(scu->clk);
  1191. return PTR_ERR(scu->pctl);
  1192. }
  1193. return 0;
  1194. }
  1195. static const struct of_device_id lpc18xx_scu_match[] = {
  1196. { .compatible = "nxp,lpc1850-scu" },
  1197. {},
  1198. };
  1199. static struct platform_driver lpc18xx_scu_driver = {
  1200. .probe = lpc18xx_scu_probe,
  1201. .driver = {
  1202. .name = "lpc18xx-scu",
  1203. .of_match_table = lpc18xx_scu_match,
  1204. .suppress_bind_attrs = true,
  1205. },
  1206. };
  1207. builtin_platform_driver(lpc18xx_scu_driver);