pinctrl-falcon.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/drivers/pinctrl/pinmux-falcon.c
  4. * based on linux/drivers/pinctrl/pinmux-pxa910.c
  5. *
  6. * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
  7. * Copyright (C) 2012 John Crispin <john@phrozen.org>
  8. */
  9. #include <linux/gpio/driver.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/slab.h>
  12. #include <linux/export.h>
  13. #include <linux/err.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_platform.h>
  17. #include <linux/of_address.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/platform_device.h>
  20. #include "pinctrl-lantiq.h"
  21. #include <lantiq_soc.h>
  22. /* Multiplexer Control Register */
  23. #define LTQ_PADC_MUX(x) (x * 0x4)
  24. /* Pull Up Enable Register */
  25. #define LTQ_PADC_PUEN 0x80
  26. /* Pull Down Enable Register */
  27. #define LTQ_PADC_PDEN 0x84
  28. /* Slew Rate Control Register */
  29. #define LTQ_PADC_SRC 0x88
  30. /* Drive Current Control Register */
  31. #define LTQ_PADC_DCC 0x8C
  32. /* Pad Control Availability Register */
  33. #define LTQ_PADC_AVAIL 0xF0
  34. #define pad_r32(p, reg) ltq_r32(p + reg)
  35. #define pad_w32(p, val, reg) ltq_w32(val, p + reg)
  36. #define pad_w32_mask(c, clear, set, reg) \
  37. pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
  38. #define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
  39. #define PORTS 5
  40. #define PINS 32
  41. #define PORT(x) (x / PINS)
  42. #define PORT_PIN(x) (x % PINS)
  43. #define MFP_FALCON(a, f0, f1, f2, f3) \
  44. { \
  45. .name = #a, \
  46. .pin = a, \
  47. .func = { \
  48. FALCON_MUX_##f0, \
  49. FALCON_MUX_##f1, \
  50. FALCON_MUX_##f2, \
  51. FALCON_MUX_##f3, \
  52. }, \
  53. }
  54. #define GRP_MUX(a, m, p) \
  55. { \
  56. .name = a, \
  57. .mux = FALCON_MUX_##m, \
  58. .pins = p, \
  59. .npins = ARRAY_SIZE(p), \
  60. }
  61. enum falcon_mux {
  62. FALCON_MUX_GPIO = 0,
  63. FALCON_MUX_RST,
  64. FALCON_MUX_NTR,
  65. FALCON_MUX_PPS,
  66. FALCON_MUX_MDIO,
  67. FALCON_MUX_LED,
  68. FALCON_MUX_SPI,
  69. FALCON_MUX_ASC,
  70. FALCON_MUX_I2C,
  71. FALCON_MUX_HOSTIF,
  72. FALCON_MUX_SLIC,
  73. FALCON_MUX_JTAG,
  74. FALCON_MUX_PCM,
  75. FALCON_MUX_MII,
  76. FALCON_MUX_PHY,
  77. FALCON_MUX_NONE = 0xffff,
  78. };
  79. static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
  80. static int pad_count[PORTS];
  81. static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
  82. {
  83. int base = bank * PINS;
  84. int i;
  85. for (i = 0; i < len; i++) {
  86. d[i].number = base + i;
  87. d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i);
  88. }
  89. pad_count[bank] = len;
  90. }
  91. static struct ltq_mfp_pin falcon_mfp[] = {
  92. /* pin f0 f1 f2 f3 */
  93. MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
  94. MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
  95. MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
  96. MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
  97. MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
  98. MFP_FALCON(GPIO5, NTR, GPIO, PPS, NONE),
  99. MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
  100. MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
  101. MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
  102. MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
  103. MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
  104. MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
  105. MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
  106. MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
  107. MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
  108. MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
  109. MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
  110. MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
  111. MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
  112. MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
  113. MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
  114. MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
  115. MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
  116. MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
  117. MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
  118. MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
  119. MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
  120. MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
  121. MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
  122. MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
  123. MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
  124. MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
  125. MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
  126. MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
  127. MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
  128. MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
  129. MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
  130. MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
  131. MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
  132. MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
  133. MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
  134. MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
  135. MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
  136. MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
  137. MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
  138. MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
  139. MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
  140. MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
  141. MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
  142. MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
  143. MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
  144. MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
  145. MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
  146. MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
  147. };
  148. static const unsigned pins_por[] = {GPIO0};
  149. static const unsigned pins_ntr[] = {GPIO4};
  150. static const unsigned pins_ntr8k[] = {GPIO5};
  151. static const unsigned pins_pps[] = {GPIO5};
  152. static const unsigned pins_hrst[] = {GPIO6};
  153. static const unsigned pins_mdio[] = {GPIO7, GPIO8};
  154. static const unsigned pins_bled[] = {GPIO9, GPIO10, GPIO11,
  155. GPIO12, GPIO13, GPIO14};
  156. static const unsigned pins_asc0[] = {GPIO32, GPIO33};
  157. static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
  158. static const unsigned pins_spi_cs0[] = {GPIO37};
  159. static const unsigned pins_spi_cs1[] = {GPIO38};
  160. static const unsigned pins_i2c[] = {GPIO39, GPIO40};
  161. static const unsigned pins_jtag[] = {GPIO41};
  162. static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
  163. static const unsigned pins_pcm[] = {GPIO44, GPIO45};
  164. static const unsigned pins_asc1[] = {GPIO44, GPIO45};
  165. static struct ltq_pin_group falcon_grps[] = {
  166. GRP_MUX("por", RST, pins_por),
  167. GRP_MUX("ntr", NTR, pins_ntr),
  168. GRP_MUX("ntr8k", NTR, pins_ntr8k),
  169. GRP_MUX("pps", PPS, pins_pps),
  170. GRP_MUX("hrst", RST, pins_hrst),
  171. GRP_MUX("mdio", MDIO, pins_mdio),
  172. GRP_MUX("bootled", LED, pins_bled),
  173. GRP_MUX("asc0", ASC, pins_asc0),
  174. GRP_MUX("spi", SPI, pins_spi),
  175. GRP_MUX("spi cs0", SPI, pins_spi_cs0),
  176. GRP_MUX("spi cs1", SPI, pins_spi_cs1),
  177. GRP_MUX("i2c", I2C, pins_i2c),
  178. GRP_MUX("jtag", JTAG, pins_jtag),
  179. GRP_MUX("slic", SLIC, pins_slic),
  180. GRP_MUX("pcm", PCM, pins_pcm),
  181. GRP_MUX("asc1", ASC, pins_asc1),
  182. };
  183. static const char * const ltq_rst_grps[] = {"por", "hrst"};
  184. static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k", "pps"};
  185. static const char * const ltq_mdio_grps[] = {"mdio"};
  186. static const char * const ltq_bled_grps[] = {"bootled"};
  187. static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
  188. static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
  189. static const char * const ltq_i2c_grps[] = {"i2c"};
  190. static const char * const ltq_jtag_grps[] = {"jtag"};
  191. static const char * const ltq_slic_grps[] = {"slic"};
  192. static const char * const ltq_pcm_grps[] = {"pcm"};
  193. static struct ltq_pmx_func falcon_funcs[] = {
  194. {"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
  195. {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
  196. {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
  197. {"led", ARRAY_AND_SIZE(ltq_bled_grps)},
  198. {"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
  199. {"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
  200. {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
  201. {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
  202. {"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
  203. {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
  204. };
  205. /* --------- pinconf related code --------- */
  206. static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
  207. unsigned group, unsigned long *config)
  208. {
  209. return -ENOTSUPP;
  210. }
  211. static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
  212. unsigned group, unsigned long *configs,
  213. unsigned num_configs)
  214. {
  215. return -ENOTSUPP;
  216. }
  217. static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
  218. unsigned pin, unsigned long *config)
  219. {
  220. struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
  221. enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
  222. void __iomem *mem = info->membase[PORT(pin)];
  223. switch (param) {
  224. case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
  225. *config = LTQ_PINCONF_PACK(param,
  226. !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
  227. break;
  228. case LTQ_PINCONF_PARAM_SLEW_RATE:
  229. *config = LTQ_PINCONF_PACK(param,
  230. !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
  231. break;
  232. case LTQ_PINCONF_PARAM_PULL:
  233. if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
  234. *config = LTQ_PINCONF_PACK(param, 1);
  235. else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
  236. *config = LTQ_PINCONF_PACK(param, 2);
  237. else
  238. *config = LTQ_PINCONF_PACK(param, 0);
  239. break;
  240. default:
  241. return -ENOTSUPP;
  242. }
  243. return 0;
  244. }
  245. static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
  246. unsigned pin, unsigned long *configs,
  247. unsigned num_configs)
  248. {
  249. enum ltq_pinconf_param param;
  250. int arg;
  251. struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
  252. void __iomem *mem = info->membase[PORT(pin)];
  253. u32 reg;
  254. int i;
  255. for (i = 0; i < num_configs; i++) {
  256. param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
  257. arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
  258. switch (param) {
  259. case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
  260. reg = LTQ_PADC_DCC;
  261. break;
  262. case LTQ_PINCONF_PARAM_SLEW_RATE:
  263. reg = LTQ_PADC_SRC;
  264. break;
  265. case LTQ_PINCONF_PARAM_PULL:
  266. if (arg == 1)
  267. reg = LTQ_PADC_PDEN;
  268. else
  269. reg = LTQ_PADC_PUEN;
  270. break;
  271. default:
  272. pr_err("%s: Invalid config param %04x\n",
  273. pinctrl_dev_get_name(pctrldev), param);
  274. return -ENOTSUPP;
  275. }
  276. pad_w32(mem, BIT(PORT_PIN(pin)), reg);
  277. if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
  278. return -ENOTSUPP;
  279. } /* for each config */
  280. return 0;
  281. }
  282. static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
  283. struct seq_file *s, unsigned offset)
  284. {
  285. unsigned long config;
  286. struct pin_desc *desc;
  287. struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
  288. int port = PORT(offset);
  289. seq_printf(s, " (port %d) mux %d -- ", port,
  290. pad_r32(info->membase[port], LTQ_PADC_MUX(PORT_PIN(offset))));
  291. config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_PULL, 0);
  292. if (!falcon_pinconf_get(pctrldev, offset, &config))
  293. seq_printf(s, "pull %d ",
  294. (int)LTQ_PINCONF_UNPACK_ARG(config));
  295. config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_DRIVE_CURRENT, 0);
  296. if (!falcon_pinconf_get(pctrldev, offset, &config))
  297. seq_printf(s, "drive-current %d ",
  298. (int)LTQ_PINCONF_UNPACK_ARG(config));
  299. config = LTQ_PINCONF_PACK(LTQ_PINCONF_PARAM_SLEW_RATE, 0);
  300. if (!falcon_pinconf_get(pctrldev, offset, &config))
  301. seq_printf(s, "slew-rate %d ",
  302. (int)LTQ_PINCONF_UNPACK_ARG(config));
  303. desc = pin_desc_get(pctrldev, offset);
  304. if (desc) {
  305. if (desc->gpio_owner)
  306. seq_printf(s, " owner: %s", desc->gpio_owner);
  307. } else {
  308. seq_printf(s, " not registered");
  309. }
  310. }
  311. static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
  312. struct seq_file *s, unsigned selector)
  313. {
  314. }
  315. static const struct pinconf_ops falcon_pinconf_ops = {
  316. .pin_config_get = falcon_pinconf_get,
  317. .pin_config_set = falcon_pinconf_set,
  318. .pin_config_group_get = falcon_pinconf_group_get,
  319. .pin_config_group_set = falcon_pinconf_group_set,
  320. .pin_config_dbg_show = falcon_pinconf_dbg_show,
  321. .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
  322. };
  323. static struct pinctrl_desc falcon_pctrl_desc = {
  324. .owner = THIS_MODULE,
  325. .pins = falcon_pads,
  326. .confops = &falcon_pinconf_ops,
  327. };
  328. static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
  329. int mfp, int mux)
  330. {
  331. struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
  332. int port = PORT(info->mfp[mfp].pin);
  333. if ((port >= PORTS) || (!info->membase[port]))
  334. return -ENODEV;
  335. pad_w32(info->membase[port], mux,
  336. LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
  337. return 0;
  338. }
  339. static const struct ltq_cfg_param falcon_cfg_params[] = {
  340. {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
  341. {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
  342. {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
  343. };
  344. static struct ltq_pinmux_info falcon_info = {
  345. .desc = &falcon_pctrl_desc,
  346. .apply_mux = falcon_mux_apply,
  347. .params = falcon_cfg_params,
  348. .num_params = ARRAY_SIZE(falcon_cfg_params),
  349. };
  350. /* --------- register the pinctrl layer --------- */
  351. int pinctrl_falcon_get_range_size(int id)
  352. {
  353. u32 avail;
  354. if ((id >= PORTS) || (!falcon_info.membase[id]))
  355. return -EINVAL;
  356. avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
  357. return fls(avail);
  358. }
  359. void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
  360. {
  361. pinctrl_add_gpio_range(falcon_info.pctrl, range);
  362. }
  363. static int pinctrl_falcon_probe(struct platform_device *pdev)
  364. {
  365. struct device_node *np;
  366. int pad_count = 0;
  367. int ret = 0;
  368. /* load and remap the pad resources of the different banks */
  369. for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
  370. const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
  371. struct resource res;
  372. struct platform_device *ppdev;
  373. u32 avail;
  374. int pins;
  375. if (!of_device_is_available(np))
  376. continue;
  377. if (!bank || *bank >= PORTS)
  378. continue;
  379. if (of_address_to_resource(np, 0, &res))
  380. continue;
  381. ppdev = of_find_device_by_node(np);
  382. if (!ppdev) {
  383. dev_err(&pdev->dev, "failed to find pad pdev\n");
  384. continue;
  385. }
  386. falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
  387. put_device(&ppdev->dev);
  388. if (IS_ERR(falcon_info.clk[*bank])) {
  389. dev_err(&ppdev->dev, "failed to get clock\n");
  390. of_node_put(np);
  391. return PTR_ERR(falcon_info.clk[*bank]);
  392. }
  393. falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev,
  394. &res);
  395. if (IS_ERR(falcon_info.membase[*bank])) {
  396. of_node_put(np);
  397. return PTR_ERR(falcon_info.membase[*bank]);
  398. }
  399. avail = pad_r32(falcon_info.membase[*bank],
  400. LTQ_PADC_AVAIL);
  401. pins = fls(avail);
  402. lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
  403. pad_count += pins;
  404. clk_enable(falcon_info.clk[*bank]);
  405. dev_dbg(&pdev->dev, "found %s with %d pads\n",
  406. res.name, pins);
  407. }
  408. dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
  409. falcon_pctrl_desc.name = dev_name(&pdev->dev);
  410. falcon_pctrl_desc.npins = pad_count;
  411. falcon_info.mfp = falcon_mfp;
  412. falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
  413. falcon_info.grps = falcon_grps;
  414. falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
  415. falcon_info.funcs = falcon_funcs;
  416. falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
  417. ret = ltq_pinctrl_register(pdev, &falcon_info);
  418. if (!ret)
  419. dev_info(&pdev->dev, "Init done\n");
  420. return ret;
  421. }
  422. static const struct of_device_id falcon_match[] = {
  423. { .compatible = "lantiq,pinctrl-falcon" },
  424. {},
  425. };
  426. MODULE_DEVICE_TABLE(of, falcon_match);
  427. static struct platform_driver pinctrl_falcon_driver = {
  428. .probe = pinctrl_falcon_probe,
  429. .driver = {
  430. .name = "pinctrl-falcon",
  431. .of_match_table = falcon_match,
  432. },
  433. };
  434. int __init pinctrl_falcon_init(void)
  435. {
  436. return platform_driver_register(&pinctrl_falcon_driver);
  437. }
  438. core_initcall_sync(pinctrl_falcon_init);