pinctrl-equilibrium.h 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright(c) 2019 Intel Corporation.
  4. */
  5. #ifndef __PINCTRL_EQUILIBRIUM_H
  6. #define __PINCTRL_EQUILIBRIUM_H
  7. /* PINPAD register offset */
  8. #define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */
  9. #define REG_PUEN 0x80 /* PULL UP Enable Register */
  10. #define REG_PDEN 0x84 /* PULL DOWN Enable Register */
  11. #define REG_SRC 0x88 /* Slew Rate Control Register */
  12. #define REG_DCC0 0x8C /* Drive Current Control Register 0 */
  13. #define REG_DCC1 0x90 /* Drive Current Control Register 1 */
  14. #define REG_OD 0x94 /* Open Drain Enable Register */
  15. #define REG_AVAIL 0x98 /* Pad Control Availability Register */
  16. #define DRV_CUR_PINS 16 /* Drive Current pin number per register */
  17. #define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */
  18. /* GPIO register offset */
  19. #define GPIO_OUT 0x0 /* Data Output Register */
  20. #define GPIO_IN 0x4 /* Data Input Register */
  21. #define GPIO_DIR 0x8 /* Direction Register */
  22. #define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */
  23. #define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */
  24. #define GPIO_IRNCR 0x20 /* IRN Capture Register */
  25. #define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */
  26. #define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */
  27. #define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */
  28. #define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */
  29. #define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */
  30. #define GPIO_OUTSET 0x40 /* Output Set Register */
  31. #define GPIO_OUTCLR 0x44 /* Output Clear Register */
  32. #define GPIO_DIRSET 0x48 /* Direction Set Register */
  33. #define GPIO_DIRCLR 0x4C /* Direction Clear Register */
  34. /* parse given pin's driver current value */
  35. #define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3)
  36. #define GPIO_EDGE_TRIG 0
  37. #define GPIO_LEVEL_TRIG 1
  38. #define GPIO_SINGLE_EDGE 0
  39. #define GPIO_BOTH_EDGE 1
  40. #define GPIO_POSITIVE_TRIG 0
  41. #define GPIO_NEGATIVE_TRIG 1
  42. #define EQBR_GPIO_MODE 0
  43. typedef enum {
  44. OP_COUNT_NR_FUNCS,
  45. OP_ADD_FUNCS,
  46. OP_COUNT_NR_FUNC_GRPS,
  47. OP_ADD_FUNC_GRPS,
  48. OP_NONE,
  49. } funcs_util_ops;
  50. /**
  51. * struct gpio_irq_type: gpio irq configuration
  52. * @trig_type: level trigger or edge trigger
  53. * @edge_type: sigle edge or both edge
  54. * @logic_type: positive trigger or negative trigger
  55. */
  56. struct gpio_irq_type {
  57. unsigned int trig_type;
  58. unsigned int edge_type;
  59. unsigned int logic_type;
  60. };
  61. /**
  62. * struct eqbr_pmx_func: represent a pin function.
  63. * @name: name of the pin function, used to lookup the function.
  64. * @groups: one or more names of pin groups that provide this function.
  65. * @nr_groups: number of groups included in @groups.
  66. */
  67. struct eqbr_pmx_func {
  68. const char *name;
  69. const char **groups;
  70. unsigned int nr_groups;
  71. };
  72. /**
  73. * struct eqbr_pin_bank: represent a pin bank.
  74. * @membase: base address of the pin bank register.
  75. * @id: bank id, to idenify the unique bank.
  76. * @pin_base: starting pin number of the pin bank.
  77. * @nr_pins: number of the pins of the pin bank.
  78. * @aval_pinmap: available pin bitmap of the pin bank.
  79. */
  80. struct eqbr_pin_bank {
  81. void __iomem *membase;
  82. unsigned int id;
  83. unsigned int pin_base;
  84. unsigned int nr_pins;
  85. u32 aval_pinmap;
  86. };
  87. /**
  88. * struct eqbr_gpio_ctrl: represent a gpio controller.
  89. * @node: device node of gpio controller.
  90. * @bank: pointer to corresponding pin bank.
  91. * @membase: base address of the gpio controller.
  92. * @chip: gpio chip.
  93. * @ic: irq chip.
  94. * @name: gpio chip name.
  95. * @virq: irq number of the gpio chip to parent's irq domain.
  96. * @lock: spin lock to protect gpio register write.
  97. */
  98. struct eqbr_gpio_ctrl {
  99. struct device_node *node;
  100. struct eqbr_pin_bank *bank;
  101. void __iomem *membase;
  102. struct gpio_chip chip;
  103. struct irq_chip ic;
  104. const char *name;
  105. unsigned int virq;
  106. raw_spinlock_t lock; /* protect gpio register */
  107. };
  108. /**
  109. * struct eqbr_pinctrl_drv_data:
  110. * @dev: device instance representing the controller.
  111. * @pctl_desc: pin controller descriptor.
  112. * @pctl_dev: pin control class device
  113. * @membase: base address of pin controller
  114. * @pin_banks: list of pin banks of the driver.
  115. * @nr_banks: number of pin banks.
  116. * @gpio_ctrls: list of gpio controllers.
  117. * @nr_gpio_ctrls: number of gpio controllers.
  118. * @lock: protect pinctrl register write
  119. */
  120. struct eqbr_pinctrl_drv_data {
  121. struct device *dev;
  122. struct pinctrl_desc pctl_desc;
  123. struct pinctrl_dev *pctl_dev;
  124. void __iomem *membase;
  125. struct eqbr_pin_bank *pin_banks;
  126. unsigned int nr_banks;
  127. struct eqbr_gpio_ctrl *gpio_ctrls;
  128. unsigned int nr_gpio_ctrls;
  129. raw_spinlock_t lock; /* protect pinpad register */
  130. };
  131. #endif /* __PINCTRL_EQUILIBRIUM_H */