pinctrl-equilibrium.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (C) 2019 Intel Corporation */
  3. #include <linux/gpio/driver.h>
  4. #include <linux/module.h>
  5. #include <linux/of.h>
  6. #include <linux/of_address.h>
  7. #include <linux/of_irq.h>
  8. #include <linux/pinctrl/pinctrl.h>
  9. #include <linux/pinctrl/pinconf.h>
  10. #include <linux/pinctrl/pinconf-generic.h>
  11. #include <linux/pinctrl/pinmux.h>
  12. #include <linux/platform_device.h>
  13. #include "core.h"
  14. #include "pinconf.h"
  15. #include "pinmux.h"
  16. #include "pinctrl-equilibrium.h"
  17. #define PIN_NAME_FMT "io-%d"
  18. #define PIN_NAME_LEN 10
  19. #define PAD_REG_OFF 0x100
  20. static void eqbr_gpio_disable_irq(struct irq_data *d)
  21. {
  22. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  23. struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
  24. unsigned int offset = irqd_to_hwirq(d);
  25. unsigned long flags;
  26. raw_spin_lock_irqsave(&gctrl->lock, flags);
  27. writel(BIT(offset), gctrl->membase + GPIO_IRNENCLR);
  28. raw_spin_unlock_irqrestore(&gctrl->lock, flags);
  29. }
  30. static void eqbr_gpio_enable_irq(struct irq_data *d)
  31. {
  32. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  33. struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
  34. unsigned int offset = irqd_to_hwirq(d);
  35. unsigned long flags;
  36. gc->direction_input(gc, offset);
  37. raw_spin_lock_irqsave(&gctrl->lock, flags);
  38. writel(BIT(offset), gctrl->membase + GPIO_IRNRNSET);
  39. raw_spin_unlock_irqrestore(&gctrl->lock, flags);
  40. }
  41. static void eqbr_gpio_ack_irq(struct irq_data *d)
  42. {
  43. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  44. struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
  45. unsigned int offset = irqd_to_hwirq(d);
  46. unsigned long flags;
  47. raw_spin_lock_irqsave(&gctrl->lock, flags);
  48. writel(BIT(offset), gctrl->membase + GPIO_IRNCR);
  49. raw_spin_unlock_irqrestore(&gctrl->lock, flags);
  50. }
  51. static void eqbr_gpio_mask_ack_irq(struct irq_data *d)
  52. {
  53. eqbr_gpio_disable_irq(d);
  54. eqbr_gpio_ack_irq(d);
  55. }
  56. static inline void eqbr_cfg_bit(void __iomem *addr,
  57. unsigned int offset, unsigned int set)
  58. {
  59. if (set)
  60. writel(readl(addr) | BIT(offset), addr);
  61. else
  62. writel(readl(addr) & ~BIT(offset), addr);
  63. }
  64. static int eqbr_irq_type_cfg(struct gpio_irq_type *type,
  65. struct eqbr_gpio_ctrl *gctrl,
  66. unsigned int offset)
  67. {
  68. unsigned long flags;
  69. raw_spin_lock_irqsave(&gctrl->lock, flags);
  70. eqbr_cfg_bit(gctrl->membase + GPIO_IRNCFG, offset, type->trig_type);
  71. eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR1, offset, type->trig_type);
  72. eqbr_cfg_bit(gctrl->membase + GPIO_EXINTCR0, offset, type->logic_type);
  73. raw_spin_unlock_irqrestore(&gctrl->lock, flags);
  74. return 0;
  75. }
  76. static int eqbr_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  77. {
  78. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  79. struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
  80. unsigned int offset = irqd_to_hwirq(d);
  81. struct gpio_irq_type it;
  82. memset(&it, 0, sizeof(it));
  83. if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
  84. return 0;
  85. switch (type) {
  86. case IRQ_TYPE_EDGE_RISING:
  87. it.trig_type = GPIO_EDGE_TRIG;
  88. it.edge_type = GPIO_SINGLE_EDGE;
  89. it.logic_type = GPIO_POSITIVE_TRIG;
  90. break;
  91. case IRQ_TYPE_EDGE_FALLING:
  92. it.trig_type = GPIO_EDGE_TRIG;
  93. it.edge_type = GPIO_SINGLE_EDGE;
  94. it.logic_type = GPIO_NEGATIVE_TRIG;
  95. break;
  96. case IRQ_TYPE_EDGE_BOTH:
  97. it.trig_type = GPIO_EDGE_TRIG;
  98. it.edge_type = GPIO_BOTH_EDGE;
  99. it.logic_type = GPIO_POSITIVE_TRIG;
  100. break;
  101. case IRQ_TYPE_LEVEL_HIGH:
  102. it.trig_type = GPIO_LEVEL_TRIG;
  103. it.edge_type = GPIO_SINGLE_EDGE;
  104. it.logic_type = GPIO_POSITIVE_TRIG;
  105. break;
  106. case IRQ_TYPE_LEVEL_LOW:
  107. it.trig_type = GPIO_LEVEL_TRIG;
  108. it.edge_type = GPIO_SINGLE_EDGE;
  109. it.logic_type = GPIO_NEGATIVE_TRIG;
  110. break;
  111. default:
  112. return -EINVAL;
  113. }
  114. eqbr_irq_type_cfg(&it, gctrl, offset);
  115. if (it.trig_type == GPIO_EDGE_TRIG)
  116. irq_set_handler_locked(d, handle_edge_irq);
  117. else
  118. irq_set_handler_locked(d, handle_level_irq);
  119. return 0;
  120. }
  121. static void eqbr_irq_handler(struct irq_desc *desc)
  122. {
  123. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  124. struct eqbr_gpio_ctrl *gctrl = gpiochip_get_data(gc);
  125. struct irq_chip *ic = irq_desc_get_chip(desc);
  126. unsigned long pins, offset;
  127. chained_irq_enter(ic, desc);
  128. pins = readl(gctrl->membase + GPIO_IRNCR);
  129. for_each_set_bit(offset, &pins, gc->ngpio)
  130. generic_handle_irq(irq_find_mapping(gc->irq.domain, offset));
  131. chained_irq_exit(ic, desc);
  132. }
  133. static int gpiochip_setup(struct device *dev, struct eqbr_gpio_ctrl *gctrl)
  134. {
  135. struct gpio_irq_chip *girq;
  136. struct gpio_chip *gc;
  137. gc = &gctrl->chip;
  138. gc->label = gctrl->name;
  139. #if defined(CONFIG_OF_GPIO)
  140. gc->of_node = gctrl->node;
  141. #endif
  142. if (!of_property_read_bool(gctrl->node, "interrupt-controller")) {
  143. dev_dbg(dev, "gc %s: doesn't act as interrupt controller!\n",
  144. gctrl->name);
  145. return 0;
  146. }
  147. gctrl->ic.name = "gpio_irq";
  148. gctrl->ic.irq_mask = eqbr_gpio_disable_irq;
  149. gctrl->ic.irq_unmask = eqbr_gpio_enable_irq;
  150. gctrl->ic.irq_ack = eqbr_gpio_ack_irq;
  151. gctrl->ic.irq_mask_ack = eqbr_gpio_mask_ack_irq;
  152. gctrl->ic.irq_set_type = eqbr_gpio_set_irq_type;
  153. girq = &gctrl->chip.irq;
  154. girq->chip = &gctrl->ic;
  155. girq->parent_handler = eqbr_irq_handler;
  156. girq->num_parents = 1;
  157. girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), GFP_KERNEL);
  158. if (!girq->parents)
  159. return -ENOMEM;
  160. girq->default_type = IRQ_TYPE_NONE;
  161. girq->handler = handle_bad_irq;
  162. girq->parents[0] = gctrl->virq;
  163. return 0;
  164. }
  165. static int gpiolib_reg(struct eqbr_pinctrl_drv_data *drvdata)
  166. {
  167. struct device *dev = drvdata->dev;
  168. struct eqbr_gpio_ctrl *gctrl;
  169. struct device_node *np;
  170. struct resource res;
  171. int i, ret;
  172. for (i = 0; i < drvdata->nr_gpio_ctrls; i++) {
  173. gctrl = drvdata->gpio_ctrls + i;
  174. np = gctrl->node;
  175. gctrl->name = devm_kasprintf(dev, GFP_KERNEL, "gpiochip%d", i);
  176. if (!gctrl->name)
  177. return -ENOMEM;
  178. if (of_address_to_resource(np, 0, &res)) {
  179. dev_err(dev, "Failed to get GPIO register address\n");
  180. return -ENXIO;
  181. }
  182. gctrl->membase = devm_ioremap_resource(dev, &res);
  183. if (IS_ERR(gctrl->membase))
  184. return PTR_ERR(gctrl->membase);
  185. gctrl->virq = irq_of_parse_and_map(np, 0);
  186. if (!gctrl->virq) {
  187. dev_err(dev, "%s: failed to parse and map irq\n",
  188. gctrl->name);
  189. return -ENXIO;
  190. }
  191. raw_spin_lock_init(&gctrl->lock);
  192. ret = bgpio_init(&gctrl->chip, dev, gctrl->bank->nr_pins / 8,
  193. gctrl->membase + GPIO_IN,
  194. gctrl->membase + GPIO_OUTSET,
  195. gctrl->membase + GPIO_OUTCLR,
  196. gctrl->membase + GPIO_DIR,
  197. NULL, 0);
  198. if (ret) {
  199. dev_err(dev, "unable to init generic GPIO\n");
  200. return ret;
  201. }
  202. ret = gpiochip_setup(dev, gctrl);
  203. if (ret)
  204. return ret;
  205. ret = devm_gpiochip_add_data(dev, &gctrl->chip, gctrl);
  206. if (ret)
  207. return ret;
  208. }
  209. return 0;
  210. }
  211. static inline struct eqbr_pin_bank
  212. *find_pinbank_via_pin(struct eqbr_pinctrl_drv_data *pctl, unsigned int pin)
  213. {
  214. struct eqbr_pin_bank *bank;
  215. int i;
  216. for (i = 0; i < pctl->nr_banks; i++) {
  217. bank = &pctl->pin_banks[i];
  218. if (pin >= bank->pin_base &&
  219. (pin - bank->pin_base) < bank->nr_pins)
  220. return bank;
  221. }
  222. return NULL;
  223. }
  224. static const struct pinctrl_ops eqbr_pctl_ops = {
  225. .get_groups_count = pinctrl_generic_get_group_count,
  226. .get_group_name = pinctrl_generic_get_group_name,
  227. .get_group_pins = pinctrl_generic_get_group_pins,
  228. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  229. .dt_free_map = pinconf_generic_dt_free_map,
  230. };
  231. static int eqbr_set_pin_mux(struct eqbr_pinctrl_drv_data *pctl,
  232. unsigned int pmx, unsigned int pin)
  233. {
  234. struct eqbr_pin_bank *bank;
  235. unsigned long flags;
  236. unsigned int offset;
  237. void __iomem *mem;
  238. bank = find_pinbank_via_pin(pctl, pin);
  239. if (!bank) {
  240. dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
  241. return -ENODEV;
  242. }
  243. mem = bank->membase;
  244. offset = pin - bank->pin_base;
  245. if (!(bank->aval_pinmap & BIT(offset))) {
  246. dev_err(pctl->dev,
  247. "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
  248. pin, bank->pin_base, bank->aval_pinmap);
  249. return -ENODEV;
  250. }
  251. raw_spin_lock_irqsave(&pctl->lock, flags);
  252. writel(pmx, mem + (offset * 4));
  253. raw_spin_unlock_irqrestore(&pctl->lock, flags);
  254. return 0;
  255. }
  256. static int eqbr_pinmux_set_mux(struct pinctrl_dev *pctldev,
  257. unsigned int selector, unsigned int group)
  258. {
  259. struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
  260. struct function_desc *func;
  261. struct group_desc *grp;
  262. unsigned int *pinmux;
  263. int i;
  264. func = pinmux_generic_get_function(pctldev, selector);
  265. if (!func)
  266. return -EINVAL;
  267. grp = pinctrl_generic_get_group(pctldev, group);
  268. if (!grp)
  269. return -EINVAL;
  270. pinmux = grp->data;
  271. for (i = 0; i < grp->num_pins; i++)
  272. eqbr_set_pin_mux(pctl, pinmux[i], grp->pins[i]);
  273. return 0;
  274. }
  275. static int eqbr_pinmux_gpio_request(struct pinctrl_dev *pctldev,
  276. struct pinctrl_gpio_range *range,
  277. unsigned int pin)
  278. {
  279. struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
  280. return eqbr_set_pin_mux(pctl, EQBR_GPIO_MODE, pin);
  281. }
  282. static const struct pinmux_ops eqbr_pinmux_ops = {
  283. .get_functions_count = pinmux_generic_get_function_count,
  284. .get_function_name = pinmux_generic_get_function_name,
  285. .get_function_groups = pinmux_generic_get_function_groups,
  286. .set_mux = eqbr_pinmux_set_mux,
  287. .gpio_request_enable = eqbr_pinmux_gpio_request,
  288. .strict = true,
  289. };
  290. static int get_drv_cur(void __iomem *mem, unsigned int offset)
  291. {
  292. unsigned int idx = offset / DRV_CUR_PINS; /* 0-15, 16-31 per register*/
  293. unsigned int pin_offset = offset % DRV_CUR_PINS;
  294. return PARSE_DRV_CURRENT(readl(mem + REG_DRCC(idx)), pin_offset);
  295. }
  296. static struct eqbr_gpio_ctrl
  297. *get_gpio_ctrls_via_bank(struct eqbr_pinctrl_drv_data *pctl,
  298. struct eqbr_pin_bank *bank)
  299. {
  300. int i;
  301. for (i = 0; i < pctl->nr_gpio_ctrls; i++) {
  302. if (pctl->gpio_ctrls[i].bank == bank)
  303. return &pctl->gpio_ctrls[i];
  304. }
  305. return NULL;
  306. }
  307. static int eqbr_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
  308. unsigned long *config)
  309. {
  310. struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
  311. enum pin_config_param param = pinconf_to_config_param(*config);
  312. struct eqbr_gpio_ctrl *gctrl;
  313. struct eqbr_pin_bank *bank;
  314. unsigned long flags;
  315. unsigned int offset;
  316. void __iomem *mem;
  317. u32 val;
  318. bank = find_pinbank_via_pin(pctl, pin);
  319. if (!bank) {
  320. dev_err(pctl->dev, "Couldn't find pin bank for pin %u\n", pin);
  321. return -ENODEV;
  322. }
  323. mem = bank->membase;
  324. offset = pin - bank->pin_base;
  325. if (!(bank->aval_pinmap & BIT(offset))) {
  326. dev_err(pctl->dev,
  327. "PIN: %u is not valid, pinbase: %u, bitmap: %u\n",
  328. pin, bank->pin_base, bank->aval_pinmap);
  329. return -ENODEV;
  330. }
  331. raw_spin_lock_irqsave(&pctl->lock, flags);
  332. switch (param) {
  333. case PIN_CONFIG_BIAS_PULL_UP:
  334. val = !!(readl(mem + REG_PUEN) & BIT(offset));
  335. break;
  336. case PIN_CONFIG_BIAS_PULL_DOWN:
  337. val = !!(readl(mem + REG_PDEN) & BIT(offset));
  338. break;
  339. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  340. val = !!(readl(mem + REG_OD) & BIT(offset));
  341. break;
  342. case PIN_CONFIG_DRIVE_STRENGTH:
  343. val = get_drv_cur(mem, offset);
  344. break;
  345. case PIN_CONFIG_SLEW_RATE:
  346. val = !!(readl(mem + REG_SRC) & BIT(offset));
  347. break;
  348. case PIN_CONFIG_OUTPUT_ENABLE:
  349. gctrl = get_gpio_ctrls_via_bank(pctl, bank);
  350. if (!gctrl) {
  351. dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
  352. bank->pin_base, pin);
  353. raw_spin_unlock_irqrestore(&pctl->lock, flags);
  354. return -ENODEV;
  355. }
  356. val = !!(readl(gctrl->membase + GPIO_DIR) & BIT(offset));
  357. break;
  358. default:
  359. raw_spin_unlock_irqrestore(&pctl->lock, flags);
  360. return -ENOTSUPP;
  361. }
  362. raw_spin_unlock_irqrestore(&pctl->lock, flags);
  363. *config = pinconf_to_config_packed(param, val);
  364. ;
  365. return 0;
  366. }
  367. static int eqbr_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  368. unsigned long *configs, unsigned int num_configs)
  369. {
  370. struct eqbr_pinctrl_drv_data *pctl = pinctrl_dev_get_drvdata(pctldev);
  371. struct eqbr_gpio_ctrl *gctrl;
  372. enum pin_config_param param;
  373. struct eqbr_pin_bank *bank;
  374. unsigned int val, offset;
  375. struct gpio_chip *gc;
  376. unsigned long flags;
  377. void __iomem *mem;
  378. u32 regval, mask;
  379. int i;
  380. for (i = 0; i < num_configs; i++) {
  381. param = pinconf_to_config_param(configs[i]);
  382. val = pinconf_to_config_argument(configs[i]);
  383. bank = find_pinbank_via_pin(pctl, pin);
  384. if (!bank) {
  385. dev_err(pctl->dev,
  386. "Couldn't find pin bank for pin %u\n", pin);
  387. return -ENODEV;
  388. }
  389. mem = bank->membase;
  390. offset = pin - bank->pin_base;
  391. switch (param) {
  392. case PIN_CONFIG_BIAS_PULL_UP:
  393. mem += REG_PUEN;
  394. mask = BIT(offset);
  395. break;
  396. case PIN_CONFIG_BIAS_PULL_DOWN:
  397. mem += REG_PDEN;
  398. mask = BIT(offset);
  399. break;
  400. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  401. mem += REG_OD;
  402. mask = BIT(offset);
  403. break;
  404. case PIN_CONFIG_DRIVE_STRENGTH:
  405. mem += REG_DRCC(offset / DRV_CUR_PINS);
  406. offset = (offset % DRV_CUR_PINS) * 2;
  407. mask = GENMASK(1, 0) << offset;
  408. break;
  409. case PIN_CONFIG_SLEW_RATE:
  410. mem += REG_SRC;
  411. mask = BIT(offset);
  412. break;
  413. case PIN_CONFIG_OUTPUT_ENABLE:
  414. gctrl = get_gpio_ctrls_via_bank(pctl, bank);
  415. if (!gctrl) {
  416. dev_err(pctl->dev, "Failed to find gpio via bank pinbase: %u, pin: %u\n",
  417. bank->pin_base, pin);
  418. return -ENODEV;
  419. }
  420. gc = &gctrl->chip;
  421. gc->direction_output(gc, offset, 0);
  422. continue;
  423. default:
  424. return -ENOTSUPP;
  425. }
  426. raw_spin_lock_irqsave(&pctl->lock, flags);
  427. regval = readl(mem);
  428. regval = (regval & ~mask) | ((val << offset) & mask);
  429. writel(regval, mem);
  430. raw_spin_unlock_irqrestore(&pctl->lock, flags);
  431. }
  432. return 0;
  433. }
  434. static int eqbr_pinconf_group_get(struct pinctrl_dev *pctldev,
  435. unsigned int group, unsigned long *config)
  436. {
  437. unsigned int i, npins, old = 0;
  438. const unsigned int *pins;
  439. int ret;
  440. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  441. if (ret)
  442. return ret;
  443. for (i = 0; i < npins; i++) {
  444. if (eqbr_pinconf_get(pctldev, pins[i], config))
  445. return -ENOTSUPP;
  446. if (i && old != *config)
  447. return -ENOTSUPP;
  448. old = *config;
  449. }
  450. return 0;
  451. }
  452. static int eqbr_pinconf_group_set(struct pinctrl_dev *pctldev,
  453. unsigned int group, unsigned long *configs,
  454. unsigned int num_configs)
  455. {
  456. const unsigned int *pins;
  457. unsigned int i, npins;
  458. int ret;
  459. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  460. if (ret)
  461. return ret;
  462. for (i = 0; i < npins; i++) {
  463. ret = eqbr_pinconf_set(pctldev, pins[i], configs, num_configs);
  464. if (ret)
  465. return ret;
  466. }
  467. return 0;
  468. }
  469. static const struct pinconf_ops eqbr_pinconf_ops = {
  470. .is_generic = true,
  471. .pin_config_get = eqbr_pinconf_get,
  472. .pin_config_set = eqbr_pinconf_set,
  473. .pin_config_group_get = eqbr_pinconf_group_get,
  474. .pin_config_group_set = eqbr_pinconf_group_set,
  475. .pin_config_config_dbg_show = pinconf_generic_dump_config,
  476. };
  477. static bool is_func_exist(struct eqbr_pmx_func *funcs, const char *name,
  478. unsigned int nr_funcs, unsigned int *idx)
  479. {
  480. int i;
  481. if (!funcs)
  482. return false;
  483. for (i = 0; i < nr_funcs; i++) {
  484. if (funcs[i].name && !strcmp(funcs[i].name, name)) {
  485. *idx = i;
  486. return true;
  487. }
  488. }
  489. return false;
  490. }
  491. static int funcs_utils(struct device *dev, struct eqbr_pmx_func *funcs,
  492. unsigned int *nr_funcs, funcs_util_ops op)
  493. {
  494. struct device_node *node = dev->of_node;
  495. struct device_node *np;
  496. struct property *prop;
  497. const char *fn_name;
  498. unsigned int fid;
  499. int i, j;
  500. i = 0;
  501. for_each_child_of_node(node, np) {
  502. prop = of_find_property(np, "groups", NULL);
  503. if (!prop)
  504. continue;
  505. if (of_property_read_string(np, "function", &fn_name)) {
  506. /* some groups may not have function, it's OK */
  507. dev_dbg(dev, "Group %s: not function binded!\n",
  508. (char *)prop->value);
  509. continue;
  510. }
  511. switch (op) {
  512. case OP_COUNT_NR_FUNCS:
  513. if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
  514. *nr_funcs = *nr_funcs + 1;
  515. break;
  516. case OP_ADD_FUNCS:
  517. if (!is_func_exist(funcs, fn_name, *nr_funcs, &fid))
  518. funcs[i].name = fn_name;
  519. break;
  520. case OP_COUNT_NR_FUNC_GRPS:
  521. if (is_func_exist(funcs, fn_name, *nr_funcs, &fid))
  522. funcs[fid].nr_groups++;
  523. break;
  524. case OP_ADD_FUNC_GRPS:
  525. if (is_func_exist(funcs, fn_name, *nr_funcs, &fid)) {
  526. for (j = 0; j < funcs[fid].nr_groups; j++)
  527. if (!funcs[fid].groups[j])
  528. break;
  529. funcs[fid].groups[j] = prop->value;
  530. }
  531. break;
  532. default:
  533. return -EINVAL;
  534. }
  535. i++;
  536. }
  537. return 0;
  538. }
  539. static int eqbr_build_functions(struct eqbr_pinctrl_drv_data *drvdata)
  540. {
  541. struct device *dev = drvdata->dev;
  542. struct eqbr_pmx_func *funcs = NULL;
  543. unsigned int nr_funcs = 0;
  544. int i, ret;
  545. ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNCS);
  546. if (ret)
  547. return ret;
  548. funcs = devm_kcalloc(dev, nr_funcs, sizeof(*funcs), GFP_KERNEL);
  549. if (!funcs)
  550. return -ENOMEM;
  551. ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNCS);
  552. if (ret)
  553. return ret;
  554. ret = funcs_utils(dev, funcs, &nr_funcs, OP_COUNT_NR_FUNC_GRPS);
  555. if (ret)
  556. return ret;
  557. for (i = 0; i < nr_funcs; i++) {
  558. if (!funcs[i].nr_groups)
  559. continue;
  560. funcs[i].groups = devm_kcalloc(dev, funcs[i].nr_groups,
  561. sizeof(*(funcs[i].groups)),
  562. GFP_KERNEL);
  563. if (!funcs[i].groups)
  564. return -ENOMEM;
  565. }
  566. ret = funcs_utils(dev, funcs, &nr_funcs, OP_ADD_FUNC_GRPS);
  567. if (ret)
  568. return ret;
  569. for (i = 0; i < nr_funcs; i++) {
  570. /* Ignore the same function with multiple groups */
  571. if (funcs[i].name == NULL)
  572. continue;
  573. ret = pinmux_generic_add_function(drvdata->pctl_dev,
  574. funcs[i].name,
  575. funcs[i].groups,
  576. funcs[i].nr_groups,
  577. drvdata);
  578. if (ret < 0) {
  579. dev_err(dev, "Failed to register function %s\n",
  580. funcs[i].name);
  581. return ret;
  582. }
  583. }
  584. return 0;
  585. }
  586. static int eqbr_build_groups(struct eqbr_pinctrl_drv_data *drvdata)
  587. {
  588. struct device *dev = drvdata->dev;
  589. struct device_node *node = dev->of_node;
  590. unsigned int *pinmux, pin_id, pinmux_id;
  591. struct group_desc group;
  592. struct device_node *np;
  593. struct property *prop;
  594. int j, err;
  595. for_each_child_of_node(node, np) {
  596. prop = of_find_property(np, "groups", NULL);
  597. if (!prop)
  598. continue;
  599. group.num_pins = of_property_count_u32_elems(np, "pins");
  600. if (group.num_pins < 0) {
  601. dev_err(dev, "No pins in the group: %s\n", prop->name);
  602. return -EINVAL;
  603. }
  604. group.name = prop->value;
  605. group.pins = devm_kcalloc(dev, group.num_pins,
  606. sizeof(*(group.pins)), GFP_KERNEL);
  607. if (!group.pins)
  608. return -ENOMEM;
  609. pinmux = devm_kcalloc(dev, group.num_pins, sizeof(*pinmux),
  610. GFP_KERNEL);
  611. if (!pinmux)
  612. return -ENOMEM;
  613. for (j = 0; j < group.num_pins; j++) {
  614. if (of_property_read_u32_index(np, "pins", j, &pin_id)) {
  615. dev_err(dev, "Group %s: Read intel pins id failed\n",
  616. group.name);
  617. return -EINVAL;
  618. }
  619. if (pin_id >= drvdata->pctl_desc.npins) {
  620. dev_err(dev, "Group %s: Invalid pin ID, idx: %d, pin %u\n",
  621. group.name, j, pin_id);
  622. return -EINVAL;
  623. }
  624. group.pins[j] = pin_id;
  625. if (of_property_read_u32_index(np, "pinmux", j, &pinmux_id)) {
  626. dev_err(dev, "Group %s: Read intel pinmux id failed\n",
  627. group.name);
  628. return -EINVAL;
  629. }
  630. pinmux[j] = pinmux_id;
  631. }
  632. err = pinctrl_generic_add_group(drvdata->pctl_dev, group.name,
  633. group.pins, group.num_pins,
  634. pinmux);
  635. if (err < 0) {
  636. dev_err(dev, "Failed to register group %s\n", group.name);
  637. return err;
  638. }
  639. memset(&group, 0, sizeof(group));
  640. pinmux = NULL;
  641. }
  642. return 0;
  643. }
  644. static int pinctrl_reg(struct eqbr_pinctrl_drv_data *drvdata)
  645. {
  646. struct pinctrl_desc *pctl_desc;
  647. struct pinctrl_pin_desc *pdesc;
  648. struct device *dev;
  649. unsigned int nr_pins;
  650. char *pin_names;
  651. int i, ret;
  652. dev = drvdata->dev;
  653. pctl_desc = &drvdata->pctl_desc;
  654. pctl_desc->name = "eqbr-pinctrl";
  655. pctl_desc->owner = THIS_MODULE;
  656. pctl_desc->pctlops = &eqbr_pctl_ops;
  657. pctl_desc->pmxops = &eqbr_pinmux_ops;
  658. pctl_desc->confops = &eqbr_pinconf_ops;
  659. raw_spin_lock_init(&drvdata->lock);
  660. for (i = 0, nr_pins = 0; i < drvdata->nr_banks; i++)
  661. nr_pins += drvdata->pin_banks[i].nr_pins;
  662. pdesc = devm_kcalloc(dev, nr_pins, sizeof(*pdesc), GFP_KERNEL);
  663. if (!pdesc)
  664. return -ENOMEM;
  665. pin_names = devm_kcalloc(dev, nr_pins, PIN_NAME_LEN, GFP_KERNEL);
  666. if (!pin_names)
  667. return -ENOMEM;
  668. for (i = 0; i < nr_pins; i++) {
  669. sprintf(pin_names, PIN_NAME_FMT, i);
  670. pdesc[i].number = i;
  671. pdesc[i].name = pin_names;
  672. pin_names += PIN_NAME_LEN;
  673. }
  674. pctl_desc->pins = pdesc;
  675. pctl_desc->npins = nr_pins;
  676. dev_dbg(dev, "pinctrl total pin number: %u\n", nr_pins);
  677. ret = devm_pinctrl_register_and_init(dev, pctl_desc, drvdata,
  678. &drvdata->pctl_dev);
  679. if (ret)
  680. return ret;
  681. ret = eqbr_build_groups(drvdata);
  682. if (ret) {
  683. dev_err(dev, "Failed to build groups\n");
  684. return ret;
  685. }
  686. ret = eqbr_build_functions(drvdata);
  687. if (ret) {
  688. dev_err(dev, "Failed to build functions\n");
  689. return ret;
  690. }
  691. return pinctrl_enable(drvdata->pctl_dev);
  692. }
  693. static int pinbank_init(struct device_node *np,
  694. struct eqbr_pinctrl_drv_data *drvdata,
  695. struct eqbr_pin_bank *bank, unsigned int id)
  696. {
  697. struct device *dev = drvdata->dev;
  698. struct of_phandle_args spec;
  699. int ret;
  700. bank->membase = drvdata->membase + id * PAD_REG_OFF;
  701. ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &spec);
  702. if (ret) {
  703. dev_err(dev, "gpio-range not available!\n");
  704. return ret;
  705. }
  706. bank->pin_base = spec.args[1];
  707. bank->nr_pins = spec.args[2];
  708. bank->aval_pinmap = readl(bank->membase + REG_AVAIL);
  709. bank->id = id;
  710. dev_dbg(dev, "pinbank id: %d, reg: %px, pinbase: %u, pin number: %u, pinmap: 0x%x\n",
  711. id, bank->membase, bank->pin_base,
  712. bank->nr_pins, bank->aval_pinmap);
  713. return ret;
  714. }
  715. static int pinbank_probe(struct eqbr_pinctrl_drv_data *drvdata)
  716. {
  717. struct device *dev = drvdata->dev;
  718. struct device_node *np_gpio;
  719. struct eqbr_gpio_ctrl *gctrls;
  720. struct eqbr_pin_bank *banks;
  721. int i, nr_gpio;
  722. /* Count gpio bank number */
  723. nr_gpio = 0;
  724. for_each_node_by_name(np_gpio, "gpio") {
  725. if (of_device_is_available(np_gpio))
  726. nr_gpio++;
  727. }
  728. if (!nr_gpio) {
  729. dev_err(dev, "NO pin bank available!\n");
  730. return -ENODEV;
  731. }
  732. /* Count pin bank number and gpio controller number */
  733. banks = devm_kcalloc(dev, nr_gpio, sizeof(*banks), GFP_KERNEL);
  734. if (!banks)
  735. return -ENOMEM;
  736. gctrls = devm_kcalloc(dev, nr_gpio, sizeof(*gctrls), GFP_KERNEL);
  737. if (!gctrls)
  738. return -ENOMEM;
  739. dev_dbg(dev, "found %d gpio controller!\n", nr_gpio);
  740. /* Initialize Pin bank */
  741. i = 0;
  742. for_each_node_by_name(np_gpio, "gpio") {
  743. if (!of_device_is_available(np_gpio))
  744. continue;
  745. pinbank_init(np_gpio, drvdata, banks + i, i);
  746. gctrls[i].node = np_gpio;
  747. gctrls[i].bank = banks + i;
  748. i++;
  749. }
  750. drvdata->pin_banks = banks;
  751. drvdata->nr_banks = nr_gpio;
  752. drvdata->gpio_ctrls = gctrls;
  753. drvdata->nr_gpio_ctrls = nr_gpio;
  754. return 0;
  755. }
  756. static int eqbr_pinctrl_probe(struct platform_device *pdev)
  757. {
  758. struct eqbr_pinctrl_drv_data *drvdata;
  759. struct device *dev = &pdev->dev;
  760. int ret;
  761. drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
  762. if (!drvdata)
  763. return -ENOMEM;
  764. drvdata->dev = dev;
  765. drvdata->membase = devm_platform_ioremap_resource(pdev, 0);
  766. if (IS_ERR(drvdata->membase))
  767. return PTR_ERR(drvdata->membase);
  768. ret = pinbank_probe(drvdata);
  769. if (ret)
  770. return ret;
  771. ret = pinctrl_reg(drvdata);
  772. if (ret)
  773. return ret;
  774. ret = gpiolib_reg(drvdata);
  775. if (ret)
  776. return ret;
  777. platform_set_drvdata(pdev, drvdata);
  778. return 0;
  779. }
  780. static const struct of_device_id eqbr_pinctrl_dt_match[] = {
  781. { .compatible = "intel,lgm-io" },
  782. {}
  783. };
  784. MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match);
  785. static struct platform_driver eqbr_pinctrl_driver = {
  786. .probe = eqbr_pinctrl_probe,
  787. .driver = {
  788. .name = "eqbr-pinctrl",
  789. .of_match_table = eqbr_pinctrl_dt_match,
  790. },
  791. };
  792. module_platform_driver(eqbr_pinctrl_driver);
  793. MODULE_AUTHOR("Zhu Yixin <yixin.zhu@intel.com>, Rahul Tanwar <rahul.tanwar@intel.com>");
  794. MODULE_DESCRIPTION("Pinctrl Driver for LGM SoC (Equilibrium)");
  795. MODULE_LICENSE("GPL v2");