pinctrl-digicolor.c 8.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Conexant Digicolor General Purpose Pin Mapping
  4. *
  5. * Author: Baruch Siach <baruch@tkos.co.il>
  6. *
  7. * Copyright (C) 2015 Paradox Innovation Ltd.
  8. *
  9. * TODO:
  10. * - GPIO interrupt support
  11. * - Pin pad configuration (pull up/down, strength)
  12. */
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/of.h>
  16. #include <linux/of_device.h>
  17. #include <linux/io.h>
  18. #include <linux/gpio/driver.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/pinctrl/machine.h>
  21. #include <linux/pinctrl/pinconf.h>
  22. #include <linux/pinctrl/pinconf-generic.h>
  23. #include <linux/pinctrl/pinctrl.h>
  24. #include <linux/pinctrl/pinmux.h>
  25. #include "pinctrl-utils.h"
  26. #define DRIVER_NAME "pinctrl-digicolor"
  27. #define GP_CLIENTSEL(clct) ((clct)*8 + 0x20)
  28. #define GP_DRIVE0(clct) (GP_CLIENTSEL(clct) + 2)
  29. #define GP_OUTPUT0(clct) (GP_CLIENTSEL(clct) + 3)
  30. #define GP_INPUT(clct) (GP_CLIENTSEL(clct) + 6)
  31. #define PIN_COLLECTIONS ('R' - 'A' + 1)
  32. #define PINS_PER_COLLECTION 8
  33. #define PINS_COUNT (PIN_COLLECTIONS * PINS_PER_COLLECTION)
  34. struct dc_pinmap {
  35. void __iomem *regs;
  36. struct device *dev;
  37. struct pinctrl_dev *pctl;
  38. struct pinctrl_desc *desc;
  39. const char *pin_names[PINS_COUNT];
  40. struct gpio_chip chip;
  41. spinlock_t lock;
  42. };
  43. static int dc_get_groups_count(struct pinctrl_dev *pctldev)
  44. {
  45. return PINS_COUNT;
  46. }
  47. static const char *dc_get_group_name(struct pinctrl_dev *pctldev,
  48. unsigned selector)
  49. {
  50. struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
  51. /* Exactly one group per pin */
  52. return pmap->desc->pins[selector].name;
  53. }
  54. static int dc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  55. const unsigned **pins,
  56. unsigned *num_pins)
  57. {
  58. struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
  59. *pins = &pmap->desc->pins[selector].number;
  60. *num_pins = 1;
  61. return 0;
  62. }
  63. static const struct pinctrl_ops dc_pinctrl_ops = {
  64. .get_groups_count = dc_get_groups_count,
  65. .get_group_name = dc_get_group_name,
  66. .get_group_pins = dc_get_group_pins,
  67. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  68. .dt_free_map = pinctrl_utils_free_map,
  69. };
  70. static const char *const dc_functions[] = {
  71. "gpio",
  72. "client_a",
  73. "client_b",
  74. "client_c",
  75. };
  76. static int dc_get_functions_count(struct pinctrl_dev *pctldev)
  77. {
  78. return ARRAY_SIZE(dc_functions);
  79. }
  80. static const char *dc_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
  81. {
  82. return dc_functions[selector];
  83. }
  84. static int dc_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
  85. const char * const **groups,
  86. unsigned * const num_groups)
  87. {
  88. struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
  89. *groups = pmap->pin_names;
  90. *num_groups = PINS_COUNT;
  91. return 0;
  92. }
  93. static void dc_client_sel(int pin_num, int *reg, int *bit)
  94. {
  95. *bit = (pin_num % PINS_PER_COLLECTION) * 2;
  96. *reg = GP_CLIENTSEL(pin_num/PINS_PER_COLLECTION);
  97. if (*bit >= PINS_PER_COLLECTION) {
  98. *bit -= PINS_PER_COLLECTION;
  99. *reg += 1;
  100. }
  101. }
  102. static int dc_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
  103. unsigned group)
  104. {
  105. struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pctldev);
  106. int bit_off, reg_off;
  107. u8 reg;
  108. dc_client_sel(group, &reg_off, &bit_off);
  109. reg = readb_relaxed(pmap->regs + reg_off);
  110. reg &= ~(3 << bit_off);
  111. reg |= (selector << bit_off);
  112. writeb_relaxed(reg, pmap->regs + reg_off);
  113. return 0;
  114. }
  115. static int dc_pmx_request_gpio(struct pinctrl_dev *pcdev,
  116. struct pinctrl_gpio_range *range,
  117. unsigned offset)
  118. {
  119. struct dc_pinmap *pmap = pinctrl_dev_get_drvdata(pcdev);
  120. int bit_off, reg_off;
  121. u8 reg;
  122. dc_client_sel(offset, &reg_off, &bit_off);
  123. reg = readb_relaxed(pmap->regs + reg_off);
  124. if ((reg & (3 << bit_off)) != 0)
  125. return -EBUSY;
  126. return 0;
  127. }
  128. static const struct pinmux_ops dc_pmxops = {
  129. .get_functions_count = dc_get_functions_count,
  130. .get_function_name = dc_get_fname,
  131. .get_function_groups = dc_get_groups,
  132. .set_mux = dc_set_mux,
  133. .gpio_request_enable = dc_pmx_request_gpio,
  134. };
  135. static int dc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  136. {
  137. struct dc_pinmap *pmap = gpiochip_get_data(chip);
  138. int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
  139. int bit_off = gpio % PINS_PER_COLLECTION;
  140. u8 drive;
  141. unsigned long flags;
  142. spin_lock_irqsave(&pmap->lock, flags);
  143. drive = readb_relaxed(pmap->regs + reg_off);
  144. drive &= ~BIT(bit_off);
  145. writeb_relaxed(drive, pmap->regs + reg_off);
  146. spin_unlock_irqrestore(&pmap->lock, flags);
  147. return 0;
  148. }
  149. static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value);
  150. static int dc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
  151. int value)
  152. {
  153. struct dc_pinmap *pmap = gpiochip_get_data(chip);
  154. int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION);
  155. int bit_off = gpio % PINS_PER_COLLECTION;
  156. u8 drive;
  157. unsigned long flags;
  158. dc_gpio_set(chip, gpio, value);
  159. spin_lock_irqsave(&pmap->lock, flags);
  160. drive = readb_relaxed(pmap->regs + reg_off);
  161. drive |= BIT(bit_off);
  162. writeb_relaxed(drive, pmap->regs + reg_off);
  163. spin_unlock_irqrestore(&pmap->lock, flags);
  164. return 0;
  165. }
  166. static int dc_gpio_get(struct gpio_chip *chip, unsigned gpio)
  167. {
  168. struct dc_pinmap *pmap = gpiochip_get_data(chip);
  169. int reg_off = GP_INPUT(gpio/PINS_PER_COLLECTION);
  170. int bit_off = gpio % PINS_PER_COLLECTION;
  171. u8 input;
  172. input = readb_relaxed(pmap->regs + reg_off);
  173. return !!(input & BIT(bit_off));
  174. }
  175. static void dc_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
  176. {
  177. struct dc_pinmap *pmap = gpiochip_get_data(chip);
  178. int reg_off = GP_OUTPUT0(gpio/PINS_PER_COLLECTION);
  179. int bit_off = gpio % PINS_PER_COLLECTION;
  180. u8 output;
  181. unsigned long flags;
  182. spin_lock_irqsave(&pmap->lock, flags);
  183. output = readb_relaxed(pmap->regs + reg_off);
  184. if (value)
  185. output |= BIT(bit_off);
  186. else
  187. output &= ~BIT(bit_off);
  188. writeb_relaxed(output, pmap->regs + reg_off);
  189. spin_unlock_irqrestore(&pmap->lock, flags);
  190. }
  191. static int dc_gpiochip_add(struct dc_pinmap *pmap, struct device_node *np)
  192. {
  193. struct gpio_chip *chip = &pmap->chip;
  194. int ret;
  195. chip->label = DRIVER_NAME;
  196. chip->parent = pmap->dev;
  197. chip->request = gpiochip_generic_request;
  198. chip->free = gpiochip_generic_free;
  199. chip->direction_input = dc_gpio_direction_input;
  200. chip->direction_output = dc_gpio_direction_output;
  201. chip->get = dc_gpio_get;
  202. chip->set = dc_gpio_set;
  203. chip->base = -1;
  204. chip->ngpio = PINS_COUNT;
  205. chip->of_node = np;
  206. chip->of_gpio_n_cells = 2;
  207. spin_lock_init(&pmap->lock);
  208. ret = gpiochip_add_data(chip, pmap);
  209. if (ret < 0)
  210. return ret;
  211. ret = gpiochip_add_pin_range(chip, dev_name(pmap->dev), 0, 0,
  212. PINS_COUNT);
  213. if (ret < 0) {
  214. gpiochip_remove(chip);
  215. return ret;
  216. }
  217. return 0;
  218. }
  219. static int dc_pinctrl_probe(struct platform_device *pdev)
  220. {
  221. struct dc_pinmap *pmap;
  222. struct pinctrl_pin_desc *pins;
  223. struct pinctrl_desc *pctl_desc;
  224. char *pin_names;
  225. int name_len = strlen("GP_xx") + 1;
  226. int i, j;
  227. pmap = devm_kzalloc(&pdev->dev, sizeof(*pmap), GFP_KERNEL);
  228. if (!pmap)
  229. return -ENOMEM;
  230. pmap->regs = devm_platform_ioremap_resource(pdev, 0);
  231. if (IS_ERR(pmap->regs))
  232. return PTR_ERR(pmap->regs);
  233. pins = devm_kcalloc(&pdev->dev, PINS_COUNT, sizeof(*pins),
  234. GFP_KERNEL);
  235. if (!pins)
  236. return -ENOMEM;
  237. pin_names = devm_kcalloc(&pdev->dev, PINS_COUNT, name_len,
  238. GFP_KERNEL);
  239. if (!pin_names)
  240. return -ENOMEM;
  241. for (i = 0; i < PIN_COLLECTIONS; i++) {
  242. for (j = 0; j < PINS_PER_COLLECTION; j++) {
  243. int pin_id = i*PINS_PER_COLLECTION + j;
  244. char *name = &pin_names[pin_id * name_len];
  245. snprintf(name, name_len, "GP_%c%c", 'A'+i, '0'+j);
  246. pins[pin_id].number = pin_id;
  247. pins[pin_id].name = name;
  248. pmap->pin_names[pin_id] = name;
  249. }
  250. }
  251. pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
  252. if (!pctl_desc)
  253. return -ENOMEM;
  254. pctl_desc->name = DRIVER_NAME,
  255. pctl_desc->owner = THIS_MODULE,
  256. pctl_desc->pctlops = &dc_pinctrl_ops,
  257. pctl_desc->pmxops = &dc_pmxops,
  258. pctl_desc->npins = PINS_COUNT;
  259. pctl_desc->pins = pins;
  260. pmap->desc = pctl_desc;
  261. pmap->dev = &pdev->dev;
  262. pmap->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, pmap);
  263. if (IS_ERR(pmap->pctl)) {
  264. dev_err(&pdev->dev, "pinctrl driver registration failed\n");
  265. return PTR_ERR(pmap->pctl);
  266. }
  267. return dc_gpiochip_add(pmap, pdev->dev.of_node);
  268. }
  269. static const struct of_device_id dc_pinctrl_ids[] = {
  270. { .compatible = "cnxt,cx92755-pinctrl" },
  271. { /* sentinel */ }
  272. };
  273. static struct platform_driver dc_pinctrl_driver = {
  274. .driver = {
  275. .name = DRIVER_NAME,
  276. .of_match_table = dc_pinctrl_ids,
  277. .suppress_bind_attrs = true,
  278. },
  279. .probe = dc_pinctrl_probe,
  280. };
  281. builtin_platform_driver(dc_pinctrl_driver);