pinctrl-artpec6.c 26 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000
  1. /*
  2. * Driver for the Axis ARTPEC-6 pin controller
  3. *
  4. * Author: Chris Paterson <chris.paterson@linux.pieboy.co.uk>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without any
  8. * warranty of any kind, whether express or implied.
  9. */
  10. #include <linux/device.h>
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pinctrl/pinctrl.h>
  17. #include <linux/pinctrl/pinconf-generic.h>
  18. #include <linux/pinctrl/pinconf.h>
  19. #include <linux/pinctrl/pinmux.h>
  20. #include <linux/slab.h>
  21. #include "core.h"
  22. #include "pinconf.h"
  23. #include "pinctrl-utils.h"
  24. #define ARTPEC6_LAST_PIN 97 /* 97 pins in pinmux */
  25. #define ARTPEC6_MAX_MUXABLE 35 /* Last pin with muxable function */
  26. /* Pinmux control register bit definitions */
  27. #define ARTPEC6_PINMUX_UDC0_MASK 0x00000001
  28. #define ARTPEC6_PINMUX_UDC0_SHIFT 0
  29. #define ARTPEC6_PINMUX_UDC1_MASK 0x00000002
  30. #define ARTPEC6_PINMUX_UDC1_SHIFT 1
  31. #define ARTPEC6_PINMUX_DRV_MASK 0x00000060
  32. #define ARTPEC6_PINMUX_DRV_SHIFT 5
  33. #define ARTPEC6_PINMUX_SEL_MASK 0x00003000
  34. #define ARTPEC6_PINMUX_SEL_SHIFT 12
  35. /* Pinmux configurations */
  36. #define ARTPEC6_CONFIG_0 0
  37. #define ARTPEC6_CONFIG_1 1
  38. #define ARTPEC6_CONFIG_2 2
  39. #define ARTPEC6_CONFIG_3 3
  40. /* Pin drive strength options */
  41. #define ARTPEC6_DRIVE_4mA 4
  42. #define ARTPEC6_DRIVE_4mA_SET 0
  43. #define ARTPEC6_DRIVE_6mA 6
  44. #define ARTPEC6_DRIVE_6mA_SET 1
  45. #define ARTPEC6_DRIVE_8mA 8
  46. #define ARTPEC6_DRIVE_8mA_SET 2
  47. #define ARTPEC6_DRIVE_9mA 9
  48. #define ARTPEC6_DRIVE_9mA_SET 3
  49. struct artpec6_pmx {
  50. struct device *dev;
  51. struct pinctrl_dev *pctl;
  52. void __iomem *base;
  53. struct pinctrl_pin_desc *pins;
  54. unsigned int num_pins;
  55. const struct artpec6_pin_group *pin_groups;
  56. unsigned int num_pin_groups;
  57. const struct artpec6_pmx_func *functions;
  58. unsigned int num_functions;
  59. };
  60. struct artpec6_pin_group {
  61. const char *name;
  62. const unsigned int *pins;
  63. const unsigned int num_pins;
  64. unsigned char config;
  65. };
  66. struct artpec6_pmx_func {
  67. const char *name;
  68. const char * const *groups;
  69. const unsigned int num_groups;
  70. };
  71. /* pins */
  72. static struct pinctrl_pin_desc artpec6_pins[] = {
  73. PINCTRL_PIN(0, "GPIO0"),
  74. PINCTRL_PIN(1, "GPIO1"),
  75. PINCTRL_PIN(2, "GPIO2"),
  76. PINCTRL_PIN(3, "GPIO3"),
  77. PINCTRL_PIN(4, "GPIO4"),
  78. PINCTRL_PIN(5, "GPIO5"),
  79. PINCTRL_PIN(6, "GPIO6"),
  80. PINCTRL_PIN(7, "GPIO7"),
  81. PINCTRL_PIN(8, "GPIO8"),
  82. PINCTRL_PIN(9, "GPIO9"),
  83. PINCTRL_PIN(10, "GPIO10"),
  84. PINCTRL_PIN(11, "GPIO11"),
  85. PINCTRL_PIN(12, "GPIO12"),
  86. PINCTRL_PIN(13, "GPIO13"),
  87. PINCTRL_PIN(14, "GPIO14"),
  88. PINCTRL_PIN(15, "GPIO15"),
  89. PINCTRL_PIN(16, "GPIO16"),
  90. PINCTRL_PIN(17, "GPIO17"),
  91. PINCTRL_PIN(18, "GPIO18"),
  92. PINCTRL_PIN(19, "GPIO19"),
  93. PINCTRL_PIN(20, "GPIO20"),
  94. PINCTRL_PIN(21, "GPIO21"),
  95. PINCTRL_PIN(22, "GPIO22"),
  96. PINCTRL_PIN(23, "GPIO23"),
  97. PINCTRL_PIN(24, "GPIO24"),
  98. PINCTRL_PIN(25, "GPIO25"),
  99. PINCTRL_PIN(26, "GPIO26"),
  100. PINCTRL_PIN(27, "GPIO27"),
  101. PINCTRL_PIN(28, "GPIO28"),
  102. PINCTRL_PIN(29, "GPIO29"),
  103. PINCTRL_PIN(30, "GPIO30"),
  104. PINCTRL_PIN(31, "GPIO31"),
  105. PINCTRL_PIN(32, "UART3_TXD"),
  106. PINCTRL_PIN(33, "UART3_RXD"),
  107. PINCTRL_PIN(34, "UART3_RTS"),
  108. PINCTRL_PIN(35, "UART3_CTS"),
  109. PINCTRL_PIN(36, "NF_ALE"),
  110. PINCTRL_PIN(37, "NF_CE0_N"),
  111. PINCTRL_PIN(38, "NF_CE1_N"),
  112. PINCTRL_PIN(39, "NF_CLE"),
  113. PINCTRL_PIN(40, "NF_RE_N"),
  114. PINCTRL_PIN(41, "NF_WE_N"),
  115. PINCTRL_PIN(42, "NF_WP0_N"),
  116. PINCTRL_PIN(43, "NF_WP1_N"),
  117. PINCTRL_PIN(44, "NF_IO0"),
  118. PINCTRL_PIN(45, "NF_IO1"),
  119. PINCTRL_PIN(46, "NF_IO2"),
  120. PINCTRL_PIN(47, "NF_IO3"),
  121. PINCTRL_PIN(48, "NF_IO4"),
  122. PINCTRL_PIN(49, "NF_IO5"),
  123. PINCTRL_PIN(50, "NF_IO6"),
  124. PINCTRL_PIN(51, "NF_IO7"),
  125. PINCTRL_PIN(52, "NF_RB0_N"),
  126. PINCTRL_PIN(53, "SDIO0_CLK"),
  127. PINCTRL_PIN(54, "SDIO0_CMD"),
  128. PINCTRL_PIN(55, "SDIO0_DAT0"),
  129. PINCTRL_PIN(56, "SDIO0_DAT1"),
  130. PINCTRL_PIN(57, "SDIO0_DAT2"),
  131. PINCTRL_PIN(58, "SDIO0_DAT3"),
  132. PINCTRL_PIN(59, "SDI0_CD"),
  133. PINCTRL_PIN(60, "SDI0_WP"),
  134. PINCTRL_PIN(61, "SDIO1_CLK"),
  135. PINCTRL_PIN(62, "SDIO1_CMD"),
  136. PINCTRL_PIN(63, "SDIO1_DAT0"),
  137. PINCTRL_PIN(64, "SDIO1_DAT1"),
  138. PINCTRL_PIN(65, "SDIO1_DAT2"),
  139. PINCTRL_PIN(66, "SDIO1_DAT3"),
  140. PINCTRL_PIN(67, "SDIO1_CD"),
  141. PINCTRL_PIN(68, "SDIO1_WP"),
  142. PINCTRL_PIN(69, "GBE_REFCLk"),
  143. PINCTRL_PIN(70, "GBE_GTX_CLK"),
  144. PINCTRL_PIN(71, "GBE_TX_CLK"),
  145. PINCTRL_PIN(72, "GBE_TX_EN"),
  146. PINCTRL_PIN(73, "GBE_TX_ER"),
  147. PINCTRL_PIN(74, "GBE_TXD0"),
  148. PINCTRL_PIN(75, "GBE_TXD1"),
  149. PINCTRL_PIN(76, "GBE_TXD2"),
  150. PINCTRL_PIN(77, "GBE_TXD3"),
  151. PINCTRL_PIN(78, "GBE_TXD4"),
  152. PINCTRL_PIN(79, "GBE_TXD5"),
  153. PINCTRL_PIN(80, "GBE_TXD6"),
  154. PINCTRL_PIN(81, "GBE_TXD7"),
  155. PINCTRL_PIN(82, "GBE_RX_CLK"),
  156. PINCTRL_PIN(83, "GBE_RX_DV"),
  157. PINCTRL_PIN(84, "GBE_RX_ER"),
  158. PINCTRL_PIN(85, "GBE_RXD0"),
  159. PINCTRL_PIN(86, "GBE_RXD1"),
  160. PINCTRL_PIN(87, "GBE_RXD2"),
  161. PINCTRL_PIN(88, "GBE_RXD3"),
  162. PINCTRL_PIN(89, "GBE_RXD4"),
  163. PINCTRL_PIN(90, "GBE_RXD5"),
  164. PINCTRL_PIN(91, "GBE_RXD6"),
  165. PINCTRL_PIN(92, "GBE_RXD7"),
  166. PINCTRL_PIN(93, "GBE_CRS"),
  167. PINCTRL_PIN(94, "GBE_COL"),
  168. PINCTRL_PIN(95, "GBE_MDC"),
  169. PINCTRL_PIN(96, "GBE_MDIO"),
  170. };
  171. static const unsigned int cpuclkout_pins0[] = { 0 };
  172. static const unsigned int udlclkout_pins0[] = { 1 };
  173. static const unsigned int i2c1_pins0[] = { 2, 3 };
  174. static const unsigned int i2c2_pins0[] = { 4, 5 };
  175. static const unsigned int i2c3_pins0[] = { 6, 7 };
  176. static const unsigned int i2s0_pins0[] = { 8, 9, 10, 11 };
  177. static const unsigned int i2s1_pins0[] = { 12, 13, 14, 15 };
  178. static const unsigned int i2srefclk_pins0[] = { 19 };
  179. static const unsigned int spi0_pins0[] = { 12, 13, 14, 15 };
  180. static const unsigned int spi1_pins0[] = { 16, 17, 18, 19 };
  181. static const unsigned int pciedebug_pins0[] = { 12, 13, 14, 15 };
  182. static const unsigned int uart0_pins0[] = { 16, 17, 18, 19, 20,
  183. 21, 22, 23, 24, 25 };
  184. static const unsigned int uart0_pins1[] = { 20, 21, 22, 23 };
  185. static const unsigned int uart1_pins0[] = { 24, 25, 26, 27 };
  186. static const unsigned int uart2_pins0[] = { 26, 27, 28, 29, 30,
  187. 31, 32, 33, 34, 35 };
  188. static const unsigned int uart2_pins1[] = { 28, 29, 30, 31 };
  189. static const unsigned int uart3_pins0[] = { 32, 33, 34, 35 };
  190. static const unsigned int uart4_pins0[] = { 20, 21, 22, 23 };
  191. static const unsigned int uart5_pins0[] = { 28, 29, 30, 31 };
  192. static const unsigned int nand_pins0[] = { 36, 37, 38, 39, 40, 41,
  193. 42, 43, 44, 45, 46, 47,
  194. 48, 49, 50, 51, 52 };
  195. static const unsigned int sdio0_pins0[] = { 53, 54, 55, 56, 57, 58, 59, 60 };
  196. static const unsigned int sdio1_pins0[] = { 61, 62, 63, 64, 65, 66, 67, 68 };
  197. static const unsigned int ethernet_pins0[] = { 69, 70, 71, 72, 73, 74, 75,
  198. 76, 77, 78, 79, 80, 81, 82,
  199. 83, 84, 85, 86, 87, 88, 89,
  200. 90, 91, 92, 93, 94, 95, 96 };
  201. static const struct artpec6_pin_group artpec6_pin_groups[] = {
  202. {
  203. .name = "cpuclkoutgrp0",
  204. .pins = cpuclkout_pins0,
  205. .num_pins = ARRAY_SIZE(cpuclkout_pins0),
  206. .config = ARTPEC6_CONFIG_1,
  207. },
  208. {
  209. .name = "udlclkoutgrp0",
  210. .pins = udlclkout_pins0,
  211. .num_pins = ARRAY_SIZE(udlclkout_pins0),
  212. .config = ARTPEC6_CONFIG_1,
  213. },
  214. {
  215. .name = "i2c1grp0",
  216. .pins = i2c1_pins0,
  217. .num_pins = ARRAY_SIZE(i2c1_pins0),
  218. .config = ARTPEC6_CONFIG_1,
  219. },
  220. {
  221. .name = "i2c2grp0",
  222. .pins = i2c2_pins0,
  223. .num_pins = ARRAY_SIZE(i2c2_pins0),
  224. .config = ARTPEC6_CONFIG_1,
  225. },
  226. {
  227. .name = "i2c3grp0",
  228. .pins = i2c3_pins0,
  229. .num_pins = ARRAY_SIZE(i2c3_pins0),
  230. .config = ARTPEC6_CONFIG_1,
  231. },
  232. {
  233. .name = "i2s0grp0",
  234. .pins = i2s0_pins0,
  235. .num_pins = ARRAY_SIZE(i2s0_pins0),
  236. .config = ARTPEC6_CONFIG_1,
  237. },
  238. {
  239. .name = "i2s1grp0",
  240. .pins = i2s1_pins0,
  241. .num_pins = ARRAY_SIZE(i2s1_pins0),
  242. .config = ARTPEC6_CONFIG_1,
  243. },
  244. {
  245. .name = "i2srefclkgrp0",
  246. .pins = i2srefclk_pins0,
  247. .num_pins = ARRAY_SIZE(i2srefclk_pins0),
  248. .config = ARTPEC6_CONFIG_3,
  249. },
  250. {
  251. .name = "spi0grp0",
  252. .pins = spi0_pins0,
  253. .num_pins = ARRAY_SIZE(spi0_pins0),
  254. .config = ARTPEC6_CONFIG_2,
  255. },
  256. {
  257. .name = "spi1grp0",
  258. .pins = spi1_pins0,
  259. .num_pins = ARRAY_SIZE(spi1_pins0),
  260. .config = ARTPEC6_CONFIG_2,
  261. },
  262. {
  263. .name = "pciedebuggrp0",
  264. .pins = pciedebug_pins0,
  265. .num_pins = ARRAY_SIZE(pciedebug_pins0),
  266. .config = ARTPEC6_CONFIG_3,
  267. },
  268. {
  269. .name = "uart0grp0", /* All pins. */
  270. .pins = uart0_pins0,
  271. .num_pins = ARRAY_SIZE(uart0_pins0),
  272. .config = ARTPEC6_CONFIG_1,
  273. },
  274. {
  275. .name = "uart0grp1", /* RX/TX and RTS/CTS */
  276. .pins = uart0_pins1,
  277. .num_pins = ARRAY_SIZE(uart0_pins1),
  278. .config = ARTPEC6_CONFIG_1,
  279. },
  280. {
  281. .name = "uart0grp2", /* Only RX/TX pins. */
  282. .pins = uart0_pins1,
  283. .num_pins = ARRAY_SIZE(uart0_pins1) - 2,
  284. .config = ARTPEC6_CONFIG_1,
  285. },
  286. {
  287. .name = "uart1grp0", /* RX/TX and RTS/CTS */
  288. .pins = uart1_pins0,
  289. .num_pins = ARRAY_SIZE(uart1_pins0),
  290. .config = ARTPEC6_CONFIG_2,
  291. },
  292. {
  293. .name = "uart1grp1", /* Only RX/TX pins. */
  294. .pins = uart1_pins0,
  295. .num_pins = 2,
  296. .config = ARTPEC6_CONFIG_2,
  297. },
  298. {
  299. .name = "uart2grp0", /* Full pinout */
  300. .pins = uart2_pins0,
  301. .num_pins = ARRAY_SIZE(uart2_pins0),
  302. .config = ARTPEC6_CONFIG_1,
  303. },
  304. {
  305. .name = "uart2grp1", /* RX/TX and RTS/CTS */
  306. .pins = uart2_pins1,
  307. .num_pins = ARRAY_SIZE(uart2_pins1),
  308. .config = ARTPEC6_CONFIG_1,
  309. },
  310. {
  311. .name = "uart2grp2", /* Only RX/TX */
  312. .pins = uart2_pins1,
  313. .num_pins = 2,
  314. .config = ARTPEC6_CONFIG_1,
  315. },
  316. {
  317. .name = "uart3grp0", /* RX/TX and CTS/RTS */
  318. .pins = uart3_pins0,
  319. .num_pins = ARRAY_SIZE(uart3_pins0),
  320. .config = ARTPEC6_CONFIG_0,
  321. },
  322. {
  323. .name = "uart3grp1", /* Only RX/TX */
  324. .pins = uart3_pins0,
  325. .num_pins = ARRAY_SIZE(uart3_pins0),
  326. .config = ARTPEC6_CONFIG_0,
  327. },
  328. {
  329. .name = "uart4grp0",
  330. .pins = uart4_pins0,
  331. .num_pins = ARRAY_SIZE(uart4_pins0),
  332. .config = ARTPEC6_CONFIG_2,
  333. },
  334. {
  335. .name = "uart5grp0", /* TX/RX and RTS/CTS */
  336. .pins = uart5_pins0,
  337. .num_pins = ARRAY_SIZE(uart5_pins0),
  338. .config = ARTPEC6_CONFIG_2,
  339. },
  340. {
  341. .name = "uart5grp1", /* Only TX/RX */
  342. .pins = uart5_pins0,
  343. .num_pins = 2,
  344. .config = ARTPEC6_CONFIG_2,
  345. },
  346. {
  347. .name = "uart5nocts", /* TX/RX/RTS */
  348. .pins = uart5_pins0,
  349. .num_pins = ARRAY_SIZE(uart5_pins0) - 1,
  350. .config = ARTPEC6_CONFIG_2,
  351. },
  352. {
  353. .name = "nandgrp0",
  354. .pins = nand_pins0,
  355. .num_pins = ARRAY_SIZE(nand_pins0),
  356. .config = ARTPEC6_CONFIG_0,
  357. },
  358. {
  359. .name = "sdio0grp0",
  360. .pins = sdio0_pins0,
  361. .num_pins = ARRAY_SIZE(sdio0_pins0),
  362. .config = ARTPEC6_CONFIG_0,
  363. },
  364. {
  365. .name = "sdio1grp0",
  366. .pins = sdio1_pins0,
  367. .num_pins = ARRAY_SIZE(sdio1_pins0),
  368. .config = ARTPEC6_CONFIG_0,
  369. },
  370. {
  371. .name = "ethernetgrp0",
  372. .pins = ethernet_pins0,
  373. .num_pins = ARRAY_SIZE(ethernet_pins0),
  374. .config = ARTPEC6_CONFIG_0,
  375. },
  376. };
  377. struct pin_register {
  378. unsigned int start;
  379. unsigned int end;
  380. unsigned int reg_base;
  381. };
  382. /*
  383. * The register map has two holes where the pin number
  384. * no longer fits directly with the register offset.
  385. * This table allows us to map this easily.
  386. */
  387. static const struct pin_register pin_register[] = {
  388. { 0, 35, 0x0 }, /* 0x0 - 0x8c */
  389. { 36, 52, 0x100 }, /* 0x100 - 0x140 */
  390. { 53, 96, 0x180 }, /* 0x180 - 0x22c */
  391. };
  392. static unsigned int artpec6_pmx_reg_offset(unsigned int pin)
  393. {
  394. int i;
  395. for (i = 0; i < ARRAY_SIZE(pin_register); i++) {
  396. if (pin <= pin_register[i].end) {
  397. return (pin - pin_register[i].start) * 4 +
  398. pin_register[i].reg_base;
  399. }
  400. }
  401. /*
  402. * Anything we return here is wrong, but we can only
  403. * get here if pin is outside registered range.
  404. */
  405. pr_err("%s: Impossible pin %d\n", __func__, pin);
  406. return 0;
  407. }
  408. static int artpec6_get_groups_count(struct pinctrl_dev *pctldev)
  409. {
  410. return ARRAY_SIZE(artpec6_pin_groups);
  411. }
  412. static const char *artpec6_get_group_name(struct pinctrl_dev *pctldev,
  413. unsigned int group)
  414. {
  415. return artpec6_pin_groups[group].name;
  416. }
  417. static int artpec6_get_group_pins(struct pinctrl_dev *pctldev,
  418. unsigned int group,
  419. const unsigned int **pins,
  420. unsigned int *num_pins)
  421. {
  422. *pins = (unsigned int *)artpec6_pin_groups[group].pins;
  423. *num_pins = artpec6_pin_groups[group].num_pins;
  424. return 0;
  425. }
  426. static int artpec6_pconf_drive_mA_to_field(unsigned int mA)
  427. {
  428. switch (mA) {
  429. case ARTPEC6_DRIVE_4mA:
  430. return ARTPEC6_DRIVE_4mA_SET;
  431. case ARTPEC6_DRIVE_6mA:
  432. return ARTPEC6_DRIVE_6mA_SET;
  433. case ARTPEC6_DRIVE_8mA:
  434. return ARTPEC6_DRIVE_8mA_SET;
  435. case ARTPEC6_DRIVE_9mA:
  436. return ARTPEC6_DRIVE_9mA_SET;
  437. default:
  438. return -EINVAL;
  439. }
  440. }
  441. static unsigned int artpec6_pconf_drive_field_to_mA(int field)
  442. {
  443. switch (field) {
  444. case ARTPEC6_DRIVE_4mA_SET:
  445. return ARTPEC6_DRIVE_4mA;
  446. case ARTPEC6_DRIVE_6mA_SET:
  447. return ARTPEC6_DRIVE_6mA;
  448. case ARTPEC6_DRIVE_8mA_SET:
  449. return ARTPEC6_DRIVE_8mA;
  450. case ARTPEC6_DRIVE_9mA_SET:
  451. return ARTPEC6_DRIVE_9mA;
  452. default:
  453. /* Shouldn't happen */
  454. return 0;
  455. }
  456. }
  457. static const struct pinctrl_ops artpec6_pctrl_ops = {
  458. .get_group_pins = artpec6_get_group_pins,
  459. .get_groups_count = artpec6_get_groups_count,
  460. .get_group_name = artpec6_get_group_name,
  461. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  462. .dt_free_map = pinctrl_utils_free_map,
  463. };
  464. static const char * const gpiogrps[] = {
  465. "cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0",
  466. "i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0",
  467. "spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0",
  468. "uart0grp1", "uart0grp2", "uart1grp0", "uart1grp1",
  469. "uart2grp0", "uart2grp1", "uart2grp2", "uart4grp0", "uart5grp0",
  470. "uart5grp1", "uart5nocts",
  471. };
  472. static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" };
  473. static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" };
  474. static const char * const i2c1grps[] = { "i2c1grp0" };
  475. static const char * const i2c2grps[] = { "i2c2grp0" };
  476. static const char * const i2c3grps[] = { "i2c3grp0" };
  477. static const char * const i2s0grps[] = { "i2s0grp0" };
  478. static const char * const i2s1grps[] = { "i2s1grp0" };
  479. static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" };
  480. static const char * const spi0grps[] = { "spi0grp0" };
  481. static const char * const spi1grps[] = { "spi1grp0" };
  482. static const char * const pciedebuggrps[] = { "pciedebuggrp0" };
  483. static const char * const uart0grps[] = { "uart0grp0", "uart0grp1",
  484. "uart0grp2" };
  485. static const char * const uart1grps[] = { "uart1grp0", "uart1grp1" };
  486. static const char * const uart2grps[] = { "uart2grp0", "uart2grp1",
  487. "uart2grp2" };
  488. static const char * const uart3grps[] = { "uart3grp0" };
  489. static const char * const uart4grps[] = { "uart4grp0", "uart4grp1" };
  490. static const char * const uart5grps[] = { "uart5grp0", "uart5grp1",
  491. "uart5nocts" };
  492. static const char * const nandgrps[] = { "nandgrp0" };
  493. static const char * const sdio0grps[] = { "sdio0grp0" };
  494. static const char * const sdio1grps[] = { "sdio1grp0" };
  495. static const char * const ethernetgrps[] = { "ethernetgrp0" };
  496. static const struct artpec6_pmx_func artpec6_pmx_functions[] = {
  497. {
  498. .name = "gpio",
  499. .groups = gpiogrps,
  500. .num_groups = ARRAY_SIZE(gpiogrps),
  501. },
  502. {
  503. .name = "cpuclkout",
  504. .groups = cpuclkoutgrps,
  505. .num_groups = ARRAY_SIZE(cpuclkoutgrps),
  506. },
  507. {
  508. .name = "udlclkout",
  509. .groups = udlclkoutgrps,
  510. .num_groups = ARRAY_SIZE(udlclkoutgrps),
  511. },
  512. {
  513. .name = "i2c1",
  514. .groups = i2c1grps,
  515. .num_groups = ARRAY_SIZE(i2c1grps),
  516. },
  517. {
  518. .name = "i2c2",
  519. .groups = i2c2grps,
  520. .num_groups = ARRAY_SIZE(i2c2grps),
  521. },
  522. {
  523. .name = "i2c3",
  524. .groups = i2c3grps,
  525. .num_groups = ARRAY_SIZE(i2c3grps),
  526. },
  527. {
  528. .name = "i2s0",
  529. .groups = i2s0grps,
  530. .num_groups = ARRAY_SIZE(i2s0grps),
  531. },
  532. {
  533. .name = "i2s1",
  534. .groups = i2s1grps,
  535. .num_groups = ARRAY_SIZE(i2s1grps),
  536. },
  537. {
  538. .name = "i2srefclk",
  539. .groups = i2srefclkgrps,
  540. .num_groups = ARRAY_SIZE(i2srefclkgrps),
  541. },
  542. {
  543. .name = "spi0",
  544. .groups = spi0grps,
  545. .num_groups = ARRAY_SIZE(spi0grps),
  546. },
  547. {
  548. .name = "spi1",
  549. .groups = spi1grps,
  550. .num_groups = ARRAY_SIZE(spi1grps),
  551. },
  552. {
  553. .name = "pciedebug",
  554. .groups = pciedebuggrps,
  555. .num_groups = ARRAY_SIZE(pciedebuggrps),
  556. },
  557. {
  558. .name = "uart0",
  559. .groups = uart0grps,
  560. .num_groups = ARRAY_SIZE(uart0grps),
  561. },
  562. {
  563. .name = "uart1",
  564. .groups = uart1grps,
  565. .num_groups = ARRAY_SIZE(uart1grps),
  566. },
  567. {
  568. .name = "uart2",
  569. .groups = uart2grps,
  570. .num_groups = ARRAY_SIZE(uart2grps),
  571. },
  572. {
  573. .name = "uart3",
  574. .groups = uart3grps,
  575. .num_groups = ARRAY_SIZE(uart3grps),
  576. },
  577. {
  578. .name = "uart4",
  579. .groups = uart4grps,
  580. .num_groups = ARRAY_SIZE(uart4grps),
  581. },
  582. {
  583. .name = "uart5",
  584. .groups = uart5grps,
  585. .num_groups = ARRAY_SIZE(uart5grps),
  586. },
  587. {
  588. .name = "nand",
  589. .groups = nandgrps,
  590. .num_groups = ARRAY_SIZE(nandgrps),
  591. },
  592. {
  593. .name = "sdio0",
  594. .groups = sdio0grps,
  595. .num_groups = ARRAY_SIZE(sdio0grps),
  596. },
  597. {
  598. .name = "sdio1",
  599. .groups = sdio1grps,
  600. .num_groups = ARRAY_SIZE(sdio1grps),
  601. },
  602. {
  603. .name = "ethernet",
  604. .groups = ethernetgrps,
  605. .num_groups = ARRAY_SIZE(ethernetgrps),
  606. },
  607. };
  608. static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev)
  609. {
  610. return ARRAY_SIZE(artpec6_pmx_functions);
  611. }
  612. static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev,
  613. unsigned int function)
  614. {
  615. return artpec6_pmx_functions[function].name;
  616. }
  617. static int artpec6_pmx_get_fgroups(struct pinctrl_dev *pctldev,
  618. unsigned int function,
  619. const char * const **groups,
  620. unsigned int * const num_groups)
  621. {
  622. *groups = artpec6_pmx_functions[function].groups;
  623. *num_groups = artpec6_pmx_functions[function].num_groups;
  624. return 0;
  625. }
  626. static void artpec6_pmx_select_func(struct pinctrl_dev *pctldev,
  627. unsigned int function, unsigned int group,
  628. bool enable)
  629. {
  630. unsigned int regval, val;
  631. unsigned int reg;
  632. int i;
  633. struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  634. for (i = 0; i < artpec6_pin_groups[group].num_pins; i++) {
  635. /*
  636. * Registers for pins above a ARTPEC6_MAX_MUXABLE
  637. * do not have a SEL field and are always selected.
  638. */
  639. if (artpec6_pin_groups[group].pins[i] > ARTPEC6_MAX_MUXABLE)
  640. continue;
  641. if (!strcmp(artpec6_pmx_get_fname(pctldev, function), "gpio")) {
  642. /* GPIO is always config 0 */
  643. val = ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
  644. } else {
  645. if (enable)
  646. val = artpec6_pin_groups[group].config
  647. << ARTPEC6_PINMUX_SEL_SHIFT;
  648. else
  649. val = ARTPEC6_CONFIG_0
  650. << ARTPEC6_PINMUX_SEL_SHIFT;
  651. }
  652. reg = artpec6_pmx_reg_offset(artpec6_pin_groups[group].pins[i]);
  653. regval = readl(pmx->base + reg);
  654. regval &= ~ARTPEC6_PINMUX_SEL_MASK;
  655. regval |= val;
  656. writel(regval, pmx->base + reg);
  657. }
  658. }
  659. static int artpec6_pmx_set(struct pinctrl_dev *pctldev,
  660. unsigned int function,
  661. unsigned int group)
  662. {
  663. struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  664. dev_dbg(pmx->dev, "enabling %s function for pin group %s\n",
  665. artpec6_pmx_get_fname(pctldev, function),
  666. artpec6_get_group_name(pctldev, group));
  667. artpec6_pmx_select_func(pctldev, function, group, true);
  668. return 0;
  669. }
  670. static int artpec6_pmx_request_gpio(struct pinctrl_dev *pctldev,
  671. struct pinctrl_gpio_range *range,
  672. unsigned int pin)
  673. {
  674. struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  675. unsigned int reg = artpec6_pmx_reg_offset(pin);
  676. u32 val;
  677. if (pin >= 32)
  678. return -EINVAL;
  679. val = readl_relaxed(pmx->base + reg);
  680. val &= ~ARTPEC6_PINMUX_SEL_MASK;
  681. val |= ARTPEC6_CONFIG_0 << ARTPEC6_PINMUX_SEL_SHIFT;
  682. writel_relaxed(val, pmx->base + reg);
  683. return 0;
  684. }
  685. static const struct pinmux_ops artpec6_pmx_ops = {
  686. .get_functions_count = artpec6_pmx_get_functions_count,
  687. .get_function_name = artpec6_pmx_get_fname,
  688. .get_function_groups = artpec6_pmx_get_fgroups,
  689. .set_mux = artpec6_pmx_set,
  690. .gpio_request_enable = artpec6_pmx_request_gpio,
  691. };
  692. static int artpec6_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
  693. unsigned long *config)
  694. {
  695. struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  696. enum pin_config_param param = pinconf_to_config_param(*config);
  697. unsigned int regval;
  698. /* Check for valid pin */
  699. if (pin >= pmx->num_pins) {
  700. dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
  701. pmx->pins[pin].name);
  702. return -ENOTSUPP;
  703. }
  704. dev_dbg(pmx->dev, "getting configuration for pin %s\n",
  705. pmx->pins[pin].name);
  706. /* Read pin register values */
  707. regval = readl(pmx->base + artpec6_pmx_reg_offset(pin));
  708. /* If valid, get configuration for parameter */
  709. switch (param) {
  710. case PIN_CONFIG_BIAS_DISABLE:
  711. if (!(regval & ARTPEC6_PINMUX_UDC1_MASK))
  712. return -EINVAL;
  713. break;
  714. case PIN_CONFIG_BIAS_PULL_UP:
  715. case PIN_CONFIG_BIAS_PULL_DOWN:
  716. if (regval & ARTPEC6_PINMUX_UDC1_MASK)
  717. return -EINVAL;
  718. regval = regval & ARTPEC6_PINMUX_UDC0_MASK;
  719. if ((param == PIN_CONFIG_BIAS_PULL_UP && !regval) ||
  720. (param == PIN_CONFIG_BIAS_PULL_DOWN && regval))
  721. return -EINVAL;
  722. break;
  723. case PIN_CONFIG_DRIVE_STRENGTH:
  724. regval = (regval & ARTPEC6_PINMUX_DRV_MASK)
  725. >> ARTPEC6_PINMUX_DRV_SHIFT;
  726. regval = artpec6_pconf_drive_field_to_mA(regval);
  727. *config = pinconf_to_config_packed(param, regval);
  728. break;
  729. default:
  730. return -ENOTSUPP;
  731. }
  732. return 0;
  733. }
  734. /*
  735. * Valid combinations of param and arg:
  736. *
  737. * param arg
  738. * PIN_CONFIG_BIAS_DISABLE: x (disable bias)
  739. * PIN_CONFIG_BIAS_PULL_UP: 1 (pull up bias + enable)
  740. * PIN_CONFIG_BIAS_PULL_DOWN: 1 (pull down bias + enable)
  741. * PIN_CONFIG_DRIVE_STRENGTH: x (4mA, 6mA, 8mA, 9mA)
  742. *
  743. * All other args are invalid. All other params are not supported.
  744. */
  745. static int artpec6_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  746. unsigned long *configs, unsigned int num_configs)
  747. {
  748. struct artpec6_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  749. enum pin_config_param param;
  750. unsigned int arg;
  751. unsigned int regval;
  752. void __iomem *reg;
  753. int i;
  754. /* Check for valid pin */
  755. if (pin >= pmx->num_pins) {
  756. dev_dbg(pmx->dev, "pinconf is not supported for pin %s\n",
  757. pmx->pins[pin].name);
  758. return -ENOTSUPP;
  759. }
  760. dev_dbg(pmx->dev, "setting configuration for pin %s\n",
  761. pmx->pins[pin].name);
  762. reg = pmx->base + artpec6_pmx_reg_offset(pin);
  763. /* For each config */
  764. for (i = 0; i < num_configs; i++) {
  765. int drive;
  766. param = pinconf_to_config_param(configs[i]);
  767. arg = pinconf_to_config_argument(configs[i]);
  768. switch (param) {
  769. case PIN_CONFIG_BIAS_DISABLE:
  770. regval = readl(reg);
  771. regval |= (1 << ARTPEC6_PINMUX_UDC1_SHIFT);
  772. writel(regval, reg);
  773. break;
  774. case PIN_CONFIG_BIAS_PULL_UP:
  775. if (arg != 1) {
  776. dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
  777. __func__, arg);
  778. return -EINVAL;
  779. }
  780. regval = readl(reg);
  781. regval |= (arg << ARTPEC6_PINMUX_UDC0_SHIFT);
  782. regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
  783. writel(regval, reg);
  784. break;
  785. case PIN_CONFIG_BIAS_PULL_DOWN:
  786. if (arg != 1) {
  787. dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
  788. __func__, arg);
  789. return -EINVAL;
  790. }
  791. regval = readl(reg);
  792. regval &= ~(arg << ARTPEC6_PINMUX_UDC0_SHIFT);
  793. regval &= ~ARTPEC6_PINMUX_UDC1_MASK; /* Enable */
  794. writel(regval, reg);
  795. break;
  796. case PIN_CONFIG_DRIVE_STRENGTH:
  797. drive = artpec6_pconf_drive_mA_to_field(arg);
  798. if (drive < 0) {
  799. dev_dbg(pctldev->dev, "%s: arg %u out of range\n",
  800. __func__, arg);
  801. return -EINVAL;
  802. }
  803. regval = readl(reg);
  804. regval &= ~ARTPEC6_PINMUX_DRV_MASK;
  805. regval |= (drive << ARTPEC6_PINMUX_DRV_SHIFT);
  806. writel(regval, reg);
  807. break;
  808. default:
  809. dev_dbg(pmx->dev, "parameter not supported\n");
  810. return -ENOTSUPP;
  811. }
  812. }
  813. return 0;
  814. }
  815. static int artpec6_pconf_group_set(struct pinctrl_dev *pctldev,
  816. unsigned int group, unsigned long *configs,
  817. unsigned int num_configs)
  818. {
  819. unsigned int num_pins, current_pin;
  820. int ret;
  821. dev_dbg(pctldev->dev, "setting group %s configuration\n",
  822. artpec6_get_group_name(pctldev, group));
  823. num_pins = artpec6_pin_groups[group].num_pins;
  824. for (current_pin = 0; current_pin < num_pins; current_pin++) {
  825. ret = artpec6_pconf_set(pctldev,
  826. artpec6_pin_groups[group].pins[current_pin],
  827. configs, num_configs);
  828. if (ret < 0)
  829. return ret;
  830. }
  831. return 0;
  832. }
  833. static const struct pinconf_ops artpec6_pconf_ops = {
  834. .is_generic = true,
  835. .pin_config_get = artpec6_pconf_get,
  836. .pin_config_set = artpec6_pconf_set,
  837. .pin_config_group_set = artpec6_pconf_group_set,
  838. };
  839. static struct pinctrl_desc artpec6_desc = {
  840. .name = "artpec6-pinctrl",
  841. .owner = THIS_MODULE,
  842. .pins = artpec6_pins,
  843. .npins = ARRAY_SIZE(artpec6_pins),
  844. .pctlops = &artpec6_pctrl_ops,
  845. .pmxops = &artpec6_pmx_ops,
  846. .confops = &artpec6_pconf_ops,
  847. };
  848. /* The reset values say 4mA, but we want 8mA as default. */
  849. static void artpec6_pmx_reset(struct artpec6_pmx *pmx)
  850. {
  851. void __iomem *base = pmx->base;
  852. int i;
  853. for (i = 0; i < ARTPEC6_LAST_PIN; i++) {
  854. u32 val;
  855. val = readl_relaxed(base + artpec6_pmx_reg_offset(i));
  856. val &= ~ARTPEC6_PINMUX_DRV_MASK;
  857. val |= ARTPEC6_DRIVE_8mA_SET << ARTPEC6_PINMUX_DRV_SHIFT;
  858. writel_relaxed(val, base + artpec6_pmx_reg_offset(i));
  859. }
  860. }
  861. static int artpec6_pmx_probe(struct platform_device *pdev)
  862. {
  863. struct artpec6_pmx *pmx;
  864. pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
  865. if (!pmx)
  866. return -ENOMEM;
  867. pmx->dev = &pdev->dev;
  868. pmx->base = devm_platform_ioremap_resource(pdev, 0);
  869. if (IS_ERR(pmx->base))
  870. return PTR_ERR(pmx->base);
  871. artpec6_pmx_reset(pmx);
  872. pmx->pins = artpec6_pins;
  873. pmx->num_pins = ARRAY_SIZE(artpec6_pins);
  874. pmx->functions = artpec6_pmx_functions;
  875. pmx->num_functions = ARRAY_SIZE(artpec6_pmx_functions);
  876. pmx->pin_groups = artpec6_pin_groups;
  877. pmx->num_pin_groups = ARRAY_SIZE(artpec6_pin_groups);
  878. pmx->pctl = pinctrl_register(&artpec6_desc, &pdev->dev, pmx);
  879. if (IS_ERR(pmx->pctl)) {
  880. dev_err(&pdev->dev, "could not register pinctrl driver\n");
  881. return PTR_ERR(pmx->pctl);
  882. }
  883. platform_set_drvdata(pdev, pmx);
  884. dev_info(&pdev->dev, "initialised Axis ARTPEC-6 pinctrl driver\n");
  885. return 0;
  886. }
  887. static int artpec6_pmx_remove(struct platform_device *pdev)
  888. {
  889. struct artpec6_pmx *pmx = platform_get_drvdata(pdev);
  890. pinctrl_unregister(pmx->pctl);
  891. return 0;
  892. }
  893. static const struct of_device_id artpec6_pinctrl_match[] = {
  894. { .compatible = "axis,artpec6-pinctrl" },
  895. {},
  896. };
  897. static struct platform_driver artpec6_pmx_driver = {
  898. .driver = {
  899. .name = "artpec6-pinctrl",
  900. .of_match_table = artpec6_pinctrl_match,
  901. },
  902. .probe = artpec6_pmx_probe,
  903. .remove = artpec6_pmx_remove,
  904. };
  905. static int __init artpec6_pmx_init(void)
  906. {
  907. return platform_driver_register(&artpec6_pmx_driver);
  908. }
  909. arch_initcall(artpec6_pmx_init);