pinctrl-paris.c 26 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
  4. * bindings for MediaTek SoC.
  5. *
  6. * Copyright (C) 2018 MediaTek Inc.
  7. * Author: Sean Wang <sean.wang@mediatek.com>
  8. * Zhiyong Tao <zhiyong.tao@mediatek.com>
  9. * Hongzhou.Yang <hongzhou.yang@mediatek.com>
  10. */
  11. #include <linux/gpio/driver.h>
  12. #include <linux/module.h>
  13. #include <dt-bindings/pinctrl/mt65xx.h>
  14. #include "pinctrl-paris.h"
  15. #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
  16. /* Custom pinconf parameters */
  17. #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
  18. #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
  19. #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
  20. #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
  21. #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
  22. static const struct pinconf_generic_params mtk_custom_bindings[] = {
  23. {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
  24. {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
  25. {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
  26. {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
  27. {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
  28. };
  29. #ifdef CONFIG_DEBUG_FS
  30. static const struct pin_config_item mtk_conf_items[] = {
  31. PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
  32. PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
  33. PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
  34. PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
  35. PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
  36. };
  37. #endif
  38. static const char * const mtk_gpio_functions[] = {
  39. "func0", "func1", "func2", "func3",
  40. "func4", "func5", "func6", "func7",
  41. "func8", "func9", "func10", "func11",
  42. "func12", "func13", "func14", "func15",
  43. };
  44. static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
  45. struct pinctrl_gpio_range *range,
  46. unsigned int pin)
  47. {
  48. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  49. const struct mtk_pin_desc *desc;
  50. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  51. return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
  52. hw->soc->gpio_m);
  53. }
  54. static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
  55. struct pinctrl_gpio_range *range,
  56. unsigned int pin, bool input)
  57. {
  58. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  59. const struct mtk_pin_desc *desc;
  60. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  61. /* hardware would take 0 as input direction */
  62. return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
  63. }
  64. static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
  65. unsigned int pin, unsigned long *config)
  66. {
  67. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  68. u32 param = pinconf_to_config_param(*config);
  69. int pullup, err, reg, ret = 1;
  70. const struct mtk_pin_desc *desc;
  71. if (pin >= hw->soc->npins) {
  72. err = -EINVAL;
  73. goto out;
  74. }
  75. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  76. switch (param) {
  77. case PIN_CONFIG_BIAS_DISABLE:
  78. case PIN_CONFIG_BIAS_PULL_UP:
  79. case PIN_CONFIG_BIAS_PULL_DOWN:
  80. if (hw->soc->bias_get_combo) {
  81. err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
  82. if (err)
  83. goto out;
  84. if (ret == MTK_PUPD_SET_R1R0_00)
  85. ret = MTK_DISABLE;
  86. if (param == PIN_CONFIG_BIAS_DISABLE) {
  87. if (ret != MTK_DISABLE)
  88. err = -EINVAL;
  89. } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
  90. if (!pullup || ret == MTK_DISABLE)
  91. err = -EINVAL;
  92. } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
  93. if (pullup || ret == MTK_DISABLE)
  94. err = -EINVAL;
  95. }
  96. } else {
  97. err = -ENOTSUPP;
  98. }
  99. break;
  100. case PIN_CONFIG_SLEW_RATE:
  101. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
  102. break;
  103. case PIN_CONFIG_INPUT_ENABLE:
  104. case PIN_CONFIG_OUTPUT_ENABLE:
  105. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
  106. if (err)
  107. goto out;
  108. /* CONFIG Current direction return value
  109. * ------------- ----------------- ----------------------
  110. * OUTPUT_ENABLE output 1 (= HW value)
  111. * input 0 (= HW value)
  112. * INPUT_ENABLE output 0 (= reverse HW value)
  113. * input 1 (= reverse HW value)
  114. */
  115. if (param == PIN_CONFIG_INPUT_ENABLE)
  116. ret = !ret;
  117. break;
  118. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  119. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
  120. if (err)
  121. goto out;
  122. /* return error when in output mode
  123. * because schmitt trigger only work in input mode
  124. */
  125. if (ret) {
  126. err = -EINVAL;
  127. goto out;
  128. }
  129. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
  130. break;
  131. case PIN_CONFIG_DRIVE_STRENGTH:
  132. if (hw->soc->drive_get)
  133. err = hw->soc->drive_get(hw, desc, &ret);
  134. else
  135. err = -ENOTSUPP;
  136. break;
  137. case MTK_PIN_CONFIG_TDSEL:
  138. case MTK_PIN_CONFIG_RDSEL:
  139. reg = (param == MTK_PIN_CONFIG_TDSEL) ?
  140. PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
  141. err = mtk_hw_get_value(hw, desc, reg, &ret);
  142. break;
  143. case MTK_PIN_CONFIG_PU_ADV:
  144. case MTK_PIN_CONFIG_PD_ADV:
  145. if (hw->soc->adv_pull_get) {
  146. pullup = param == MTK_PIN_CONFIG_PU_ADV;
  147. err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
  148. } else
  149. err = -ENOTSUPP;
  150. break;
  151. case MTK_PIN_CONFIG_DRV_ADV:
  152. if (hw->soc->adv_drive_get)
  153. err = hw->soc->adv_drive_get(hw, desc, &ret);
  154. else
  155. err = -ENOTSUPP;
  156. break;
  157. default:
  158. err = -ENOTSUPP;
  159. }
  160. out:
  161. if (!err)
  162. *config = pinconf_to_config_packed(param, ret);
  163. return err;
  164. }
  165. static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  166. enum pin_config_param param, u32 arg)
  167. {
  168. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  169. const struct mtk_pin_desc *desc;
  170. int err = 0;
  171. u32 reg;
  172. if (pin >= hw->soc->npins) {
  173. err = -EINVAL;
  174. goto err;
  175. }
  176. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  177. switch ((u32)param) {
  178. case PIN_CONFIG_BIAS_DISABLE:
  179. if (hw->soc->bias_set_combo)
  180. err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
  181. else
  182. err = -ENOTSUPP;
  183. break;
  184. case PIN_CONFIG_BIAS_PULL_UP:
  185. if (hw->soc->bias_set_combo)
  186. err = hw->soc->bias_set_combo(hw, desc, 1, arg);
  187. else
  188. err = -ENOTSUPP;
  189. break;
  190. case PIN_CONFIG_BIAS_PULL_DOWN:
  191. if (hw->soc->bias_set_combo)
  192. err = hw->soc->bias_set_combo(hw, desc, 0, arg);
  193. else
  194. err = -ENOTSUPP;
  195. break;
  196. case PIN_CONFIG_OUTPUT_ENABLE:
  197. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
  198. MTK_DISABLE);
  199. /* Keep set direction to consider the case that a GPIO pin
  200. * does not have SMT control
  201. */
  202. if (err != -ENOTSUPP)
  203. goto err;
  204. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  205. MTK_OUTPUT);
  206. break;
  207. case PIN_CONFIG_INPUT_ENABLE:
  208. /* regard all non-zero value as enable */
  209. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
  210. if (err)
  211. goto err;
  212. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  213. MTK_INPUT);
  214. break;
  215. case PIN_CONFIG_SLEW_RATE:
  216. /* regard all non-zero value as enable */
  217. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
  218. break;
  219. case PIN_CONFIG_OUTPUT:
  220. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  221. MTK_OUTPUT);
  222. if (err)
  223. goto err;
  224. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
  225. arg);
  226. break;
  227. case PIN_CONFIG_INPUT_SCHMITT:
  228. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  229. /* arg = 1: Input mode & SMT enable ;
  230. * arg = 0: Output mode & SMT disable
  231. */
  232. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
  233. if (err)
  234. goto err;
  235. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
  236. break;
  237. case PIN_CONFIG_DRIVE_STRENGTH:
  238. if (hw->soc->drive_set)
  239. err = hw->soc->drive_set(hw, desc, arg);
  240. else
  241. err = -ENOTSUPP;
  242. break;
  243. case MTK_PIN_CONFIG_TDSEL:
  244. case MTK_PIN_CONFIG_RDSEL:
  245. reg = (param == MTK_PIN_CONFIG_TDSEL) ?
  246. PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
  247. err = mtk_hw_set_value(hw, desc, reg, arg);
  248. break;
  249. case MTK_PIN_CONFIG_PU_ADV:
  250. case MTK_PIN_CONFIG_PD_ADV:
  251. if (hw->soc->adv_pull_set) {
  252. bool pullup;
  253. pullup = param == MTK_PIN_CONFIG_PU_ADV;
  254. err = hw->soc->adv_pull_set(hw, desc, pullup,
  255. arg);
  256. } else
  257. err = -ENOTSUPP;
  258. break;
  259. case MTK_PIN_CONFIG_DRV_ADV:
  260. if (hw->soc->adv_drive_set)
  261. err = hw->soc->adv_drive_set(hw, desc, arg);
  262. else
  263. err = -ENOTSUPP;
  264. break;
  265. default:
  266. err = -ENOTSUPP;
  267. }
  268. err:
  269. return err;
  270. }
  271. static struct mtk_pinctrl_group *
  272. mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
  273. {
  274. int i;
  275. for (i = 0; i < hw->soc->ngrps; i++) {
  276. struct mtk_pinctrl_group *grp = hw->groups + i;
  277. if (grp->pin == pin)
  278. return grp;
  279. }
  280. return NULL;
  281. }
  282. static const struct mtk_func_desc *
  283. mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
  284. {
  285. const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
  286. const struct mtk_func_desc *func = pin->funcs;
  287. while (func && func->name) {
  288. if (func->muxval == fnum)
  289. return func;
  290. func++;
  291. }
  292. return NULL;
  293. }
  294. static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
  295. u32 fnum)
  296. {
  297. int i;
  298. for (i = 0; i < hw->soc->npins; i++) {
  299. const struct mtk_pin_desc *pin = hw->soc->pins + i;
  300. if (pin->number == pin_num) {
  301. const struct mtk_func_desc *func = pin->funcs;
  302. while (func && func->name) {
  303. if (func->muxval == fnum)
  304. return true;
  305. func++;
  306. }
  307. break;
  308. }
  309. }
  310. return false;
  311. }
  312. static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
  313. u32 pin, u32 fnum,
  314. struct mtk_pinctrl_group *grp,
  315. struct pinctrl_map **map,
  316. unsigned *reserved_maps,
  317. unsigned *num_maps)
  318. {
  319. bool ret;
  320. if (*num_maps == *reserved_maps)
  321. return -ENOSPC;
  322. (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
  323. (*map)[*num_maps].data.mux.group = grp->name;
  324. ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
  325. if (!ret) {
  326. dev_err(pctl->dev, "invalid function %d on pin %d .\n",
  327. fnum, pin);
  328. return -EINVAL;
  329. }
  330. (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
  331. (*num_maps)++;
  332. return 0;
  333. }
  334. static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
  335. struct device_node *node,
  336. struct pinctrl_map **map,
  337. unsigned *reserved_maps,
  338. unsigned *num_maps)
  339. {
  340. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  341. int num_pins, num_funcs, maps_per_pin, i, err;
  342. struct mtk_pinctrl_group *grp;
  343. unsigned int num_configs;
  344. bool has_config = false;
  345. unsigned long *configs;
  346. u32 pinfunc, pin, func;
  347. struct property *pins;
  348. unsigned reserve = 0;
  349. pins = of_find_property(node, "pinmux", NULL);
  350. if (!pins) {
  351. dev_err(hw->dev, "missing pins property in node %pOFn .\n",
  352. node);
  353. return -EINVAL;
  354. }
  355. err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
  356. &num_configs);
  357. if (err)
  358. return err;
  359. if (num_configs)
  360. has_config = true;
  361. num_pins = pins->length / sizeof(u32);
  362. num_funcs = num_pins;
  363. maps_per_pin = 0;
  364. if (num_funcs)
  365. maps_per_pin++;
  366. if (has_config && num_pins >= 1)
  367. maps_per_pin++;
  368. if (!num_pins || !maps_per_pin) {
  369. err = -EINVAL;
  370. goto exit;
  371. }
  372. reserve = num_pins * maps_per_pin;
  373. err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
  374. reserve);
  375. if (err < 0)
  376. goto exit;
  377. for (i = 0; i < num_pins; i++) {
  378. err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
  379. if (err)
  380. goto exit;
  381. pin = MTK_GET_PIN_NO(pinfunc);
  382. func = MTK_GET_PIN_FUNC(pinfunc);
  383. if (pin >= hw->soc->npins ||
  384. func >= ARRAY_SIZE(mtk_gpio_functions)) {
  385. dev_err(hw->dev, "invalid pins value.\n");
  386. err = -EINVAL;
  387. goto exit;
  388. }
  389. grp = mtk_pctrl_find_group_by_pin(hw, pin);
  390. if (!grp) {
  391. dev_err(hw->dev, "unable to match pin %d to group\n",
  392. pin);
  393. err = -EINVAL;
  394. goto exit;
  395. }
  396. err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
  397. reserved_maps, num_maps);
  398. if (err < 0)
  399. goto exit;
  400. if (has_config) {
  401. err = pinctrl_utils_add_map_configs(pctldev, map,
  402. reserved_maps,
  403. num_maps,
  404. grp->name,
  405. configs,
  406. num_configs,
  407. PIN_MAP_TYPE_CONFIGS_GROUP);
  408. if (err < 0)
  409. goto exit;
  410. }
  411. }
  412. err = 0;
  413. exit:
  414. kfree(configs);
  415. return err;
  416. }
  417. static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
  418. struct device_node *np_config,
  419. struct pinctrl_map **map,
  420. unsigned *num_maps)
  421. {
  422. struct device_node *np;
  423. unsigned reserved_maps;
  424. int ret;
  425. *map = NULL;
  426. *num_maps = 0;
  427. reserved_maps = 0;
  428. for_each_child_of_node(np_config, np) {
  429. ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
  430. &reserved_maps,
  431. num_maps);
  432. if (ret < 0) {
  433. pinctrl_utils_free_map(pctldev, *map, *num_maps);
  434. of_node_put(np);
  435. return ret;
  436. }
  437. }
  438. return 0;
  439. }
  440. static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
  441. {
  442. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  443. return hw->soc->ngrps;
  444. }
  445. static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
  446. unsigned group)
  447. {
  448. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  449. return hw->groups[group].name;
  450. }
  451. static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
  452. unsigned group, const unsigned **pins,
  453. unsigned *num_pins)
  454. {
  455. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  456. *pins = (unsigned *)&hw->groups[group].pin;
  457. *num_pins = 1;
  458. return 0;
  459. }
  460. static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
  461. {
  462. const struct mtk_pin_desc *desc;
  463. int value, err;
  464. if (gpio >= hw->soc->npins)
  465. return -EINVAL;
  466. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  467. err = mtk_hw_get_value(hw, desc, field, &value);
  468. if (err)
  469. return err;
  470. return value;
  471. }
  472. #define mtk_pctrl_get_pinmux(hw, gpio) \
  473. mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
  474. #define mtk_pctrl_get_direction(hw, gpio) \
  475. mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
  476. #define mtk_pctrl_get_out(hw, gpio) \
  477. mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
  478. #define mtk_pctrl_get_in(hw, gpio) \
  479. mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
  480. #define mtk_pctrl_get_smt(hw, gpio) \
  481. mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
  482. #define mtk_pctrl_get_ies(hw, gpio) \
  483. mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
  484. #define mtk_pctrl_get_driving(hw, gpio) \
  485. mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
  486. ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
  487. unsigned int gpio, char *buf, unsigned int bufLen)
  488. {
  489. int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1;
  490. const struct mtk_pin_desc *desc;
  491. if (gpio >= hw->soc->npins)
  492. return -EINVAL;
  493. if (mtk_is_virt_gpio(hw, gpio))
  494. return -EINVAL;
  495. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  496. pinmux = mtk_pctrl_get_pinmux(hw, gpio);
  497. if (pinmux >= hw->soc->nfuncs)
  498. pinmux -= hw->soc->nfuncs;
  499. mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
  500. if (pullen == MTK_PUPD_SET_R1R0_00) {
  501. pullen = 0;
  502. r1 = 0;
  503. r0 = 0;
  504. } else if (pullen == MTK_PUPD_SET_R1R0_01) {
  505. pullen = 1;
  506. r1 = 0;
  507. r0 = 1;
  508. } else if (pullen == MTK_PUPD_SET_R1R0_10) {
  509. pullen = 1;
  510. r1 = 1;
  511. r0 = 0;
  512. } else if (pullen == MTK_PUPD_SET_R1R0_11) {
  513. pullen = 1;
  514. r1 = 1;
  515. r0 = 1;
  516. } else if (pullen != MTK_DISABLE && pullen != MTK_ENABLE) {
  517. pullen = 0;
  518. }
  519. len += scnprintf(buf + len, bufLen - len,
  520. "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
  521. gpio,
  522. pinmux,
  523. mtk_pctrl_get_direction(hw, gpio),
  524. mtk_pctrl_get_out(hw, gpio),
  525. mtk_pctrl_get_in(hw, gpio),
  526. mtk_pctrl_get_driving(hw, gpio),
  527. mtk_pctrl_get_smt(hw, gpio),
  528. mtk_pctrl_get_ies(hw, gpio),
  529. pullen,
  530. pullup);
  531. if (r1 != -1) {
  532. len += scnprintf(buf + len, bufLen - len, " (%1d %1d)\n",
  533. r1, r0);
  534. } else {
  535. len += scnprintf(buf + len, bufLen - len, "\n");
  536. }
  537. return len;
  538. }
  539. EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin);
  540. #define PIN_DBG_BUF_SZ 96
  541. static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  542. unsigned int gpio)
  543. {
  544. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  545. char buf[PIN_DBG_BUF_SZ];
  546. (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
  547. seq_printf(s, "%s", buf);
  548. }
  549. static const struct pinctrl_ops mtk_pctlops = {
  550. .dt_node_to_map = mtk_pctrl_dt_node_to_map,
  551. .dt_free_map = pinctrl_utils_free_map,
  552. .get_groups_count = mtk_pctrl_get_groups_count,
  553. .get_group_name = mtk_pctrl_get_group_name,
  554. .get_group_pins = mtk_pctrl_get_group_pins,
  555. .pin_dbg_show = mtk_pctrl_dbg_show,
  556. };
  557. static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
  558. {
  559. return ARRAY_SIZE(mtk_gpio_functions);
  560. }
  561. static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
  562. unsigned selector)
  563. {
  564. return mtk_gpio_functions[selector];
  565. }
  566. static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
  567. unsigned function,
  568. const char * const **groups,
  569. unsigned * const num_groups)
  570. {
  571. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  572. *groups = hw->grp_names;
  573. *num_groups = hw->soc->ngrps;
  574. return 0;
  575. }
  576. static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
  577. unsigned function,
  578. unsigned group)
  579. {
  580. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  581. struct mtk_pinctrl_group *grp = hw->groups + group;
  582. const struct mtk_func_desc *desc_func;
  583. const struct mtk_pin_desc *desc;
  584. bool ret;
  585. ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
  586. if (!ret) {
  587. dev_err(hw->dev, "invalid function %d on group %d .\n",
  588. function, group);
  589. return -EINVAL;
  590. }
  591. desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
  592. if (!desc_func)
  593. return -EINVAL;
  594. desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
  595. mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
  596. return 0;
  597. }
  598. static const struct pinmux_ops mtk_pmxops = {
  599. .get_functions_count = mtk_pmx_get_funcs_cnt,
  600. .get_function_name = mtk_pmx_get_func_name,
  601. .get_function_groups = mtk_pmx_get_func_groups,
  602. .set_mux = mtk_pmx_set_mux,
  603. .gpio_set_direction = mtk_pinmux_gpio_set_direction,
  604. .gpio_request_enable = mtk_pinmux_gpio_request_enable,
  605. };
  606. static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
  607. unsigned long *config)
  608. {
  609. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  610. struct mtk_pinctrl_group *grp = &hw->groups[group];
  611. /* One pin per group only */
  612. return mtk_pinconf_get(pctldev, grp->pin, config);
  613. }
  614. static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
  615. unsigned long *configs, unsigned num_configs)
  616. {
  617. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  618. struct mtk_pinctrl_group *grp = &hw->groups[group];
  619. int i, ret;
  620. for (i = 0; i < num_configs; i++) {
  621. ret = mtk_pinconf_set(pctldev, grp->pin,
  622. pinconf_to_config_param(configs[i]),
  623. pinconf_to_config_argument(configs[i]));
  624. if (ret < 0)
  625. return ret;
  626. }
  627. return 0;
  628. }
  629. static const struct pinconf_ops mtk_confops = {
  630. .pin_config_get = mtk_pinconf_get,
  631. .pin_config_group_get = mtk_pconf_group_get,
  632. .pin_config_group_set = mtk_pconf_group_set,
  633. .is_generic = true,
  634. };
  635. static struct pinctrl_desc mtk_desc = {
  636. .name = PINCTRL_PINCTRL_DEV,
  637. .pctlops = &mtk_pctlops,
  638. .pmxops = &mtk_pmxops,
  639. .confops = &mtk_confops,
  640. .owner = THIS_MODULE,
  641. };
  642. static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
  643. {
  644. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  645. const struct mtk_pin_desc *desc;
  646. int value, err;
  647. if (gpio >= hw->soc->npins)
  648. return -EINVAL;
  649. /*
  650. * "Virtual" GPIOs are always and only used for interrupts
  651. * Since they are only used for interrupts, they are always inputs
  652. */
  653. if (mtk_is_virt_gpio(hw, gpio))
  654. return 1;
  655. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  656. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
  657. if (err)
  658. return err;
  659. if (value)
  660. return GPIO_LINE_DIRECTION_OUT;
  661. return GPIO_LINE_DIRECTION_IN;
  662. }
  663. static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
  664. {
  665. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  666. const struct mtk_pin_desc *desc;
  667. int value, err;
  668. if (gpio >= hw->soc->npins)
  669. return -EINVAL;
  670. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  671. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
  672. if (err)
  673. return err;
  674. return !!value;
  675. }
  676. static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
  677. {
  678. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  679. const struct mtk_pin_desc *desc;
  680. if (gpio >= hw->soc->npins)
  681. return;
  682. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  683. mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
  684. }
  685. static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
  686. {
  687. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  688. if (gpio >= hw->soc->npins)
  689. return -EINVAL;
  690. return pinctrl_gpio_direction_input(chip->base + gpio);
  691. }
  692. static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
  693. int value)
  694. {
  695. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  696. if (gpio >= hw->soc->npins)
  697. return -EINVAL;
  698. mtk_gpio_set(chip, gpio, value);
  699. return pinctrl_gpio_direction_output(chip->base + gpio);
  700. }
  701. static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
  702. {
  703. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  704. const struct mtk_pin_desc *desc;
  705. if (!hw->eint)
  706. return -ENOTSUPP;
  707. desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
  708. if (desc->eint.eint_n == EINT_NA)
  709. return -ENOTSUPP;
  710. return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
  711. }
  712. static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  713. unsigned long config)
  714. {
  715. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  716. const struct mtk_pin_desc *desc;
  717. u32 debounce;
  718. desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
  719. if (!hw->eint ||
  720. pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
  721. desc->eint.eint_n == EINT_NA)
  722. return -ENOTSUPP;
  723. debounce = pinconf_to_config_argument(config);
  724. return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
  725. }
  726. static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
  727. {
  728. struct gpio_chip *chip = &hw->chip;
  729. int ret;
  730. chip->label = PINCTRL_PINCTRL_DEV;
  731. chip->parent = hw->dev;
  732. chip->request = gpiochip_generic_request;
  733. chip->free = gpiochip_generic_free;
  734. chip->get_direction = mtk_gpio_get_direction;
  735. chip->direction_input = mtk_gpio_direction_input;
  736. chip->direction_output = mtk_gpio_direction_output;
  737. chip->get = mtk_gpio_get;
  738. chip->set = mtk_gpio_set;
  739. chip->to_irq = mtk_gpio_to_irq,
  740. chip->set_config = mtk_gpio_set_config,
  741. chip->base = -1;
  742. chip->ngpio = hw->soc->npins;
  743. chip->of_node = np;
  744. chip->of_gpio_n_cells = 2;
  745. ret = gpiochip_add_data(chip, hw);
  746. if (ret < 0)
  747. return ret;
  748. return 0;
  749. }
  750. static int mtk_pctrl_build_state(struct platform_device *pdev)
  751. {
  752. struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
  753. int i;
  754. /* Allocate groups */
  755. hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
  756. sizeof(*hw->groups), GFP_KERNEL);
  757. if (!hw->groups)
  758. return -ENOMEM;
  759. /* We assume that one pin is one group, use pin name as group name. */
  760. hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
  761. sizeof(*hw->grp_names), GFP_KERNEL);
  762. if (!hw->grp_names)
  763. return -ENOMEM;
  764. for (i = 0; i < hw->soc->npins; i++) {
  765. const struct mtk_pin_desc *pin = hw->soc->pins + i;
  766. struct mtk_pinctrl_group *group = hw->groups + i;
  767. group->name = pin->name;
  768. group->pin = pin->number;
  769. hw->grp_names[i] = pin->name;
  770. }
  771. return 0;
  772. }
  773. int mtk_paris_pinctrl_probe(struct platform_device *pdev,
  774. const struct mtk_pin_soc *soc)
  775. {
  776. struct pinctrl_pin_desc *pins;
  777. struct mtk_pinctrl *hw;
  778. int err, i;
  779. hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
  780. if (!hw)
  781. return -ENOMEM;
  782. platform_set_drvdata(pdev, hw);
  783. hw->soc = soc;
  784. hw->dev = &pdev->dev;
  785. if (!hw->soc->nbase_names) {
  786. dev_err(&pdev->dev,
  787. "SoC should be assigned at least one register base\n");
  788. return -EINVAL;
  789. }
  790. hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
  791. sizeof(*hw->base), GFP_KERNEL);
  792. if (!hw->base)
  793. return -ENOMEM;
  794. for (i = 0; i < hw->soc->nbase_names; i++) {
  795. hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
  796. hw->soc->base_names[i]);
  797. if (IS_ERR(hw->base[i]))
  798. return PTR_ERR(hw->base[i]);
  799. }
  800. hw->nbase = hw->soc->nbase_names;
  801. err = mtk_pctrl_build_state(pdev);
  802. if (err) {
  803. dev_err(&pdev->dev, "build state failed: %d\n", err);
  804. return -EINVAL;
  805. }
  806. /* Copy from internal struct mtk_pin_desc to register to the core */
  807. pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
  808. GFP_KERNEL);
  809. if (!pins)
  810. return -ENOMEM;
  811. for (i = 0; i < hw->soc->npins; i++) {
  812. pins[i].number = hw->soc->pins[i].number;
  813. pins[i].name = hw->soc->pins[i].name;
  814. }
  815. /* Setup pins descriptions per SoC types */
  816. mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
  817. mtk_desc.npins = hw->soc->npins;
  818. mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
  819. mtk_desc.custom_params = mtk_custom_bindings;
  820. #ifdef CONFIG_DEBUG_FS
  821. mtk_desc.custom_conf_items = mtk_conf_items;
  822. #endif
  823. err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
  824. &hw->pctrl);
  825. if (err)
  826. return err;
  827. err = pinctrl_enable(hw->pctrl);
  828. if (err)
  829. return err;
  830. err = mtk_build_eint(hw, pdev);
  831. if (err)
  832. dev_warn(&pdev->dev,
  833. "Failed to add EINT, but pinctrl still can work\n");
  834. /* Build gpiochip should be after pinctrl_enable is done */
  835. err = mtk_build_gpiochip(hw, pdev->dev.of_node);
  836. if (err) {
  837. dev_err(&pdev->dev, "Failed to add gpio_chip\n");
  838. return err;
  839. }
  840. platform_set_drvdata(pdev, hw);
  841. return 0;
  842. }
  843. EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe);
  844. static int mtk_paris_pinctrl_suspend(struct device *device)
  845. {
  846. struct mtk_pinctrl *pctl = dev_get_drvdata(device);
  847. return mtk_eint_do_suspend(pctl->eint);
  848. }
  849. static int mtk_paris_pinctrl_resume(struct device *device)
  850. {
  851. struct mtk_pinctrl *pctl = dev_get_drvdata(device);
  852. return mtk_eint_do_resume(pctl->eint);
  853. }
  854. const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
  855. .suspend_noirq = mtk_paris_pinctrl_suspend,
  856. .resume_noirq = mtk_paris_pinctrl_resume,
  857. };
  858. MODULE_LICENSE("GPL v2");
  859. MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris");