pinctrl-mt8516.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2019 MediaTek Inc.
  4. * Author: Min.Guo <min.guo@mediatek.com>
  5. */
  6. #include <dt-bindings/pinctrl/mt65xx.h>
  7. #include <linux/of.h>
  8. #include <linux/of_device.h>
  9. #include <linux/module.h>
  10. #include <linux/pinctrl/pinctrl.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/regmap.h>
  13. #include "pinctrl-mtk-common.h"
  14. #include "pinctrl-mtk-mt8516.h"
  15. static const struct mtk_drv_group_desc mt8516_drv_grp[] = {
  16. /* 0E4E8SR 4/8/12/16 */
  17. MTK_DRV_GRP(4, 16, 1, 2, 4),
  18. /* 0E2E4SR 2/4/6/8 */
  19. MTK_DRV_GRP(2, 8, 1, 2, 2),
  20. /* E8E4E2 2/4/6/8/10/12/14/16 */
  21. MTK_DRV_GRP(2, 16, 0, 2, 2)
  22. };
  23. static const struct mtk_pin_drv_grp mt8516_pin_drv[] = {
  24. MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
  25. MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
  26. MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
  27. MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
  28. MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
  29. MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
  30. MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
  31. MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
  32. MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
  33. MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
  34. MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
  35. MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
  36. MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
  37. MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
  38. MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
  39. MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
  40. MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
  41. MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
  42. MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
  43. MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
  44. MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
  45. MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
  46. MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
  47. MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
  48. MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
  49. MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
  50. MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
  51. MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
  52. MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
  53. MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
  54. MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
  55. MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
  56. MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
  57. MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
  58. MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
  59. MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
  60. MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
  61. MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
  62. MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
  63. MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
  64. MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
  65. MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
  66. MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
  67. MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
  68. MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
  69. MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
  70. MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
  71. MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
  72. MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
  73. MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
  74. MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
  75. MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
  76. MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
  77. MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
  78. MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
  79. MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
  80. MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
  81. MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
  82. MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
  83. MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
  84. MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
  85. MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
  86. MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
  87. MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
  88. MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
  89. MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
  90. MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
  91. MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
  92. MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
  93. MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
  94. MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
  95. MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
  96. MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
  97. MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
  98. MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
  99. MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
  100. MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
  101. MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
  102. MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
  103. MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
  104. MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
  105. MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
  106. MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
  107. MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
  108. MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
  109. MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
  110. MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
  111. MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
  112. MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
  113. };
  114. static const struct mtk_pin_spec_pupd_set_samereg mt8516_spec_pupd[] = {
  115. MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
  116. MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
  117. MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
  118. MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
  119. MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
  120. MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
  121. MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
  122. MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
  123. MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
  124. MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
  125. MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
  126. MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
  127. MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
  128. MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
  129. MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
  130. MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
  131. MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
  132. MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
  133. MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
  134. MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
  135. MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
  136. MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
  137. MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
  138. MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
  139. MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
  140. MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
  141. MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
  142. MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
  143. MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
  144. MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
  145. MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
  146. MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
  147. MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
  148. MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
  149. };
  150. static int mt8516_spec_pull_set(struct regmap *regmap, unsigned int pin,
  151. unsigned char align, bool isup, unsigned int r1r0)
  152. {
  153. return mtk_pctrl_spec_pull_set_samereg(regmap, mt8516_spec_pupd,
  154. ARRAY_SIZE(mt8516_spec_pupd), pin, align, isup, r1r0);
  155. }
  156. static const struct mtk_pin_ies_smt_set mt8516_ies_set[] = {
  157. MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
  158. MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
  159. MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
  160. MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
  161. MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
  162. MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
  163. MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
  164. MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
  165. MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
  166. MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
  167. MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
  168. MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
  169. MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
  170. MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
  171. MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
  172. MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
  173. MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
  174. MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
  175. MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
  176. MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
  177. MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
  178. MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
  179. MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
  180. MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
  181. MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
  182. MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
  183. MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
  184. MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
  185. MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
  186. MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
  187. MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
  188. MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
  189. MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
  190. MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
  191. MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
  192. MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
  193. MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
  194. MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
  195. MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
  196. MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
  197. MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
  198. MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
  199. MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
  200. MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
  201. MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
  202. MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
  203. };
  204. static const struct mtk_pin_ies_smt_set mt8516_smt_set[] = {
  205. MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
  206. MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
  207. MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
  208. MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
  209. MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
  210. MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
  211. MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
  212. MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
  213. MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
  214. MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
  215. MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
  216. MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
  217. MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
  218. MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
  219. MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
  220. MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
  221. MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
  222. MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
  223. MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
  224. MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
  225. MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
  226. MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
  227. MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
  228. MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
  229. MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
  230. MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
  231. MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
  232. MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
  233. MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
  234. MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
  235. MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
  236. MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
  237. MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
  238. MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
  239. MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
  240. MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
  241. MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
  242. MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
  243. MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
  244. MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
  245. MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
  246. MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
  247. MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
  248. MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
  249. MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
  250. MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
  251. };
  252. static int mt8516_ies_smt_set(struct regmap *regmap, unsigned int pin,
  253. unsigned char align, int value, enum pin_config_param arg)
  254. {
  255. if (arg == PIN_CONFIG_INPUT_ENABLE)
  256. return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_ies_set,
  257. ARRAY_SIZE(mt8516_ies_set), pin, align, value);
  258. else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
  259. return mtk_pconf_spec_set_ies_smt_range(regmap, mt8516_smt_set,
  260. ARRAY_SIZE(mt8516_smt_set), pin, align, value);
  261. return -EINVAL;
  262. }
  263. static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
  264. .pins = mtk_pins_mt8516,
  265. .npins = ARRAY_SIZE(mtk_pins_mt8516),
  266. .grp_desc = mt8516_drv_grp,
  267. .n_grp_cls = ARRAY_SIZE(mt8516_drv_grp),
  268. .pin_drv_grp = mt8516_pin_drv,
  269. .n_pin_drv_grps = ARRAY_SIZE(mt8516_pin_drv),
  270. .spec_pull_set = mt8516_spec_pull_set,
  271. .spec_ies_smt_set = mt8516_ies_smt_set,
  272. .dir_offset = 0x0000,
  273. .pullen_offset = 0x0500,
  274. .pullsel_offset = 0x0600,
  275. .dout_offset = 0x0100,
  276. .din_offset = 0x0200,
  277. .pinmux_offset = 0x0300,
  278. .type1_start = 125,
  279. .type1_end = 125,
  280. .port_shf = 4,
  281. .port_mask = 0xf,
  282. .port_align = 4,
  283. .eint_hw = {
  284. .port_mask = 7,
  285. .ports = 6,
  286. .ap_num = 169,
  287. .db_cnt = 64,
  288. },
  289. };
  290. static int mt8516_pinctrl_probe(struct platform_device *pdev)
  291. {
  292. return mtk_pctrl_init(pdev, &mt8516_pinctrl_data, NULL);
  293. }
  294. static const struct of_device_id mt8516_pctrl_match[] = {
  295. {
  296. .compatible = "mediatek,mt8516-pinctrl",
  297. },
  298. {}
  299. };
  300. MODULE_DEVICE_TABLE(of, mt8516_pctrl_match);
  301. static struct platform_driver mtk_pinctrl_driver = {
  302. .probe = mt8516_pinctrl_probe,
  303. .driver = {
  304. .name = "mediatek-mt8516-pinctrl",
  305. .of_match_table = mt8516_pctrl_match,
  306. .pm = &mtk_eint_pm_ops,
  307. },
  308. };
  309. static int __init mtk_pinctrl_init(void)
  310. {
  311. return platform_driver_register(&mtk_pinctrl_driver);
  312. }
  313. arch_initcall(mtk_pinctrl_init);