pinctrl-moore.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
  4. * pinctrl-bindings.txt for MediaTek SoC.
  5. *
  6. * Copyright (C) 2017-2018 MediaTek Inc.
  7. * Author: Sean Wang <sean.wang@mediatek.com>
  8. *
  9. */
  10. #include <linux/gpio/driver.h>
  11. #include "pinctrl-moore.h"
  12. #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
  13. /* Custom pinconf parameters */
  14. #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
  15. #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
  16. #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
  17. #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
  18. static const struct pinconf_generic_params mtk_custom_bindings[] = {
  19. {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
  20. {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
  21. {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
  22. {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
  23. };
  24. #ifdef CONFIG_DEBUG_FS
  25. static const struct pin_config_item mtk_conf_items[] = {
  26. PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
  27. PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
  28. PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
  29. PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
  30. };
  31. #endif
  32. static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
  33. unsigned int selector, unsigned int group)
  34. {
  35. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  36. struct function_desc *func;
  37. struct group_desc *grp;
  38. int i;
  39. func = pinmux_generic_get_function(pctldev, selector);
  40. if (!func)
  41. return -EINVAL;
  42. grp = pinctrl_generic_get_group(pctldev, group);
  43. if (!grp)
  44. return -EINVAL;
  45. dev_dbg(pctldev->dev, "enable function %s group %s\n",
  46. func->name, grp->name);
  47. for (i = 0; i < grp->num_pins; i++) {
  48. const struct mtk_pin_desc *desc;
  49. int *pin_modes = grp->data;
  50. int pin = grp->pins[i];
  51. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  52. mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
  53. pin_modes[i]);
  54. }
  55. return 0;
  56. }
  57. static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
  58. struct pinctrl_gpio_range *range,
  59. unsigned int pin)
  60. {
  61. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  62. const struct mtk_pin_desc *desc;
  63. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  64. return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
  65. hw->soc->gpio_m);
  66. }
  67. static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
  68. struct pinctrl_gpio_range *range,
  69. unsigned int pin, bool input)
  70. {
  71. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  72. const struct mtk_pin_desc *desc;
  73. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  74. /* hardware would take 0 as input direction */
  75. return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
  76. }
  77. static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
  78. unsigned int pin, unsigned long *config)
  79. {
  80. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  81. u32 param = pinconf_to_config_param(*config);
  82. int val, val2, err, reg, ret = 1;
  83. const struct mtk_pin_desc *desc;
  84. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  85. switch (param) {
  86. case PIN_CONFIG_BIAS_DISABLE:
  87. if (hw->soc->bias_disable_get) {
  88. err = hw->soc->bias_disable_get(hw, desc, &ret);
  89. if (err)
  90. return err;
  91. } else {
  92. return -ENOTSUPP;
  93. }
  94. break;
  95. case PIN_CONFIG_BIAS_PULL_UP:
  96. if (hw->soc->bias_get) {
  97. err = hw->soc->bias_get(hw, desc, 1, &ret);
  98. if (err)
  99. return err;
  100. } else {
  101. return -ENOTSUPP;
  102. }
  103. break;
  104. case PIN_CONFIG_BIAS_PULL_DOWN:
  105. if (hw->soc->bias_get) {
  106. err = hw->soc->bias_get(hw, desc, 0, &ret);
  107. if (err)
  108. return err;
  109. } else {
  110. return -ENOTSUPP;
  111. }
  112. break;
  113. case PIN_CONFIG_SLEW_RATE:
  114. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
  115. if (err)
  116. return err;
  117. if (!val)
  118. return -EINVAL;
  119. break;
  120. case PIN_CONFIG_INPUT_ENABLE:
  121. case PIN_CONFIG_OUTPUT_ENABLE:
  122. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
  123. if (err)
  124. return err;
  125. /* HW takes input mode as zero; output mode as non-zero */
  126. if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
  127. (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
  128. return -EINVAL;
  129. break;
  130. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  131. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
  132. if (err)
  133. return err;
  134. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
  135. if (err)
  136. return err;
  137. if (val || !val2)
  138. return -EINVAL;
  139. break;
  140. case PIN_CONFIG_DRIVE_STRENGTH:
  141. if (hw->soc->drive_get) {
  142. err = hw->soc->drive_get(hw, desc, &ret);
  143. if (err)
  144. return err;
  145. } else {
  146. err = -ENOTSUPP;
  147. }
  148. break;
  149. case MTK_PIN_CONFIG_TDSEL:
  150. case MTK_PIN_CONFIG_RDSEL:
  151. reg = (param == MTK_PIN_CONFIG_TDSEL) ?
  152. PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
  153. err = mtk_hw_get_value(hw, desc, reg, &val);
  154. if (err)
  155. return err;
  156. ret = val;
  157. break;
  158. case MTK_PIN_CONFIG_PU_ADV:
  159. case MTK_PIN_CONFIG_PD_ADV:
  160. if (hw->soc->adv_pull_get) {
  161. bool pullup;
  162. pullup = param == MTK_PIN_CONFIG_PU_ADV;
  163. err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
  164. if (err)
  165. return err;
  166. } else {
  167. return -ENOTSUPP;
  168. }
  169. break;
  170. default:
  171. return -ENOTSUPP;
  172. }
  173. *config = pinconf_to_config_packed(param, ret);
  174. return 0;
  175. }
  176. static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
  177. unsigned long *configs, unsigned int num_configs)
  178. {
  179. struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
  180. const struct mtk_pin_desc *desc;
  181. u32 reg, param, arg;
  182. int cfg, err = 0;
  183. desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
  184. for (cfg = 0; cfg < num_configs; cfg++) {
  185. param = pinconf_to_config_param(configs[cfg]);
  186. arg = pinconf_to_config_argument(configs[cfg]);
  187. switch (param) {
  188. case PIN_CONFIG_BIAS_DISABLE:
  189. if (hw->soc->bias_disable_set) {
  190. err = hw->soc->bias_disable_set(hw, desc);
  191. if (err)
  192. return err;
  193. } else {
  194. return -ENOTSUPP;
  195. }
  196. break;
  197. case PIN_CONFIG_BIAS_PULL_UP:
  198. if (hw->soc->bias_set) {
  199. err = hw->soc->bias_set(hw, desc, 1);
  200. if (err)
  201. return err;
  202. } else {
  203. return -ENOTSUPP;
  204. }
  205. break;
  206. case PIN_CONFIG_BIAS_PULL_DOWN:
  207. if (hw->soc->bias_set) {
  208. err = hw->soc->bias_set(hw, desc, 0);
  209. if (err)
  210. return err;
  211. } else {
  212. return -ENOTSUPP;
  213. }
  214. break;
  215. case PIN_CONFIG_OUTPUT_ENABLE:
  216. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
  217. MTK_DISABLE);
  218. if (err)
  219. goto err;
  220. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  221. MTK_OUTPUT);
  222. if (err)
  223. goto err;
  224. break;
  225. case PIN_CONFIG_INPUT_ENABLE:
  226. if (hw->soc->ies_present) {
  227. mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
  228. MTK_ENABLE);
  229. }
  230. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  231. MTK_INPUT);
  232. if (err)
  233. goto err;
  234. break;
  235. case PIN_CONFIG_SLEW_RATE:
  236. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
  237. arg);
  238. if (err)
  239. goto err;
  240. break;
  241. case PIN_CONFIG_OUTPUT:
  242. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  243. MTK_OUTPUT);
  244. if (err)
  245. goto err;
  246. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
  247. arg);
  248. if (err)
  249. goto err;
  250. break;
  251. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  252. /* arg = 1: Input mode & SMT enable ;
  253. * arg = 0: Output mode & SMT disable
  254. */
  255. arg = arg ? 2 : 1;
  256. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
  257. arg & 1);
  258. if (err)
  259. goto err;
  260. err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
  261. !!(arg & 2));
  262. if (err)
  263. goto err;
  264. break;
  265. case PIN_CONFIG_DRIVE_STRENGTH:
  266. if (hw->soc->drive_set) {
  267. err = hw->soc->drive_set(hw, desc, arg);
  268. if (err)
  269. return err;
  270. } else {
  271. err = -ENOTSUPP;
  272. }
  273. break;
  274. case MTK_PIN_CONFIG_TDSEL:
  275. case MTK_PIN_CONFIG_RDSEL:
  276. reg = (param == MTK_PIN_CONFIG_TDSEL) ?
  277. PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
  278. err = mtk_hw_set_value(hw, desc, reg, arg);
  279. if (err)
  280. goto err;
  281. break;
  282. case MTK_PIN_CONFIG_PU_ADV:
  283. case MTK_PIN_CONFIG_PD_ADV:
  284. if (hw->soc->adv_pull_set) {
  285. bool pullup;
  286. pullup = param == MTK_PIN_CONFIG_PU_ADV;
  287. err = hw->soc->adv_pull_set(hw, desc, pullup,
  288. arg);
  289. if (err)
  290. return err;
  291. } else {
  292. return -ENOTSUPP;
  293. }
  294. break;
  295. default:
  296. err = -ENOTSUPP;
  297. }
  298. }
  299. err:
  300. return err;
  301. }
  302. static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
  303. unsigned int group, unsigned long *config)
  304. {
  305. const unsigned int *pins;
  306. unsigned int i, npins, old = 0;
  307. int ret;
  308. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  309. if (ret)
  310. return ret;
  311. for (i = 0; i < npins; i++) {
  312. if (mtk_pinconf_get(pctldev, pins[i], config))
  313. return -ENOTSUPP;
  314. /* configs do not match between two pins */
  315. if (i && old != *config)
  316. return -ENOTSUPP;
  317. old = *config;
  318. }
  319. return 0;
  320. }
  321. static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
  322. unsigned int group, unsigned long *configs,
  323. unsigned int num_configs)
  324. {
  325. const unsigned int *pins;
  326. unsigned int i, npins;
  327. int ret;
  328. ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
  329. if (ret)
  330. return ret;
  331. for (i = 0; i < npins; i++) {
  332. ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
  333. if (ret)
  334. return ret;
  335. }
  336. return 0;
  337. }
  338. static const struct pinctrl_ops mtk_pctlops = {
  339. .get_groups_count = pinctrl_generic_get_group_count,
  340. .get_group_name = pinctrl_generic_get_group_name,
  341. .get_group_pins = pinctrl_generic_get_group_pins,
  342. .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
  343. .dt_free_map = pinconf_generic_dt_free_map,
  344. };
  345. static const struct pinmux_ops mtk_pmxops = {
  346. .get_functions_count = pinmux_generic_get_function_count,
  347. .get_function_name = pinmux_generic_get_function_name,
  348. .get_function_groups = pinmux_generic_get_function_groups,
  349. .set_mux = mtk_pinmux_set_mux,
  350. .gpio_request_enable = mtk_pinmux_gpio_request_enable,
  351. .gpio_set_direction = mtk_pinmux_gpio_set_direction,
  352. .strict = true,
  353. };
  354. static const struct pinconf_ops mtk_confops = {
  355. .is_generic = true,
  356. .pin_config_get = mtk_pinconf_get,
  357. .pin_config_set = mtk_pinconf_set,
  358. .pin_config_group_get = mtk_pinconf_group_get,
  359. .pin_config_group_set = mtk_pinconf_group_set,
  360. .pin_config_config_dbg_show = pinconf_generic_dump_config,
  361. };
  362. static struct pinctrl_desc mtk_desc = {
  363. .name = PINCTRL_PINCTRL_DEV,
  364. .pctlops = &mtk_pctlops,
  365. .pmxops = &mtk_pmxops,
  366. .confops = &mtk_confops,
  367. .owner = THIS_MODULE,
  368. };
  369. static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
  370. {
  371. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  372. const struct mtk_pin_desc *desc;
  373. int value, err;
  374. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  375. err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
  376. if (err)
  377. return err;
  378. return !!value;
  379. }
  380. static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
  381. {
  382. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  383. const struct mtk_pin_desc *desc;
  384. desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
  385. mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
  386. }
  387. static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
  388. {
  389. return pinctrl_gpio_direction_input(chip->base + gpio);
  390. }
  391. static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
  392. int value)
  393. {
  394. mtk_gpio_set(chip, gpio, value);
  395. return pinctrl_gpio_direction_output(chip->base + gpio);
  396. }
  397. static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
  398. {
  399. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  400. const struct mtk_pin_desc *desc;
  401. if (!hw->eint)
  402. return -ENOTSUPP;
  403. desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
  404. if (desc->eint.eint_n == (u16)EINT_NA)
  405. return -ENOTSUPP;
  406. return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
  407. }
  408. static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
  409. unsigned long config)
  410. {
  411. struct mtk_pinctrl *hw = gpiochip_get_data(chip);
  412. const struct mtk_pin_desc *desc;
  413. u32 debounce;
  414. desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
  415. if (!hw->eint ||
  416. pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
  417. desc->eint.eint_n == (u16)EINT_NA)
  418. return -ENOTSUPP;
  419. debounce = pinconf_to_config_argument(config);
  420. return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
  421. }
  422. static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
  423. {
  424. struct gpio_chip *chip = &hw->chip;
  425. int ret;
  426. chip->label = PINCTRL_PINCTRL_DEV;
  427. chip->parent = hw->dev;
  428. chip->request = gpiochip_generic_request;
  429. chip->free = gpiochip_generic_free;
  430. chip->direction_input = mtk_gpio_direction_input;
  431. chip->direction_output = mtk_gpio_direction_output;
  432. chip->get = mtk_gpio_get;
  433. chip->set = mtk_gpio_set;
  434. chip->to_irq = mtk_gpio_to_irq,
  435. chip->set_config = mtk_gpio_set_config,
  436. chip->base = -1;
  437. chip->ngpio = hw->soc->npins;
  438. chip->of_node = np;
  439. chip->of_gpio_n_cells = 2;
  440. ret = gpiochip_add_data(chip, hw);
  441. if (ret < 0)
  442. return ret;
  443. /* Just for backward compatible for these old pinctrl nodes without
  444. * "gpio-ranges" property. Otherwise, called directly from a
  445. * DeviceTree-supported pinctrl driver is DEPRECATED.
  446. * Please see Section 2.1 of
  447. * Documentation/devicetree/bindings/gpio/gpio.txt on how to
  448. * bind pinctrl and gpio drivers via the "gpio-ranges" property.
  449. */
  450. if (!of_find_property(np, "gpio-ranges", NULL)) {
  451. ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
  452. chip->ngpio);
  453. if (ret < 0) {
  454. gpiochip_remove(chip);
  455. return ret;
  456. }
  457. }
  458. return 0;
  459. }
  460. static int mtk_build_groups(struct mtk_pinctrl *hw)
  461. {
  462. int err, i;
  463. for (i = 0; i < hw->soc->ngrps; i++) {
  464. const struct group_desc *group = hw->soc->grps + i;
  465. err = pinctrl_generic_add_group(hw->pctrl, group->name,
  466. group->pins, group->num_pins,
  467. group->data);
  468. if (err < 0) {
  469. dev_err(hw->dev, "Failed to register group %s\n",
  470. group->name);
  471. return err;
  472. }
  473. }
  474. return 0;
  475. }
  476. static int mtk_build_functions(struct mtk_pinctrl *hw)
  477. {
  478. int i, err;
  479. for (i = 0; i < hw->soc->nfuncs ; i++) {
  480. const struct function_desc *func = hw->soc->funcs + i;
  481. err = pinmux_generic_add_function(hw->pctrl, func->name,
  482. func->group_names,
  483. func->num_group_names,
  484. func->data);
  485. if (err < 0) {
  486. dev_err(hw->dev, "Failed to register function %s\n",
  487. func->name);
  488. return err;
  489. }
  490. }
  491. return 0;
  492. }
  493. int mtk_moore_pinctrl_probe(struct platform_device *pdev,
  494. const struct mtk_pin_soc *soc)
  495. {
  496. struct pinctrl_pin_desc *pins;
  497. struct mtk_pinctrl *hw;
  498. int err, i;
  499. hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
  500. if (!hw)
  501. return -ENOMEM;
  502. hw->soc = soc;
  503. hw->dev = &pdev->dev;
  504. if (!hw->soc->nbase_names) {
  505. dev_err(&pdev->dev,
  506. "SoC should be assigned at least one register base\n");
  507. return -EINVAL;
  508. }
  509. hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
  510. sizeof(*hw->base), GFP_KERNEL);
  511. if (!hw->base)
  512. return -ENOMEM;
  513. for (i = 0; i < hw->soc->nbase_names; i++) {
  514. hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
  515. hw->soc->base_names[i]);
  516. if (IS_ERR(hw->base[i]))
  517. return PTR_ERR(hw->base[i]);
  518. }
  519. hw->nbase = hw->soc->nbase_names;
  520. /* Copy from internal struct mtk_pin_desc to register to the core */
  521. pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
  522. GFP_KERNEL);
  523. if (!pins)
  524. return -ENOMEM;
  525. for (i = 0; i < hw->soc->npins; i++) {
  526. pins[i].number = hw->soc->pins[i].number;
  527. pins[i].name = hw->soc->pins[i].name;
  528. }
  529. /* Setup pins descriptions per SoC types */
  530. mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
  531. mtk_desc.npins = hw->soc->npins;
  532. mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
  533. mtk_desc.custom_params = mtk_custom_bindings;
  534. #ifdef CONFIG_DEBUG_FS
  535. mtk_desc.custom_conf_items = mtk_conf_items;
  536. #endif
  537. err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
  538. &hw->pctrl);
  539. if (err)
  540. return err;
  541. /* Setup groups descriptions per SoC types */
  542. err = mtk_build_groups(hw);
  543. if (err) {
  544. dev_err(&pdev->dev, "Failed to build groups\n");
  545. return err;
  546. }
  547. /* Setup functions descriptions per SoC types */
  548. err = mtk_build_functions(hw);
  549. if (err) {
  550. dev_err(&pdev->dev, "Failed to build functions\n");
  551. return err;
  552. }
  553. /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
  554. * until all groups and functions are being added one.
  555. */
  556. err = pinctrl_enable(hw->pctrl);
  557. if (err)
  558. return err;
  559. err = mtk_build_eint(hw, pdev);
  560. if (err)
  561. dev_warn(&pdev->dev,
  562. "Failed to add EINT, but pinctrl still can work\n");
  563. /* Build gpiochip should be after pinctrl_enable is done */
  564. err = mtk_build_gpiochip(hw, pdev->dev.of_node);
  565. if (err) {
  566. dev_err(&pdev->dev, "Failed to add gpio_chip\n");
  567. return err;
  568. }
  569. platform_set_drvdata(pdev, hw);
  570. return 0;
  571. }