pinctrl-sunrisepoint.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Sunrisepoint PCH pinctrl/GPIO driver
  4. *
  5. * Copyright (C) 2015, Intel Corporation
  6. * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
  7. * Mika Westerberg <mika.westerberg@linux.intel.com>
  8. */
  9. #include <linux/mod_devicetable.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pinctrl/pinctrl.h>
  13. #include "pinctrl-intel.h"
  14. #define SPT_PAD_OWN 0x020
  15. #define SPT_H_PADCFGLOCK 0x090
  16. #define SPT_LP_PADCFGLOCK 0x0a0
  17. #define SPT_HOSTSW_OWN 0x0d0
  18. #define SPT_GPI_IS 0x100
  19. #define SPT_GPI_IE 0x120
  20. #define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \
  21. { \
  22. .barno = (b), \
  23. .padown_offset = SPT_PAD_OWN, \
  24. .padcfglock_offset = (pl), \
  25. .hostown_offset = SPT_HOSTSW_OWN, \
  26. .is_offset = SPT_GPI_IS, \
  27. .ie_offset = SPT_GPI_IE, \
  28. .gpp_size = (gs), \
  29. .gpp_num_padown_regs = (gn), \
  30. .pin_base = (s), \
  31. .npins = ((e) - (s) + 1), \
  32. .gpps = (g), \
  33. .ngpps = (n), \
  34. }
  35. #define SPT_LP_COMMUNITY(b, s, e) \
  36. SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0)
  37. #define SPT_H_GPP(r, s, e, g) \
  38. { \
  39. .reg_num = (r), \
  40. .base = (s), \
  41. .size = ((e) - (s) + 1), \
  42. .gpio_base = (g), \
  43. }
  44. #define SPT_H_COMMUNITY(b, s, e, g) \
  45. SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g))
  46. /* Sunrisepoint-LP */
  47. static const struct pinctrl_pin_desc sptlp_pins[] = {
  48. /* GPP_A */
  49. PINCTRL_PIN(0, "RCINB"),
  50. PINCTRL_PIN(1, "LAD_0"),
  51. PINCTRL_PIN(2, "LAD_1"),
  52. PINCTRL_PIN(3, "LAD_2"),
  53. PINCTRL_PIN(4, "LAD_3"),
  54. PINCTRL_PIN(5, "LFRAMEB"),
  55. PINCTRL_PIN(6, "SERIQ"),
  56. PINCTRL_PIN(7, "PIRQAB"),
  57. PINCTRL_PIN(8, "CLKRUNB"),
  58. PINCTRL_PIN(9, "CLKOUT_LPC_0"),
  59. PINCTRL_PIN(10, "CLKOUT_LPC_1"),
  60. PINCTRL_PIN(11, "PMEB"),
  61. PINCTRL_PIN(12, "BM_BUSYB"),
  62. PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
  63. PINCTRL_PIN(14, "SUS_STATB"),
  64. PINCTRL_PIN(15, "SUSACKB"),
  65. PINCTRL_PIN(16, "SD_1P8_SEL"),
  66. PINCTRL_PIN(17, "SD_PWR_EN_B"),
  67. PINCTRL_PIN(18, "ISH_GP_0"),
  68. PINCTRL_PIN(19, "ISH_GP_1"),
  69. PINCTRL_PIN(20, "ISH_GP_2"),
  70. PINCTRL_PIN(21, "ISH_GP_3"),
  71. PINCTRL_PIN(22, "ISH_GP_4"),
  72. PINCTRL_PIN(23, "ISH_GP_5"),
  73. /* GPP_B */
  74. PINCTRL_PIN(24, "CORE_VID_0"),
  75. PINCTRL_PIN(25, "CORE_VID_1"),
  76. PINCTRL_PIN(26, "VRALERTB"),
  77. PINCTRL_PIN(27, "CPU_GP_2"),
  78. PINCTRL_PIN(28, "CPU_GP_3"),
  79. PINCTRL_PIN(29, "SRCCLKREQB_0"),
  80. PINCTRL_PIN(30, "SRCCLKREQB_1"),
  81. PINCTRL_PIN(31, "SRCCLKREQB_2"),
  82. PINCTRL_PIN(32, "SRCCLKREQB_3"),
  83. PINCTRL_PIN(33, "SRCCLKREQB_4"),
  84. PINCTRL_PIN(34, "SRCCLKREQB_5"),
  85. PINCTRL_PIN(35, "EXT_PWR_GATEB"),
  86. PINCTRL_PIN(36, "SLP_S0B"),
  87. PINCTRL_PIN(37, "PLTRSTB"),
  88. PINCTRL_PIN(38, "SPKR"),
  89. PINCTRL_PIN(39, "GSPI0_CSB"),
  90. PINCTRL_PIN(40, "GSPI0_CLK"),
  91. PINCTRL_PIN(41, "GSPI0_MISO"),
  92. PINCTRL_PIN(42, "GSPI0_MOSI"),
  93. PINCTRL_PIN(43, "GSPI1_CSB"),
  94. PINCTRL_PIN(44, "GSPI1_CLK"),
  95. PINCTRL_PIN(45, "GSPI1_MISO"),
  96. PINCTRL_PIN(46, "GSPI1_MOSI"),
  97. PINCTRL_PIN(47, "SML1ALERTB"),
  98. /* GPP_C */
  99. PINCTRL_PIN(48, "SMBCLK"),
  100. PINCTRL_PIN(49, "SMBDATA"),
  101. PINCTRL_PIN(50, "SMBALERTB"),
  102. PINCTRL_PIN(51, "SML0CLK"),
  103. PINCTRL_PIN(52, "SML0DATA"),
  104. PINCTRL_PIN(53, "SML0ALERTB"),
  105. PINCTRL_PIN(54, "SML1CLK"),
  106. PINCTRL_PIN(55, "SML1DATA"),
  107. PINCTRL_PIN(56, "UART0_RXD"),
  108. PINCTRL_PIN(57, "UART0_TXD"),
  109. PINCTRL_PIN(58, "UART0_RTSB"),
  110. PINCTRL_PIN(59, "UART0_CTSB"),
  111. PINCTRL_PIN(60, "UART1_RXD"),
  112. PINCTRL_PIN(61, "UART1_TXD"),
  113. PINCTRL_PIN(62, "UART1_RTSB"),
  114. PINCTRL_PIN(63, "UART1_CTSB"),
  115. PINCTRL_PIN(64, "I2C0_SDA"),
  116. PINCTRL_PIN(65, "I2C0_SCL"),
  117. PINCTRL_PIN(66, "I2C1_SDA"),
  118. PINCTRL_PIN(67, "I2C1_SCL"),
  119. PINCTRL_PIN(68, "UART2_RXD"),
  120. PINCTRL_PIN(69, "UART2_TXD"),
  121. PINCTRL_PIN(70, "UART2_RTSB"),
  122. PINCTRL_PIN(71, "UART2_CTSB"),
  123. /* GPP_D */
  124. PINCTRL_PIN(72, "SPI1_CSB"),
  125. PINCTRL_PIN(73, "SPI1_CLK"),
  126. PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
  127. PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
  128. PINCTRL_PIN(76, "FLASHTRIG"),
  129. PINCTRL_PIN(77, "ISH_I2C0_SDA"),
  130. PINCTRL_PIN(78, "ISH_I2C0_SCL"),
  131. PINCTRL_PIN(79, "ISH_I2C1_SDA"),
  132. PINCTRL_PIN(80, "ISH_I2C1_SCL"),
  133. PINCTRL_PIN(81, "ISH_SPI_CSB"),
  134. PINCTRL_PIN(82, "ISH_SPI_CLK"),
  135. PINCTRL_PIN(83, "ISH_SPI_MISO"),
  136. PINCTRL_PIN(84, "ISH_SPI_MOSI"),
  137. PINCTRL_PIN(85, "ISH_UART0_RXD"),
  138. PINCTRL_PIN(86, "ISH_UART0_TXD"),
  139. PINCTRL_PIN(87, "ISH_UART0_RTSB"),
  140. PINCTRL_PIN(88, "ISH_UART0_CTSB"),
  141. PINCTRL_PIN(89, "DMIC_CLK_1"),
  142. PINCTRL_PIN(90, "DMIC_DATA_1"),
  143. PINCTRL_PIN(91, "DMIC_CLK_0"),
  144. PINCTRL_PIN(92, "DMIC_DATA_0"),
  145. PINCTRL_PIN(93, "SPI1_IO_2"),
  146. PINCTRL_PIN(94, "SPI1_IO_3"),
  147. PINCTRL_PIN(95, "SSP_MCLK"),
  148. /* GPP_E */
  149. PINCTRL_PIN(96, "SATAXPCIE_0"),
  150. PINCTRL_PIN(97, "SATAXPCIE_1"),
  151. PINCTRL_PIN(98, "SATAXPCIE_2"),
  152. PINCTRL_PIN(99, "CPU_GP_0"),
  153. PINCTRL_PIN(100, "SATA_DEVSLP_0"),
  154. PINCTRL_PIN(101, "SATA_DEVSLP_1"),
  155. PINCTRL_PIN(102, "SATA_DEVSLP_2"),
  156. PINCTRL_PIN(103, "CPU_GP_1"),
  157. PINCTRL_PIN(104, "SATA_LEDB"),
  158. PINCTRL_PIN(105, "USB2_OCB_0"),
  159. PINCTRL_PIN(106, "USB2_OCB_1"),
  160. PINCTRL_PIN(107, "USB2_OCB_2"),
  161. PINCTRL_PIN(108, "USB2_OCB_3"),
  162. PINCTRL_PIN(109, "DDSP_HPD_0"),
  163. PINCTRL_PIN(110, "DDSP_HPD_1"),
  164. PINCTRL_PIN(111, "DDSP_HPD_2"),
  165. PINCTRL_PIN(112, "DDSP_HPD_3"),
  166. PINCTRL_PIN(113, "EDP_HPD"),
  167. PINCTRL_PIN(114, "DDPB_CTRLCLK"),
  168. PINCTRL_PIN(115, "DDPB_CTRLDATA"),
  169. PINCTRL_PIN(116, "DDPC_CTRLCLK"),
  170. PINCTRL_PIN(117, "DDPC_CTRLDATA"),
  171. PINCTRL_PIN(118, "DDPD_CTRLCLK"),
  172. PINCTRL_PIN(119, "DDPD_CTRLDATA"),
  173. /* GPP_F */
  174. PINCTRL_PIN(120, "SSP2_SCLK"),
  175. PINCTRL_PIN(121, "SSP2_SFRM"),
  176. PINCTRL_PIN(122, "SSP2_TXD"),
  177. PINCTRL_PIN(123, "SSP2_RXD"),
  178. PINCTRL_PIN(124, "I2C2_SDA"),
  179. PINCTRL_PIN(125, "I2C2_SCL"),
  180. PINCTRL_PIN(126, "I2C3_SDA"),
  181. PINCTRL_PIN(127, "I2C3_SCL"),
  182. PINCTRL_PIN(128, "I2C4_SDA"),
  183. PINCTRL_PIN(129, "I2C4_SCL"),
  184. PINCTRL_PIN(130, "I2C5_SDA"),
  185. PINCTRL_PIN(131, "I2C5_SCL"),
  186. PINCTRL_PIN(132, "EMMC_CMD"),
  187. PINCTRL_PIN(133, "EMMC_DATA_0"),
  188. PINCTRL_PIN(134, "EMMC_DATA_1"),
  189. PINCTRL_PIN(135, "EMMC_DATA_2"),
  190. PINCTRL_PIN(136, "EMMC_DATA_3"),
  191. PINCTRL_PIN(137, "EMMC_DATA_4"),
  192. PINCTRL_PIN(138, "EMMC_DATA_5"),
  193. PINCTRL_PIN(139, "EMMC_DATA_6"),
  194. PINCTRL_PIN(140, "EMMC_DATA_7"),
  195. PINCTRL_PIN(141, "EMMC_RCLK"),
  196. PINCTRL_PIN(142, "EMMC_CLK"),
  197. PINCTRL_PIN(143, "GPP_F_23"),
  198. /* GPP_G */
  199. PINCTRL_PIN(144, "SD_CMD"),
  200. PINCTRL_PIN(145, "SD_DATA_0"),
  201. PINCTRL_PIN(146, "SD_DATA_1"),
  202. PINCTRL_PIN(147, "SD_DATA_2"),
  203. PINCTRL_PIN(148, "SD_DATA_3"),
  204. PINCTRL_PIN(149, "SD_CDB"),
  205. PINCTRL_PIN(150, "SD_CLK"),
  206. PINCTRL_PIN(151, "SD_WP"),
  207. };
  208. static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
  209. static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
  210. static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
  211. static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
  212. static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
  213. static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
  214. static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
  215. static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
  216. static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
  217. static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
  218. static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
  219. static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
  220. static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
  221. static const unsigned sptlp_emmc_pins[] = {
  222. 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
  223. };
  224. static const unsigned sptlp_sd_pins[] = {
  225. 144, 145, 146, 147, 148, 149, 150, 151,
  226. };
  227. static const struct intel_pingroup sptlp_groups[] = {
  228. PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
  229. PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
  230. PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
  231. PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
  232. PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
  233. PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
  234. PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
  235. PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
  236. PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
  237. PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
  238. PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
  239. PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
  240. PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
  241. PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
  242. PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
  243. };
  244. static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
  245. static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
  246. static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
  247. static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
  248. static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
  249. static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
  250. static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
  251. static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
  252. static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
  253. static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
  254. static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
  255. static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
  256. static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
  257. static const char * const sptlp_sd_groups[] = { "sd_grp" };
  258. static const struct intel_function sptlp_functions[] = {
  259. FUNCTION("spi0", sptlp_spi0_groups),
  260. FUNCTION("spi1", sptlp_spi1_groups),
  261. FUNCTION("uart0", sptlp_uart0_groups),
  262. FUNCTION("uart1", sptlp_uart1_groups),
  263. FUNCTION("uart2", sptlp_uart2_groups),
  264. FUNCTION("i2c0", sptlp_i2c0_groups),
  265. FUNCTION("i2c1", sptlp_i2c1_groups),
  266. FUNCTION("i2c2", sptlp_i2c2_groups),
  267. FUNCTION("i2c3", sptlp_i2c3_groups),
  268. FUNCTION("i2c4", sptlp_i2c4_groups),
  269. FUNCTION("i2c5", sptlp_i2c5_groups),
  270. FUNCTION("ssp2", sptlp_ssp2_groups),
  271. FUNCTION("emmc", sptlp_emmc_groups),
  272. FUNCTION("sd", sptlp_sd_groups),
  273. };
  274. static const struct intel_community sptlp_communities[] = {
  275. SPT_LP_COMMUNITY(0, 0, 47),
  276. SPT_LP_COMMUNITY(1, 48, 119),
  277. SPT_LP_COMMUNITY(2, 120, 151),
  278. };
  279. static const struct intel_pinctrl_soc_data sptlp_soc_data = {
  280. .pins = sptlp_pins,
  281. .npins = ARRAY_SIZE(sptlp_pins),
  282. .groups = sptlp_groups,
  283. .ngroups = ARRAY_SIZE(sptlp_groups),
  284. .functions = sptlp_functions,
  285. .nfunctions = ARRAY_SIZE(sptlp_functions),
  286. .communities = sptlp_communities,
  287. .ncommunities = ARRAY_SIZE(sptlp_communities),
  288. };
  289. /* Sunrisepoint-H */
  290. static const struct pinctrl_pin_desc spth_pins[] = {
  291. /* GPP_A */
  292. PINCTRL_PIN(0, "RCINB"),
  293. PINCTRL_PIN(1, "LAD_0"),
  294. PINCTRL_PIN(2, "LAD_1"),
  295. PINCTRL_PIN(3, "LAD_2"),
  296. PINCTRL_PIN(4, "LAD_3"),
  297. PINCTRL_PIN(5, "LFRAMEB"),
  298. PINCTRL_PIN(6, "SERIQ"),
  299. PINCTRL_PIN(7, "PIRQAB"),
  300. PINCTRL_PIN(8, "CLKRUNB"),
  301. PINCTRL_PIN(9, "CLKOUT_LPC_0"),
  302. PINCTRL_PIN(10, "CLKOUT_LPC_1"),
  303. PINCTRL_PIN(11, "PMEB"),
  304. PINCTRL_PIN(12, "BM_BUSYB"),
  305. PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
  306. PINCTRL_PIN(14, "SUS_STATB"),
  307. PINCTRL_PIN(15, "SUSACKB"),
  308. PINCTRL_PIN(16, "CLKOUT_48"),
  309. PINCTRL_PIN(17, "ISH_GP_7"),
  310. PINCTRL_PIN(18, "ISH_GP_0"),
  311. PINCTRL_PIN(19, "ISH_GP_1"),
  312. PINCTRL_PIN(20, "ISH_GP_2"),
  313. PINCTRL_PIN(21, "ISH_GP_3"),
  314. PINCTRL_PIN(22, "ISH_GP_4"),
  315. PINCTRL_PIN(23, "ISH_GP_5"),
  316. /* GPP_B */
  317. PINCTRL_PIN(24, "CORE_VID_0"),
  318. PINCTRL_PIN(25, "CORE_VID_1"),
  319. PINCTRL_PIN(26, "VRALERTB"),
  320. PINCTRL_PIN(27, "CPU_GP_2"),
  321. PINCTRL_PIN(28, "CPU_GP_3"),
  322. PINCTRL_PIN(29, "SRCCLKREQB_0"),
  323. PINCTRL_PIN(30, "SRCCLKREQB_1"),
  324. PINCTRL_PIN(31, "SRCCLKREQB_2"),
  325. PINCTRL_PIN(32, "SRCCLKREQB_3"),
  326. PINCTRL_PIN(33, "SRCCLKREQB_4"),
  327. PINCTRL_PIN(34, "SRCCLKREQB_5"),
  328. PINCTRL_PIN(35, "EXT_PWR_GATEB"),
  329. PINCTRL_PIN(36, "SLP_S0B"),
  330. PINCTRL_PIN(37, "PLTRSTB"),
  331. PINCTRL_PIN(38, "SPKR"),
  332. PINCTRL_PIN(39, "GSPI0_CSB"),
  333. PINCTRL_PIN(40, "GSPI0_CLK"),
  334. PINCTRL_PIN(41, "GSPI0_MISO"),
  335. PINCTRL_PIN(42, "GSPI0_MOSI"),
  336. PINCTRL_PIN(43, "GSPI1_CSB"),
  337. PINCTRL_PIN(44, "GSPI1_CLK"),
  338. PINCTRL_PIN(45, "GSPI1_MISO"),
  339. PINCTRL_PIN(46, "GSPI1_MOSI"),
  340. PINCTRL_PIN(47, "SML1ALERTB"),
  341. /* GPP_C */
  342. PINCTRL_PIN(48, "SMBCLK"),
  343. PINCTRL_PIN(49, "SMBDATA"),
  344. PINCTRL_PIN(50, "SMBALERTB"),
  345. PINCTRL_PIN(51, "SML0CLK"),
  346. PINCTRL_PIN(52, "SML0DATA"),
  347. PINCTRL_PIN(53, "SML0ALERTB"),
  348. PINCTRL_PIN(54, "SML1CLK"),
  349. PINCTRL_PIN(55, "SML1DATA"),
  350. PINCTRL_PIN(56, "UART0_RXD"),
  351. PINCTRL_PIN(57, "UART0_TXD"),
  352. PINCTRL_PIN(58, "UART0_RTSB"),
  353. PINCTRL_PIN(59, "UART0_CTSB"),
  354. PINCTRL_PIN(60, "UART1_RXD"),
  355. PINCTRL_PIN(61, "UART1_TXD"),
  356. PINCTRL_PIN(62, "UART1_RTSB"),
  357. PINCTRL_PIN(63, "UART1_CTSB"),
  358. PINCTRL_PIN(64, "I2C0_SDA"),
  359. PINCTRL_PIN(65, "I2C0_SCL"),
  360. PINCTRL_PIN(66, "I2C1_SDA"),
  361. PINCTRL_PIN(67, "I2C1_SCL"),
  362. PINCTRL_PIN(68, "UART2_RXD"),
  363. PINCTRL_PIN(69, "UART2_TXD"),
  364. PINCTRL_PIN(70, "UART2_RTSB"),
  365. PINCTRL_PIN(71, "UART2_CTSB"),
  366. /* GPP_D */
  367. PINCTRL_PIN(72, "SPI1_CSB"),
  368. PINCTRL_PIN(73, "SPI1_CLK"),
  369. PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
  370. PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
  371. PINCTRL_PIN(76, "ISH_I2C2_SDA"),
  372. PINCTRL_PIN(77, "SSP0_SFRM"),
  373. PINCTRL_PIN(78, "SSP0_TXD"),
  374. PINCTRL_PIN(79, "SSP0_RXD"),
  375. PINCTRL_PIN(80, "SSP0_SCLK"),
  376. PINCTRL_PIN(81, "ISH_SPI_CSB"),
  377. PINCTRL_PIN(82, "ISH_SPI_CLK"),
  378. PINCTRL_PIN(83, "ISH_SPI_MISO"),
  379. PINCTRL_PIN(84, "ISH_SPI_MOSI"),
  380. PINCTRL_PIN(85, "ISH_UART0_RXD"),
  381. PINCTRL_PIN(86, "ISH_UART0_TXD"),
  382. PINCTRL_PIN(87, "ISH_UART0_RTSB"),
  383. PINCTRL_PIN(88, "ISH_UART0_CTSB"),
  384. PINCTRL_PIN(89, "DMIC_CLK_1"),
  385. PINCTRL_PIN(90, "DMIC_DATA_1"),
  386. PINCTRL_PIN(91, "DMIC_CLK_0"),
  387. PINCTRL_PIN(92, "DMIC_DATA_0"),
  388. PINCTRL_PIN(93, "SPI1_IO_2"),
  389. PINCTRL_PIN(94, "SPI1_IO_3"),
  390. PINCTRL_PIN(95, "ISH_I2C2_SCL"),
  391. /* GPP_E */
  392. PINCTRL_PIN(96, "SATAXPCIE_0"),
  393. PINCTRL_PIN(97, "SATAXPCIE_1"),
  394. PINCTRL_PIN(98, "SATAXPCIE_2"),
  395. PINCTRL_PIN(99, "CPU_GP_0"),
  396. PINCTRL_PIN(100, "SATA_DEVSLP_0"),
  397. PINCTRL_PIN(101, "SATA_DEVSLP_1"),
  398. PINCTRL_PIN(102, "SATA_DEVSLP_2"),
  399. PINCTRL_PIN(103, "CPU_GP_1"),
  400. PINCTRL_PIN(104, "SATA_LEDB"),
  401. PINCTRL_PIN(105, "USB2_OCB_0"),
  402. PINCTRL_PIN(106, "USB2_OCB_1"),
  403. PINCTRL_PIN(107, "USB2_OCB_2"),
  404. PINCTRL_PIN(108, "USB2_OCB_3"),
  405. /* GPP_F */
  406. PINCTRL_PIN(109, "SATAXPCIE_3"),
  407. PINCTRL_PIN(110, "SATAXPCIE_4"),
  408. PINCTRL_PIN(111, "SATAXPCIE_5"),
  409. PINCTRL_PIN(112, "SATAXPCIE_6"),
  410. PINCTRL_PIN(113, "SATAXPCIE_7"),
  411. PINCTRL_PIN(114, "SATA_DEVSLP_3"),
  412. PINCTRL_PIN(115, "SATA_DEVSLP_4"),
  413. PINCTRL_PIN(116, "SATA_DEVSLP_5"),
  414. PINCTRL_PIN(117, "SATA_DEVSLP_6"),
  415. PINCTRL_PIN(118, "SATA_DEVSLP_7"),
  416. PINCTRL_PIN(119, "SATA_SCLOCK"),
  417. PINCTRL_PIN(120, "SATA_SLOAD"),
  418. PINCTRL_PIN(121, "SATA_SDATAOUT1"),
  419. PINCTRL_PIN(122, "SATA_SDATAOUT0"),
  420. PINCTRL_PIN(123, "GPP_F_14"),
  421. PINCTRL_PIN(124, "USB_OCB_4"),
  422. PINCTRL_PIN(125, "USB_OCB_5"),
  423. PINCTRL_PIN(126, "USB_OCB_6"),
  424. PINCTRL_PIN(127, "USB_OCB_7"),
  425. PINCTRL_PIN(128, "L_VDDEN"),
  426. PINCTRL_PIN(129, "L_BKLTEN"),
  427. PINCTRL_PIN(130, "L_BKLTCTL"),
  428. PINCTRL_PIN(131, "GPP_F_22"),
  429. PINCTRL_PIN(132, "GPP_F_23"),
  430. /* GPP_G */
  431. PINCTRL_PIN(133, "FAN_TACH_0"),
  432. PINCTRL_PIN(134, "FAN_TACH_1"),
  433. PINCTRL_PIN(135, "FAN_TACH_2"),
  434. PINCTRL_PIN(136, "FAN_TACH_3"),
  435. PINCTRL_PIN(137, "FAN_TACH_4"),
  436. PINCTRL_PIN(138, "FAN_TACH_5"),
  437. PINCTRL_PIN(139, "FAN_TACH_6"),
  438. PINCTRL_PIN(140, "FAN_TACH_7"),
  439. PINCTRL_PIN(141, "FAN_PWM_0"),
  440. PINCTRL_PIN(142, "FAN_PWM_1"),
  441. PINCTRL_PIN(143, "FAN_PWM_2"),
  442. PINCTRL_PIN(144, "FAN_PWM_3"),
  443. PINCTRL_PIN(145, "GSXDOUT"),
  444. PINCTRL_PIN(146, "GSXSLOAD"),
  445. PINCTRL_PIN(147, "GSXDIN"),
  446. PINCTRL_PIN(148, "GSXRESETB"),
  447. PINCTRL_PIN(149, "GSXCLK"),
  448. PINCTRL_PIN(150, "ADR_COMPLETE"),
  449. PINCTRL_PIN(151, "NMIB"),
  450. PINCTRL_PIN(152, "SMIB"),
  451. PINCTRL_PIN(153, "GPP_G_20"),
  452. PINCTRL_PIN(154, "GPP_G_21"),
  453. PINCTRL_PIN(155, "GPP_G_22"),
  454. PINCTRL_PIN(156, "GPP_G_23"),
  455. /* GPP_H */
  456. PINCTRL_PIN(157, "SRCCLKREQB_6"),
  457. PINCTRL_PIN(158, "SRCCLKREQB_7"),
  458. PINCTRL_PIN(159, "SRCCLKREQB_8"),
  459. PINCTRL_PIN(160, "SRCCLKREQB_9"),
  460. PINCTRL_PIN(161, "SRCCLKREQB_10"),
  461. PINCTRL_PIN(162, "SRCCLKREQB_11"),
  462. PINCTRL_PIN(163, "SRCCLKREQB_12"),
  463. PINCTRL_PIN(164, "SRCCLKREQB_13"),
  464. PINCTRL_PIN(165, "SRCCLKREQB_14"),
  465. PINCTRL_PIN(166, "SRCCLKREQB_15"),
  466. PINCTRL_PIN(167, "SML2CLK"),
  467. PINCTRL_PIN(168, "SML2DATA"),
  468. PINCTRL_PIN(169, "SML2ALERTB"),
  469. PINCTRL_PIN(170, "SML3CLK"),
  470. PINCTRL_PIN(171, "SML3DATA"),
  471. PINCTRL_PIN(172, "SML3ALERTB"),
  472. PINCTRL_PIN(173, "SML4CLK"),
  473. PINCTRL_PIN(174, "SML4DATA"),
  474. PINCTRL_PIN(175, "SML4ALERTB"),
  475. PINCTRL_PIN(176, "ISH_I2C0_SDA"),
  476. PINCTRL_PIN(177, "ISH_I2C0_SCL"),
  477. PINCTRL_PIN(178, "ISH_I2C1_SDA"),
  478. PINCTRL_PIN(179, "ISH_I2C1_SCL"),
  479. PINCTRL_PIN(180, "GPP_H_23"),
  480. /* GPP_I */
  481. PINCTRL_PIN(181, "DDSP_HDP_0"),
  482. PINCTRL_PIN(182, "DDSP_HDP_1"),
  483. PINCTRL_PIN(183, "DDSP_HDP_2"),
  484. PINCTRL_PIN(184, "DDSP_HDP_3"),
  485. PINCTRL_PIN(185, "EDP_HPD"),
  486. PINCTRL_PIN(186, "DDPB_CTRLCLK"),
  487. PINCTRL_PIN(187, "DDPB_CTRLDATA"),
  488. PINCTRL_PIN(188, "DDPC_CTRLCLK"),
  489. PINCTRL_PIN(189, "DDPC_CTRLDATA"),
  490. PINCTRL_PIN(190, "DDPD_CTRLCLK"),
  491. PINCTRL_PIN(191, "DDPD_CTRLDATA"),
  492. };
  493. static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
  494. static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
  495. static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
  496. static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
  497. static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
  498. static const unsigned spth_i2c0_pins[] = { 64, 65 };
  499. static const unsigned spth_i2c1_pins[] = { 66, 67 };
  500. static const unsigned spth_i2c2_pins[] = { 76, 95 };
  501. static const struct intel_pingroup spth_groups[] = {
  502. PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
  503. PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
  504. PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
  505. PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
  506. PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
  507. PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
  508. PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
  509. PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
  510. };
  511. static const char * const spth_spi0_groups[] = { "spi0_grp" };
  512. static const char * const spth_spi1_groups[] = { "spi0_grp" };
  513. static const char * const spth_uart0_groups[] = { "uart0_grp" };
  514. static const char * const spth_uart1_groups[] = { "uart1_grp" };
  515. static const char * const spth_uart2_groups[] = { "uart2_grp" };
  516. static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
  517. static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
  518. static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
  519. static const struct intel_function spth_functions[] = {
  520. FUNCTION("spi0", spth_spi0_groups),
  521. FUNCTION("spi1", spth_spi1_groups),
  522. FUNCTION("uart0", spth_uart0_groups),
  523. FUNCTION("uart1", spth_uart1_groups),
  524. FUNCTION("uart2", spth_uart2_groups),
  525. FUNCTION("i2c0", spth_i2c0_groups),
  526. FUNCTION("i2c1", spth_i2c1_groups),
  527. FUNCTION("i2c2", spth_i2c2_groups),
  528. };
  529. static const struct intel_padgroup spth_community0_gpps[] = {
  530. SPT_H_GPP(0, 0, 23, 0), /* GPP_A */
  531. SPT_H_GPP(1, 24, 47, 24), /* GPP_B */
  532. };
  533. static const struct intel_padgroup spth_community1_gpps[] = {
  534. SPT_H_GPP(0, 48, 71, 48), /* GPP_C */
  535. SPT_H_GPP(1, 72, 95, 72), /* GPP_D */
  536. SPT_H_GPP(2, 96, 108, 96), /* GPP_E */
  537. SPT_H_GPP(3, 109, 132, 120), /* GPP_F */
  538. SPT_H_GPP(4, 133, 156, 144), /* GPP_G */
  539. SPT_H_GPP(5, 157, 180, 168), /* GPP_H */
  540. };
  541. static const struct intel_padgroup spth_community3_gpps[] = {
  542. SPT_H_GPP(0, 181, 191, 192), /* GPP_I */
  543. };
  544. static const struct intel_community spth_communities[] = {
  545. SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps),
  546. SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps),
  547. SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps),
  548. };
  549. static const struct intel_pinctrl_soc_data spth_soc_data = {
  550. .pins = spth_pins,
  551. .npins = ARRAY_SIZE(spth_pins),
  552. .groups = spth_groups,
  553. .ngroups = ARRAY_SIZE(spth_groups),
  554. .functions = spth_functions,
  555. .nfunctions = ARRAY_SIZE(spth_functions),
  556. .communities = spth_communities,
  557. .ncommunities = ARRAY_SIZE(spth_communities),
  558. };
  559. static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
  560. { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
  561. { "INT3451", (kernel_ulong_t)&spth_soc_data },
  562. { "INT345D", (kernel_ulong_t)&spth_soc_data },
  563. { }
  564. };
  565. MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
  566. static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
  567. static struct platform_driver spt_pinctrl_driver = {
  568. .probe = intel_pinctrl_probe_by_hid,
  569. .driver = {
  570. .name = "sunrisepoint-pinctrl",
  571. .acpi_match_table = spt_pinctrl_acpi_match,
  572. .pm = &spt_pinctrl_pm_ops,
  573. },
  574. };
  575. static int __init spt_pinctrl_init(void)
  576. {
  577. return platform_driver_register(&spt_pinctrl_driver);
  578. }
  579. subsys_initcall(spt_pinctrl_init);
  580. static void __exit spt_pinctrl_exit(void)
  581. {
  582. platform_driver_unregister(&spt_pinctrl_driver);
  583. }
  584. module_exit(spt_pinctrl_exit);
  585. MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
  586. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  587. MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
  588. MODULE_LICENSE("GPL v2");