pinctrl-merrifield.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Merrifield SoC pinctrl driver
  4. *
  5. * Copyright (C) 2016, Intel Corporation
  6. * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  7. */
  8. #include <linux/bits.h>
  9. #include <linux/err.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/mod_devicetable.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/pinctrl/pinconf.h>
  15. #include <linux/pinctrl/pinconf-generic.h>
  16. #include <linux/pinctrl/pinctrl.h>
  17. #include <linux/pinctrl/pinmux.h>
  18. #include "pinctrl-intel.h"
  19. #define MRFLD_FAMILY_NR 64
  20. #define MRFLD_FAMILY_LEN 0x400
  21. #define SLEW_OFFSET 0x000
  22. #define BUFCFG_OFFSET 0x100
  23. #define MISC_OFFSET 0x300
  24. #define BUFCFG_PINMODE_SHIFT 0
  25. #define BUFCFG_PINMODE_MASK GENMASK(2, 0)
  26. #define BUFCFG_PINMODE_GPIO 0
  27. #define BUFCFG_PUPD_VAL_SHIFT 4
  28. #define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
  29. #define BUFCFG_PUPD_VAL_2K 0
  30. #define BUFCFG_PUPD_VAL_20K 1
  31. #define BUFCFG_PUPD_VAL_50K 2
  32. #define BUFCFG_PUPD_VAL_910 3
  33. #define BUFCFG_PU_EN BIT(8)
  34. #define BUFCFG_PD_EN BIT(9)
  35. #define BUFCFG_Px_EN_MASK GENMASK(9, 8)
  36. #define BUFCFG_SLEWSEL BIT(10)
  37. #define BUFCFG_OVINEN BIT(12)
  38. #define BUFCFG_OVINEN_EN BIT(13)
  39. #define BUFCFG_OVINEN_MASK GENMASK(13, 12)
  40. #define BUFCFG_OVOUTEN BIT(14)
  41. #define BUFCFG_OVOUTEN_EN BIT(15)
  42. #define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
  43. #define BUFCFG_INDATAOV_VAL BIT(16)
  44. #define BUFCFG_INDATAOV_EN BIT(17)
  45. #define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
  46. #define BUFCFG_OUTDATAOV_VAL BIT(18)
  47. #define BUFCFG_OUTDATAOV_EN BIT(19)
  48. #define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
  49. #define BUFCFG_OD_EN BIT(21)
  50. /**
  51. * struct mrfld_family - Intel pin family description
  52. * @barno: MMIO BAR number where registers for this family reside
  53. * @pin_base: Starting pin of pins in this family
  54. * @npins: Number of pins in this family
  55. * @protected: True if family is protected by access
  56. * @regs: family specific common registers
  57. */
  58. struct mrfld_family {
  59. unsigned int barno;
  60. unsigned int pin_base;
  61. size_t npins;
  62. bool protected;
  63. void __iomem *regs;
  64. };
  65. #define MRFLD_FAMILY(b, s, e) \
  66. { \
  67. .barno = (b), \
  68. .pin_base = (s), \
  69. .npins = (e) - (s) + 1, \
  70. }
  71. #define MRFLD_FAMILY_PROTECTED(b, s, e) \
  72. { \
  73. .barno = (b), \
  74. .pin_base = (s), \
  75. .npins = (e) - (s) + 1, \
  76. .protected = true, \
  77. }
  78. static const struct pinctrl_pin_desc mrfld_pins[] = {
  79. /* Family 0: OCP2SSC (0 pins) */
  80. /* Family 1: ULPI (13 pins) */
  81. PINCTRL_PIN(0, "ULPI_CLK"),
  82. PINCTRL_PIN(1, "ULPI_D0"),
  83. PINCTRL_PIN(2, "ULPI_D1"),
  84. PINCTRL_PIN(3, "ULPI_D2"),
  85. PINCTRL_PIN(4, "ULPI_D3"),
  86. PINCTRL_PIN(5, "ULPI_D4"),
  87. PINCTRL_PIN(6, "ULPI_D5"),
  88. PINCTRL_PIN(7, "ULPI_D6"),
  89. PINCTRL_PIN(8, "ULPI_D7"),
  90. PINCTRL_PIN(9, "ULPI_DIR"),
  91. PINCTRL_PIN(10, "ULPI_NXT"),
  92. PINCTRL_PIN(11, "ULPI_REFCLK"),
  93. PINCTRL_PIN(12, "ULPI_STP"),
  94. /* Family 2: eMMC (24 pins) */
  95. PINCTRL_PIN(13, "EMMC_CLK"),
  96. PINCTRL_PIN(14, "EMMC_CMD"),
  97. PINCTRL_PIN(15, "EMMC_D0"),
  98. PINCTRL_PIN(16, "EMMC_D1"),
  99. PINCTRL_PIN(17, "EMMC_D2"),
  100. PINCTRL_PIN(18, "EMMC_D3"),
  101. PINCTRL_PIN(19, "EMMC_D4"),
  102. PINCTRL_PIN(20, "EMMC_D5"),
  103. PINCTRL_PIN(21, "EMMC_D6"),
  104. PINCTRL_PIN(22, "EMMC_D7"),
  105. PINCTRL_PIN(23, "EMMC_RST_N"),
  106. PINCTRL_PIN(24, "GP154"),
  107. PINCTRL_PIN(25, "GP155"),
  108. PINCTRL_PIN(26, "GP156"),
  109. PINCTRL_PIN(27, "GP157"),
  110. PINCTRL_PIN(28, "GP158"),
  111. PINCTRL_PIN(29, "GP159"),
  112. PINCTRL_PIN(30, "GP160"),
  113. PINCTRL_PIN(31, "GP161"),
  114. PINCTRL_PIN(32, "GP162"),
  115. PINCTRL_PIN(33, "GP163"),
  116. PINCTRL_PIN(34, "GP97"),
  117. PINCTRL_PIN(35, "GP14"),
  118. PINCTRL_PIN(36, "GP15"),
  119. /* Family 3: SDIO (20 pins) */
  120. PINCTRL_PIN(37, "GP77_SD_CD"),
  121. PINCTRL_PIN(38, "GP78_SD_CLK"),
  122. PINCTRL_PIN(39, "GP79_SD_CMD"),
  123. PINCTRL_PIN(40, "GP80_SD_D0"),
  124. PINCTRL_PIN(41, "GP81_SD_D1"),
  125. PINCTRL_PIN(42, "GP82_SD_D2"),
  126. PINCTRL_PIN(43, "GP83_SD_D3"),
  127. PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
  128. PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
  129. PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"),
  130. PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
  131. PINCTRL_PIN(48, "GP87_SD_PD"),
  132. PINCTRL_PIN(49, "GP89_SD_WP"),
  133. PINCTRL_PIN(50, "GP90_SDIO_CLK"),
  134. PINCTRL_PIN(51, "GP91_SDIO_CMD"),
  135. PINCTRL_PIN(52, "GP92_SDIO_D0"),
  136. PINCTRL_PIN(53, "GP93_SDIO_D1"),
  137. PINCTRL_PIN(54, "GP94_SDIO_D2"),
  138. PINCTRL_PIN(55, "GP95_SDIO_D3"),
  139. PINCTRL_PIN(56, "GP96_SDIO_PD"),
  140. /* Family 4: HSI (8 pins) */
  141. PINCTRL_PIN(57, "HSI_ACDATA"),
  142. PINCTRL_PIN(58, "HSI_ACFLAG"),
  143. PINCTRL_PIN(59, "HSI_ACREADY"),
  144. PINCTRL_PIN(60, "HSI_ACWAKE"),
  145. PINCTRL_PIN(61, "HSI_CADATA"),
  146. PINCTRL_PIN(62, "HSI_CAFLAG"),
  147. PINCTRL_PIN(63, "HSI_CAREADY"),
  148. PINCTRL_PIN(64, "HSI_CAWAKE"),
  149. /* Family 5: SSP Audio (14 pins) */
  150. PINCTRL_PIN(65, "GP70"),
  151. PINCTRL_PIN(66, "GP71"),
  152. PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
  153. PINCTRL_PIN(68, "GP33_I2S_0_FS"),
  154. PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
  155. PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
  156. PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
  157. PINCTRL_PIN(72, "GP37_I2S_1_FS"),
  158. PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
  159. PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
  160. PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
  161. PINCTRL_PIN(76, "GP41_I2S_2_FS"),
  162. PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
  163. PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
  164. /* Family 6: GP SSP (22 pins) */
  165. PINCTRL_PIN(79, "GP120_SPI_0_CLK"),
  166. PINCTRL_PIN(80, "GP121_SPI_0_SS"),
  167. PINCTRL_PIN(81, "GP122_SPI_0_RXD"),
  168. PINCTRL_PIN(82, "GP123_SPI_0_TXD"),
  169. PINCTRL_PIN(83, "GP102_SPI_1_CLK"),
  170. PINCTRL_PIN(84, "GP103_SPI_1_SS0"),
  171. PINCTRL_PIN(85, "GP104_SPI_1_SS1"),
  172. PINCTRL_PIN(86, "GP105_SPI_1_SS2"),
  173. PINCTRL_PIN(87, "GP106_SPI_1_SS3"),
  174. PINCTRL_PIN(88, "GP107_SPI_1_RXD"),
  175. PINCTRL_PIN(89, "GP108_SPI_1_TXD"),
  176. PINCTRL_PIN(90, "GP109_SPI_2_CLK"),
  177. PINCTRL_PIN(91, "GP110_SPI_2_SS0"),
  178. PINCTRL_PIN(92, "GP111_SPI_2_SS1"),
  179. PINCTRL_PIN(93, "GP112_SPI_2_SS2"),
  180. PINCTRL_PIN(94, "GP113_SPI_2_SS3"),
  181. PINCTRL_PIN(95, "GP114_SPI_2_RXD"),
  182. PINCTRL_PIN(96, "GP115_SPI_2_TXD"),
  183. PINCTRL_PIN(97, "GP116_SPI_3_CLK"),
  184. PINCTRL_PIN(98, "GP117_SPI_3_SS"),
  185. PINCTRL_PIN(99, "GP118_SPI_3_RXD"),
  186. PINCTRL_PIN(100, "GP119_SPI_3_TXD"),
  187. /* Family 7: I2C (14 pins) */
  188. PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
  189. PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
  190. PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
  191. PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
  192. PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
  193. PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
  194. PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
  195. PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
  196. PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
  197. PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
  198. PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
  199. PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
  200. PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
  201. PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
  202. /* Family 8: UART (12 pins) */
  203. PINCTRL_PIN(115, "GP124_UART_0_CTS"),
  204. PINCTRL_PIN(116, "GP125_UART_0_RTS"),
  205. PINCTRL_PIN(117, "GP126_UART_0_RX"),
  206. PINCTRL_PIN(118, "GP127_UART_0_TX"),
  207. PINCTRL_PIN(119, "GP128_UART_1_CTS"),
  208. PINCTRL_PIN(120, "GP129_UART_1_RTS"),
  209. PINCTRL_PIN(121, "GP130_UART_1_RX"),
  210. PINCTRL_PIN(122, "GP131_UART_1_TX"),
  211. PINCTRL_PIN(123, "GP132_UART_2_CTS"),
  212. PINCTRL_PIN(124, "GP133_UART_2_RTS"),
  213. PINCTRL_PIN(125, "GP134_UART_2_RX"),
  214. PINCTRL_PIN(126, "GP135_UART_2_TX"),
  215. /* Family 9: GPIO South (19 pins) */
  216. PINCTRL_PIN(127, "GP177"),
  217. PINCTRL_PIN(128, "GP178"),
  218. PINCTRL_PIN(129, "GP179"),
  219. PINCTRL_PIN(130, "GP180"),
  220. PINCTRL_PIN(131, "GP181"),
  221. PINCTRL_PIN(132, "GP182_PWM2"),
  222. PINCTRL_PIN(133, "GP183_PWM3"),
  223. PINCTRL_PIN(134, "GP184"),
  224. PINCTRL_PIN(135, "GP185"),
  225. PINCTRL_PIN(136, "GP186"),
  226. PINCTRL_PIN(137, "GP187"),
  227. PINCTRL_PIN(138, "GP188"),
  228. PINCTRL_PIN(139, "GP189"),
  229. PINCTRL_PIN(140, "GP64_FAST_INT0"),
  230. PINCTRL_PIN(141, "GP65_FAST_INT1"),
  231. PINCTRL_PIN(142, "GP66_FAST_INT2"),
  232. PINCTRL_PIN(143, "GP67_FAST_INT3"),
  233. PINCTRL_PIN(144, "GP12_PWM0"),
  234. PINCTRL_PIN(145, "GP13_PWM1"),
  235. /* Family 10: Camera Sideband (12 pins) */
  236. PINCTRL_PIN(146, "GP0"),
  237. PINCTRL_PIN(147, "GP1"),
  238. PINCTRL_PIN(148, "GP2"),
  239. PINCTRL_PIN(149, "GP3"),
  240. PINCTRL_PIN(150, "GP4"),
  241. PINCTRL_PIN(151, "GP5"),
  242. PINCTRL_PIN(152, "GP6"),
  243. PINCTRL_PIN(153, "GP7"),
  244. PINCTRL_PIN(154, "GP8"),
  245. PINCTRL_PIN(155, "GP9"),
  246. PINCTRL_PIN(156, "GP10"),
  247. PINCTRL_PIN(157, "GP11"),
  248. /* Family 11: Clock (22 pins) */
  249. PINCTRL_PIN(158, "GP137"),
  250. PINCTRL_PIN(159, "GP138"),
  251. PINCTRL_PIN(160, "GP139"),
  252. PINCTRL_PIN(161, "GP140"),
  253. PINCTRL_PIN(162, "GP141"),
  254. PINCTRL_PIN(163, "GP142"),
  255. PINCTRL_PIN(164, "GP16_HDMI_HPD"),
  256. PINCTRL_PIN(165, "GP68_DSI_A_TE"),
  257. PINCTRL_PIN(166, "GP69_DSI_C_TE"),
  258. PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
  259. PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
  260. PINCTRL_PIN(169, "OSC_CLK0"),
  261. PINCTRL_PIN(170, "OSC_CLK1"),
  262. PINCTRL_PIN(171, "OSC_CLK2"),
  263. PINCTRL_PIN(172, "OSC_CLK3"),
  264. PINCTRL_PIN(173, "OSC_CLK4"),
  265. PINCTRL_PIN(174, "RESETOUT"),
  266. PINCTRL_PIN(175, "PMODE"),
  267. PINCTRL_PIN(176, "PRDY"),
  268. PINCTRL_PIN(177, "PREQ"),
  269. PINCTRL_PIN(178, "GP190"),
  270. PINCTRL_PIN(179, "GP191"),
  271. /* Family 12: MSIC (15 pins) */
  272. PINCTRL_PIN(180, "I2C_0_SCL"),
  273. PINCTRL_PIN(181, "I2C_0_SDA"),
  274. PINCTRL_PIN(182, "IERR"),
  275. PINCTRL_PIN(183, "JTAG_TCK"),
  276. PINCTRL_PIN(184, "JTAG_TDI"),
  277. PINCTRL_PIN(185, "JTAG_TDO"),
  278. PINCTRL_PIN(186, "JTAG_TMS"),
  279. PINCTRL_PIN(187, "JTAG_TRST"),
  280. PINCTRL_PIN(188, "PROCHOT"),
  281. PINCTRL_PIN(189, "RTC_CLK"),
  282. PINCTRL_PIN(190, "SVID_ALERT"),
  283. PINCTRL_PIN(191, "SVID_CLK"),
  284. PINCTRL_PIN(192, "SVID_D"),
  285. PINCTRL_PIN(193, "THERMTRIP"),
  286. PINCTRL_PIN(194, "STANDBY"),
  287. /* Family 13: Keyboard (20 pins) */
  288. PINCTRL_PIN(195, "GP44"),
  289. PINCTRL_PIN(196, "GP45"),
  290. PINCTRL_PIN(197, "GP46"),
  291. PINCTRL_PIN(198, "GP47"),
  292. PINCTRL_PIN(199, "GP48"),
  293. PINCTRL_PIN(200, "GP49"),
  294. PINCTRL_PIN(201, "GP50"),
  295. PINCTRL_PIN(202, "GP51"),
  296. PINCTRL_PIN(203, "GP52"),
  297. PINCTRL_PIN(204, "GP53"),
  298. PINCTRL_PIN(205, "GP54"),
  299. PINCTRL_PIN(206, "GP55"),
  300. PINCTRL_PIN(207, "GP56"),
  301. PINCTRL_PIN(208, "GP57"),
  302. PINCTRL_PIN(209, "GP58"),
  303. PINCTRL_PIN(210, "GP59"),
  304. PINCTRL_PIN(211, "GP60"),
  305. PINCTRL_PIN(212, "GP61"),
  306. PINCTRL_PIN(213, "GP62"),
  307. PINCTRL_PIN(214, "GP63"),
  308. /* Family 14: GPIO North (13 pins) */
  309. PINCTRL_PIN(215, "GP164"),
  310. PINCTRL_PIN(216, "GP165"),
  311. PINCTRL_PIN(217, "GP166"),
  312. PINCTRL_PIN(218, "GP167"),
  313. PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
  314. PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
  315. PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
  316. PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
  317. PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
  318. PINCTRL_PIN(224, "GP173"),
  319. PINCTRL_PIN(225, "GP174"),
  320. PINCTRL_PIN(226, "GP175"),
  321. PINCTRL_PIN(227, "GP176"),
  322. /* Family 15: PTI (5 pins) */
  323. PINCTRL_PIN(228, "GP72_PTI_CLK"),
  324. PINCTRL_PIN(229, "GP73_PTI_D0"),
  325. PINCTRL_PIN(230, "GP74_PTI_D1"),
  326. PINCTRL_PIN(231, "GP75_PTI_D2"),
  327. PINCTRL_PIN(232, "GP76_PTI_D3"),
  328. /* Family 16: USB3 (0 pins) */
  329. /* Family 17: HSIC (0 pins) */
  330. /* Family 18: Broadcast (0 pins) */
  331. };
  332. static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
  333. static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 };
  334. static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
  335. static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
  336. static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
  337. static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
  338. static const unsigned int mrfld_pwm0_pins[] = { 144 };
  339. static const unsigned int mrfld_pwm1_pins[] = { 145 };
  340. static const unsigned int mrfld_pwm2_pins[] = { 132 };
  341. static const unsigned int mrfld_pwm3_pins[] = { 133 };
  342. static const struct intel_pingroup mrfld_groups[] = {
  343. PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
  344. PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1),
  345. PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
  346. PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
  347. PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
  348. PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
  349. PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
  350. PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
  351. PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
  352. PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
  353. };
  354. static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
  355. static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" };
  356. static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
  357. static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
  358. static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
  359. static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
  360. static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
  361. static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
  362. static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
  363. static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
  364. static const struct intel_function mrfld_functions[] = {
  365. FUNCTION("sdio", mrfld_sdio_groups),
  366. FUNCTION("i2s2", mrfld_i2s2_groups),
  367. FUNCTION("spi5", mrfld_spi5_groups),
  368. FUNCTION("uart0", mrfld_uart0_groups),
  369. FUNCTION("uart1", mrfld_uart1_groups),
  370. FUNCTION("uart2", mrfld_uart2_groups),
  371. FUNCTION("pwm0", mrfld_pwm0_groups),
  372. FUNCTION("pwm1", mrfld_pwm1_groups),
  373. FUNCTION("pwm2", mrfld_pwm2_groups),
  374. FUNCTION("pwm3", mrfld_pwm3_groups),
  375. };
  376. static const struct mrfld_family mrfld_families[] = {
  377. MRFLD_FAMILY(1, 0, 12),
  378. MRFLD_FAMILY(2, 13, 36),
  379. MRFLD_FAMILY(3, 37, 56),
  380. MRFLD_FAMILY(4, 57, 64),
  381. MRFLD_FAMILY(5, 65, 78),
  382. MRFLD_FAMILY(6, 79, 100),
  383. MRFLD_FAMILY_PROTECTED(7, 101, 114),
  384. MRFLD_FAMILY(8, 115, 126),
  385. MRFLD_FAMILY(9, 127, 145),
  386. MRFLD_FAMILY(10, 146, 157),
  387. MRFLD_FAMILY(11, 158, 179),
  388. MRFLD_FAMILY_PROTECTED(12, 180, 194),
  389. MRFLD_FAMILY(13, 195, 214),
  390. MRFLD_FAMILY(14, 215, 227),
  391. MRFLD_FAMILY(15, 228, 232),
  392. };
  393. /**
  394. * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
  395. * @dev: Pointer to the device structure
  396. * @lock: Lock to serialize register access
  397. * @pctldesc: Pin controller description
  398. * @pctldev: Pointer to the pin controller device
  399. * @families: Array of families this pinctrl handles
  400. * @nfamilies: Number of families in the array
  401. * @functions: Array of functions
  402. * @nfunctions: Number of functions in the array
  403. * @groups: Array of pin groups
  404. * @ngroups: Number of groups in the array
  405. * @pins: Array of pins this pinctrl controls
  406. * @npins: Number of pins in the array
  407. */
  408. struct mrfld_pinctrl {
  409. struct device *dev;
  410. raw_spinlock_t lock;
  411. struct pinctrl_desc pctldesc;
  412. struct pinctrl_dev *pctldev;
  413. /* Pin controller configuration */
  414. const struct mrfld_family *families;
  415. size_t nfamilies;
  416. const struct intel_function *functions;
  417. size_t nfunctions;
  418. const struct intel_pingroup *groups;
  419. size_t ngroups;
  420. const struct pinctrl_pin_desc *pins;
  421. size_t npins;
  422. };
  423. #define pin_to_bufno(f, p) ((p) - (f)->pin_base)
  424. static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
  425. unsigned int pin)
  426. {
  427. const struct mrfld_family *family;
  428. unsigned int i;
  429. for (i = 0; i < mp->nfamilies; i++) {
  430. family = &mp->families[i];
  431. if (pin >= family->pin_base &&
  432. pin < family->pin_base + family->npins)
  433. return family;
  434. }
  435. dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
  436. return NULL;
  437. }
  438. static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
  439. {
  440. const struct mrfld_family *family;
  441. family = mrfld_get_family(mp, pin);
  442. if (!family)
  443. return false;
  444. return !family->protected;
  445. }
  446. static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
  447. {
  448. const struct mrfld_family *family;
  449. unsigned int bufno;
  450. family = mrfld_get_family(mp, pin);
  451. if (!family)
  452. return NULL;
  453. bufno = pin_to_bufno(family, pin);
  454. return family->regs + BUFCFG_OFFSET + bufno * 4;
  455. }
  456. static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
  457. {
  458. void __iomem *bufcfg;
  459. if (!mrfld_buf_available(mp, pin))
  460. return -EBUSY;
  461. bufcfg = mrfld_get_bufcfg(mp, pin);
  462. *value = readl(bufcfg);
  463. return 0;
  464. }
  465. static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
  466. u32 bits, u32 mask)
  467. {
  468. void __iomem *bufcfg;
  469. u32 value;
  470. bufcfg = mrfld_get_bufcfg(mp, pin);
  471. value = readl(bufcfg);
  472. value &= ~mask;
  473. value |= bits & mask;
  474. writel(value, bufcfg);
  475. }
  476. static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
  477. {
  478. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  479. return mp->ngroups;
  480. }
  481. static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
  482. unsigned int group)
  483. {
  484. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  485. return mp->groups[group].name;
  486. }
  487. static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
  488. const unsigned int **pins, unsigned int *npins)
  489. {
  490. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  491. *pins = mp->groups[group].pins;
  492. *npins = mp->groups[group].npins;
  493. return 0;
  494. }
  495. static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  496. unsigned int pin)
  497. {
  498. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  499. u32 value, mode;
  500. int ret;
  501. ret = mrfld_read_bufcfg(mp, pin, &value);
  502. if (ret) {
  503. seq_puts(s, "not available");
  504. return;
  505. }
  506. mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
  507. if (!mode)
  508. seq_puts(s, "GPIO ");
  509. else
  510. seq_printf(s, "mode %d ", mode);
  511. seq_printf(s, "0x%08x", value);
  512. }
  513. static const struct pinctrl_ops mrfld_pinctrl_ops = {
  514. .get_groups_count = mrfld_get_groups_count,
  515. .get_group_name = mrfld_get_group_name,
  516. .get_group_pins = mrfld_get_group_pins,
  517. .pin_dbg_show = mrfld_pin_dbg_show,
  518. };
  519. static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
  520. {
  521. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  522. return mp->nfunctions;
  523. }
  524. static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
  525. unsigned int function)
  526. {
  527. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  528. return mp->functions[function].name;
  529. }
  530. static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
  531. unsigned int function,
  532. const char * const **groups,
  533. unsigned int * const ngroups)
  534. {
  535. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  536. *groups = mp->functions[function].groups;
  537. *ngroups = mp->functions[function].ngroups;
  538. return 0;
  539. }
  540. static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
  541. unsigned int function,
  542. unsigned int group)
  543. {
  544. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  545. const struct intel_pingroup *grp = &mp->groups[group];
  546. u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
  547. u32 mask = BUFCFG_PINMODE_MASK;
  548. unsigned long flags;
  549. unsigned int i;
  550. /*
  551. * All pins in the groups needs to be accessible and writable
  552. * before we can enable the mux for this group.
  553. */
  554. for (i = 0; i < grp->npins; i++) {
  555. if (!mrfld_buf_available(mp, grp->pins[i]))
  556. return -EBUSY;
  557. }
  558. /* Now enable the mux setting for each pin in the group */
  559. raw_spin_lock_irqsave(&mp->lock, flags);
  560. for (i = 0; i < grp->npins; i++)
  561. mrfld_update_bufcfg(mp, grp->pins[i], bits, mask);
  562. raw_spin_unlock_irqrestore(&mp->lock, flags);
  563. return 0;
  564. }
  565. static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
  566. struct pinctrl_gpio_range *range,
  567. unsigned int pin)
  568. {
  569. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  570. u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
  571. u32 mask = BUFCFG_PINMODE_MASK;
  572. unsigned long flags;
  573. if (!mrfld_buf_available(mp, pin))
  574. return -EBUSY;
  575. raw_spin_lock_irqsave(&mp->lock, flags);
  576. mrfld_update_bufcfg(mp, pin, bits, mask);
  577. raw_spin_unlock_irqrestore(&mp->lock, flags);
  578. return 0;
  579. }
  580. static const struct pinmux_ops mrfld_pinmux_ops = {
  581. .get_functions_count = mrfld_get_functions_count,
  582. .get_function_name = mrfld_get_function_name,
  583. .get_function_groups = mrfld_get_function_groups,
  584. .set_mux = mrfld_pinmux_set_mux,
  585. .gpio_request_enable = mrfld_gpio_request_enable,
  586. };
  587. static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
  588. unsigned long *config)
  589. {
  590. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  591. enum pin_config_param param = pinconf_to_config_param(*config);
  592. u32 value, term;
  593. u16 arg = 0;
  594. int ret;
  595. ret = mrfld_read_bufcfg(mp, pin, &value);
  596. if (ret)
  597. return -ENOTSUPP;
  598. term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
  599. switch (param) {
  600. case PIN_CONFIG_BIAS_DISABLE:
  601. if (value & BUFCFG_Px_EN_MASK)
  602. return -EINVAL;
  603. break;
  604. case PIN_CONFIG_BIAS_PULL_UP:
  605. if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
  606. return -EINVAL;
  607. switch (term) {
  608. case BUFCFG_PUPD_VAL_910:
  609. arg = 910;
  610. break;
  611. case BUFCFG_PUPD_VAL_2K:
  612. arg = 2000;
  613. break;
  614. case BUFCFG_PUPD_VAL_20K:
  615. arg = 20000;
  616. break;
  617. case BUFCFG_PUPD_VAL_50K:
  618. arg = 50000;
  619. break;
  620. }
  621. break;
  622. case PIN_CONFIG_BIAS_PULL_DOWN:
  623. if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
  624. return -EINVAL;
  625. switch (term) {
  626. case BUFCFG_PUPD_VAL_910:
  627. arg = 910;
  628. break;
  629. case BUFCFG_PUPD_VAL_2K:
  630. arg = 2000;
  631. break;
  632. case BUFCFG_PUPD_VAL_20K:
  633. arg = 20000;
  634. break;
  635. case BUFCFG_PUPD_VAL_50K:
  636. arg = 50000;
  637. break;
  638. }
  639. break;
  640. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  641. if (!(value & BUFCFG_OD_EN))
  642. return -EINVAL;
  643. break;
  644. case PIN_CONFIG_SLEW_RATE:
  645. if (!(value & BUFCFG_SLEWSEL))
  646. arg = 0;
  647. else
  648. arg = 1;
  649. break;
  650. default:
  651. return -ENOTSUPP;
  652. }
  653. *config = pinconf_to_config_packed(param, arg);
  654. return 0;
  655. }
  656. static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
  657. unsigned long config)
  658. {
  659. unsigned int param = pinconf_to_config_param(config);
  660. unsigned int arg = pinconf_to_config_argument(config);
  661. u32 bits = 0, mask = 0;
  662. unsigned long flags;
  663. switch (param) {
  664. case PIN_CONFIG_BIAS_DISABLE:
  665. mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
  666. break;
  667. case PIN_CONFIG_BIAS_PULL_UP:
  668. mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
  669. bits |= BUFCFG_PU_EN;
  670. /* Set default strength value in case none is given */
  671. if (arg == 1)
  672. arg = 20000;
  673. switch (arg) {
  674. case 50000:
  675. bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
  676. break;
  677. case 20000:
  678. bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
  679. break;
  680. case 2000:
  681. bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
  682. break;
  683. default:
  684. return -EINVAL;
  685. }
  686. break;
  687. case PIN_CONFIG_BIAS_PULL_DOWN:
  688. mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
  689. bits |= BUFCFG_PD_EN;
  690. /* Set default strength value in case none is given */
  691. if (arg == 1)
  692. arg = 20000;
  693. switch (arg) {
  694. case 50000:
  695. bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
  696. break;
  697. case 20000:
  698. bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
  699. break;
  700. case 2000:
  701. bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
  702. break;
  703. default:
  704. return -EINVAL;
  705. }
  706. break;
  707. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  708. mask |= BUFCFG_OD_EN;
  709. if (arg)
  710. bits |= BUFCFG_OD_EN;
  711. break;
  712. case PIN_CONFIG_SLEW_RATE:
  713. mask |= BUFCFG_SLEWSEL;
  714. if (arg)
  715. bits |= BUFCFG_SLEWSEL;
  716. break;
  717. }
  718. raw_spin_lock_irqsave(&mp->lock, flags);
  719. mrfld_update_bufcfg(mp, pin, bits, mask);
  720. raw_spin_unlock_irqrestore(&mp->lock, flags);
  721. return 0;
  722. }
  723. static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
  724. unsigned long *configs, unsigned int nconfigs)
  725. {
  726. struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
  727. unsigned int i;
  728. int ret;
  729. if (!mrfld_buf_available(mp, pin))
  730. return -ENOTSUPP;
  731. for (i = 0; i < nconfigs; i++) {
  732. switch (pinconf_to_config_param(configs[i])) {
  733. case PIN_CONFIG_BIAS_DISABLE:
  734. case PIN_CONFIG_BIAS_PULL_UP:
  735. case PIN_CONFIG_BIAS_PULL_DOWN:
  736. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  737. case PIN_CONFIG_SLEW_RATE:
  738. ret = mrfld_config_set_pin(mp, pin, configs[i]);
  739. if (ret)
  740. return ret;
  741. break;
  742. default:
  743. return -ENOTSUPP;
  744. }
  745. }
  746. return 0;
  747. }
  748. static int mrfld_config_group_get(struct pinctrl_dev *pctldev,
  749. unsigned int group, unsigned long *config)
  750. {
  751. const unsigned int *pins;
  752. unsigned int npins;
  753. int ret;
  754. ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
  755. if (ret)
  756. return ret;
  757. ret = mrfld_config_get(pctldev, pins[0], config);
  758. if (ret)
  759. return ret;
  760. return 0;
  761. }
  762. static int mrfld_config_group_set(struct pinctrl_dev *pctldev,
  763. unsigned int group, unsigned long *configs,
  764. unsigned int num_configs)
  765. {
  766. const unsigned int *pins;
  767. unsigned int npins;
  768. int i, ret;
  769. ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
  770. if (ret)
  771. return ret;
  772. for (i = 0; i < npins; i++) {
  773. ret = mrfld_config_set(pctldev, pins[i], configs, num_configs);
  774. if (ret)
  775. return ret;
  776. }
  777. return 0;
  778. }
  779. static const struct pinconf_ops mrfld_pinconf_ops = {
  780. .is_generic = true,
  781. .pin_config_get = mrfld_config_get,
  782. .pin_config_set = mrfld_config_set,
  783. .pin_config_group_get = mrfld_config_group_get,
  784. .pin_config_group_set = mrfld_config_group_set,
  785. };
  786. static const struct pinctrl_desc mrfld_pinctrl_desc = {
  787. .pctlops = &mrfld_pinctrl_ops,
  788. .pmxops = &mrfld_pinmux_ops,
  789. .confops = &mrfld_pinconf_ops,
  790. .owner = THIS_MODULE,
  791. };
  792. static int mrfld_pinctrl_probe(struct platform_device *pdev)
  793. {
  794. struct mrfld_family *families;
  795. struct mrfld_pinctrl *mp;
  796. void __iomem *regs;
  797. size_t nfamilies;
  798. unsigned int i;
  799. mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
  800. if (!mp)
  801. return -ENOMEM;
  802. mp->dev = &pdev->dev;
  803. raw_spin_lock_init(&mp->lock);
  804. regs = devm_platform_ioremap_resource(pdev, 0);
  805. if (IS_ERR(regs))
  806. return PTR_ERR(regs);
  807. /*
  808. * Make a copy of the families which we can use to hold pointers
  809. * to the registers.
  810. */
  811. nfamilies = ARRAY_SIZE(mrfld_families),
  812. families = devm_kmemdup(&pdev->dev, mrfld_families,
  813. sizeof(mrfld_families),
  814. GFP_KERNEL);
  815. if (!families)
  816. return -ENOMEM;
  817. /* Splice memory resource by chunk per family */
  818. for (i = 0; i < nfamilies; i++) {
  819. struct mrfld_family *family = &families[i];
  820. family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
  821. }
  822. mp->families = families;
  823. mp->nfamilies = nfamilies;
  824. mp->functions = mrfld_functions;
  825. mp->nfunctions = ARRAY_SIZE(mrfld_functions);
  826. mp->groups = mrfld_groups;
  827. mp->ngroups = ARRAY_SIZE(mrfld_groups);
  828. mp->pctldesc = mrfld_pinctrl_desc;
  829. mp->pctldesc.name = dev_name(&pdev->dev);
  830. mp->pctldesc.pins = mrfld_pins;
  831. mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
  832. mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp);
  833. if (IS_ERR(mp->pctldev)) {
  834. dev_err(&pdev->dev, "failed to register pinctrl driver\n");
  835. return PTR_ERR(mp->pctldev);
  836. }
  837. platform_set_drvdata(pdev, mp);
  838. return 0;
  839. }
  840. static const struct acpi_device_id mrfld_acpi_table[] = {
  841. { "INTC1002" },
  842. { }
  843. };
  844. MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
  845. static struct platform_driver mrfld_pinctrl_driver = {
  846. .probe = mrfld_pinctrl_probe,
  847. .driver = {
  848. .name = "pinctrl-merrifield",
  849. .acpi_match_table = mrfld_acpi_table,
  850. },
  851. };
  852. static int __init mrfld_pinctrl_init(void)
  853. {
  854. return platform_driver_register(&mrfld_pinctrl_driver);
  855. }
  856. subsys_initcall(mrfld_pinctrl_init);
  857. static void __exit mrfld_pinctrl_exit(void)
  858. {
  859. platform_driver_unregister(&mrfld_pinctrl_driver);
  860. }
  861. module_exit(mrfld_pinctrl_exit);
  862. MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
  863. MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
  864. MODULE_LICENSE("GPL v2");
  865. MODULE_ALIAS("platform:pinctrl-merrifield");