pinctrl-icelake.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Ice Lake PCH pinctrl/GPIO driver
  4. *
  5. * Copyright (C) 2018, Intel Corporation
  6. * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  7. * Mika Westerberg <mika.westerberg@linux.intel.com>
  8. */
  9. #include <linux/acpi.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pinctrl/pinctrl.h>
  13. #include "pinctrl-intel.h"
  14. #define ICL_PAD_OWN 0x020
  15. #define ICL_PADCFGLOCK 0x080
  16. #define ICL_HOSTSW_OWN 0x0b0
  17. #define ICL_GPI_IS 0x100
  18. #define ICL_GPI_IE 0x110
  19. #define ICL_GPP(r, s, e, g) \
  20. { \
  21. .reg_num = (r), \
  22. .base = (s), \
  23. .size = ((e) - (s) + 1), \
  24. .gpio_base = (g), \
  25. }
  26. #define ICL_COMMUNITY(b, s, e, g) \
  27. { \
  28. .barno = (b), \
  29. .padown_offset = ICL_PAD_OWN, \
  30. .padcfglock_offset = ICL_PADCFGLOCK, \
  31. .hostown_offset = ICL_HOSTSW_OWN, \
  32. .is_offset = ICL_GPI_IS, \
  33. .ie_offset = ICL_GPI_IE, \
  34. .pin_base = (s), \
  35. .npins = ((e) - (s) + 1), \
  36. .gpps = (g), \
  37. .ngpps = ARRAY_SIZE(g), \
  38. }
  39. /* Ice Lake-LP */
  40. static const struct pinctrl_pin_desc icllp_pins[] = {
  41. /* GPP_G */
  42. PINCTRL_PIN(0, "SD3_CMD"),
  43. PINCTRL_PIN(1, "SD3_D0"),
  44. PINCTRL_PIN(2, "SD3_D1"),
  45. PINCTRL_PIN(3, "SD3_D2"),
  46. PINCTRL_PIN(4, "SD3_D3"),
  47. PINCTRL_PIN(5, "SD3_CDB"),
  48. PINCTRL_PIN(6, "SD3_CLK"),
  49. PINCTRL_PIN(7, "SD3_WP"),
  50. /* GPP_B */
  51. PINCTRL_PIN(8, "CORE_VID_0"),
  52. PINCTRL_PIN(9, "CORE_VID_1"),
  53. PINCTRL_PIN(10, "VRALERTB"),
  54. PINCTRL_PIN(11, "CPU_GP_2"),
  55. PINCTRL_PIN(12, "CPU_GP_3"),
  56. PINCTRL_PIN(13, "ISH_I2C0_SDA"),
  57. PINCTRL_PIN(14, "ISH_I2C0_SCL"),
  58. PINCTRL_PIN(15, "ISH_I2C1_SDA"),
  59. PINCTRL_PIN(16, "ISH_I2C1_SCL"),
  60. PINCTRL_PIN(17, "I2C5_SDA"),
  61. PINCTRL_PIN(18, "I2C5_SCL"),
  62. PINCTRL_PIN(19, "PMCALERTB"),
  63. PINCTRL_PIN(20, "SLP_S0B"),
  64. PINCTRL_PIN(21, "PLTRSTB"),
  65. PINCTRL_PIN(22, "SPKR"),
  66. PINCTRL_PIN(23, "GSPI0_CS0B"),
  67. PINCTRL_PIN(24, "GSPI0_CLK"),
  68. PINCTRL_PIN(25, "GSPI0_MISO"),
  69. PINCTRL_PIN(26, "GSPI0_MOSI"),
  70. PINCTRL_PIN(27, "GSPI1_CS0B"),
  71. PINCTRL_PIN(28, "GSPI1_CLK"),
  72. PINCTRL_PIN(29, "GSPI1_MISO"),
  73. PINCTRL_PIN(30, "GSPI1_MOSI"),
  74. PINCTRL_PIN(31, "SML1ALERTB"),
  75. PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"),
  76. PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"),
  77. /* GPP_A */
  78. PINCTRL_PIN(34, "ESPI_IO_0"),
  79. PINCTRL_PIN(35, "ESPI_IO_1"),
  80. PINCTRL_PIN(36, "ESPI_IO_2"),
  81. PINCTRL_PIN(37, "ESPI_IO_3"),
  82. PINCTRL_PIN(38, "ESPI_CSB"),
  83. PINCTRL_PIN(39, "ESPI_CLK"),
  84. PINCTRL_PIN(40, "ESPI_RESETB"),
  85. PINCTRL_PIN(41, "I2S2_SCLK"),
  86. PINCTRL_PIN(42, "I2S2_SFRM"),
  87. PINCTRL_PIN(43, "I2S2_TXD"),
  88. PINCTRL_PIN(44, "I2S2_RXD"),
  89. PINCTRL_PIN(45, "SATA_DEVSLP_2"),
  90. PINCTRL_PIN(46, "SATAXPCIE_1"),
  91. PINCTRL_PIN(47, "SATAXPCIE_2"),
  92. PINCTRL_PIN(48, "USB2_OCB_1"),
  93. PINCTRL_PIN(49, "USB2_OCB_2"),
  94. PINCTRL_PIN(50, "USB2_OCB_3"),
  95. PINCTRL_PIN(51, "DDSP_HPD_C"),
  96. PINCTRL_PIN(52, "DDSP_HPD_B"),
  97. PINCTRL_PIN(53, "DDSP_HPD_1"),
  98. PINCTRL_PIN(54, "DDSP_HPD_2"),
  99. PINCTRL_PIN(55, "I2S5_TXD"),
  100. PINCTRL_PIN(56, "I2S5_RXD"),
  101. PINCTRL_PIN(57, "I2S1_SCLK"),
  102. PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"),
  103. /* GPP_H */
  104. PINCTRL_PIN(59, "SD_1P8_SEL"),
  105. PINCTRL_PIN(60, "SD_PWR_EN_B"),
  106. PINCTRL_PIN(61, "GPPC_H_2"),
  107. PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"),
  108. PINCTRL_PIN(63, "I2C2_SDA"),
  109. PINCTRL_PIN(64, "I2C2_SCL"),
  110. PINCTRL_PIN(65, "I2C3_SDA"),
  111. PINCTRL_PIN(66, "I2C3_SCL"),
  112. PINCTRL_PIN(67, "I2C4_SDA"),
  113. PINCTRL_PIN(68, "I2C4_SCL"),
  114. PINCTRL_PIN(69, "SRCCLKREQB_4"),
  115. PINCTRL_PIN(70, "SRCCLKREQB_5"),
  116. PINCTRL_PIN(71, "M2_SKT2_CFG_0"),
  117. PINCTRL_PIN(72, "M2_SKT2_CFG_1"),
  118. PINCTRL_PIN(73, "M2_SKT2_CFG_2"),
  119. PINCTRL_PIN(74, "M2_SKT2_CFG_3"),
  120. PINCTRL_PIN(75, "DDPB_CTRLCLK"),
  121. PINCTRL_PIN(76, "DDPB_CTRLDATA"),
  122. PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"),
  123. PINCTRL_PIN(78, "TIME_SYNC_0"),
  124. PINCTRL_PIN(79, "IMGCLKOUT_1"),
  125. PINCTRL_PIN(80, "IMGCLKOUT_2"),
  126. PINCTRL_PIN(81, "IMGCLKOUT_3"),
  127. PINCTRL_PIN(82, "IMGCLKOUT_4"),
  128. /* GPP_D */
  129. PINCTRL_PIN(83, "ISH_GP_0"),
  130. PINCTRL_PIN(84, "ISH_GP_1"),
  131. PINCTRL_PIN(85, "ISH_GP_2"),
  132. PINCTRL_PIN(86, "ISH_GP_3"),
  133. PINCTRL_PIN(87, "IMGCLKOUT_0"),
  134. PINCTRL_PIN(88, "SRCCLKREQB_0"),
  135. PINCTRL_PIN(89, "SRCCLKREQB_1"),
  136. PINCTRL_PIN(90, "SRCCLKREQB_2"),
  137. PINCTRL_PIN(91, "SRCCLKREQB_3"),
  138. PINCTRL_PIN(92, "ISH_SPI_CSB"),
  139. PINCTRL_PIN(93, "ISH_SPI_CLK"),
  140. PINCTRL_PIN(94, "ISH_SPI_MISO"),
  141. PINCTRL_PIN(95, "ISH_SPI_MOSI"),
  142. PINCTRL_PIN(96, "ISH_UART0_RXD"),
  143. PINCTRL_PIN(97, "ISH_UART0_TXD"),
  144. PINCTRL_PIN(98, "ISH_UART0_RTSB"),
  145. PINCTRL_PIN(99, "ISH_UART0_CTSB"),
  146. PINCTRL_PIN(100, "ISH_GP_4"),
  147. PINCTRL_PIN(101, "ISH_GP_5"),
  148. PINCTRL_PIN(102, "I2S_MCLK"),
  149. PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"),
  150. /* GPP_F */
  151. PINCTRL_PIN(104, "CNV_BRI_DT"),
  152. PINCTRL_PIN(105, "CNV_BRI_RSP"),
  153. PINCTRL_PIN(106, "CNV_RGI_DT"),
  154. PINCTRL_PIN(107, "CNV_RGI_RSP"),
  155. PINCTRL_PIN(108, "CNV_RF_RESET_B"),
  156. PINCTRL_PIN(109, "EMMC_HIP_MON"),
  157. PINCTRL_PIN(110, "CNV_PA_BLANKING"),
  158. PINCTRL_PIN(111, "EMMC_CMD"),
  159. PINCTRL_PIN(112, "EMMC_DATA0"),
  160. PINCTRL_PIN(113, "EMMC_DATA1"),
  161. PINCTRL_PIN(114, "EMMC_DATA2"),
  162. PINCTRL_PIN(115, "EMMC_DATA3"),
  163. PINCTRL_PIN(116, "EMMC_DATA4"),
  164. PINCTRL_PIN(117, "EMMC_DATA5"),
  165. PINCTRL_PIN(118, "EMMC_DATA6"),
  166. PINCTRL_PIN(119, "EMMC_DATA7"),
  167. PINCTRL_PIN(120, "EMMC_RCLK"),
  168. PINCTRL_PIN(121, "EMMC_CLK"),
  169. PINCTRL_PIN(122, "EMMC_RESETB"),
  170. PINCTRL_PIN(123, "A4WP_PRESENT"),
  171. /* vGPIO */
  172. PINCTRL_PIN(124, "CNV_BTEN"),
  173. PINCTRL_PIN(125, "CNV_WCEN"),
  174. PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"),
  175. PINCTRL_PIN(127, "CNV_BT_IF_SELECT"),
  176. PINCTRL_PIN(128, "vCNV_BT_UART_TXD"),
  177. PINCTRL_PIN(129, "vCNV_BT_UART_RXD"),
  178. PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"),
  179. PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"),
  180. PINCTRL_PIN(132, "vCNV_MFUART1_TXD"),
  181. PINCTRL_PIN(133, "vCNV_MFUART1_RXD"),
  182. PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"),
  183. PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"),
  184. PINCTRL_PIN(136, "vUART0_TXD"),
  185. PINCTRL_PIN(137, "vUART0_RXD"),
  186. PINCTRL_PIN(138, "vUART0_CTS_B"),
  187. PINCTRL_PIN(139, "vUART0_RTS_B"),
  188. PINCTRL_PIN(140, "vISH_UART0_TXD"),
  189. PINCTRL_PIN(141, "vISH_UART0_RXD"),
  190. PINCTRL_PIN(142, "vISH_UART0_CTS_B"),
  191. PINCTRL_PIN(143, "vISH_UART0_RTS_B"),
  192. PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"),
  193. PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"),
  194. PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"),
  195. PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"),
  196. PINCTRL_PIN(148, "vI2S2_SCLK"),
  197. PINCTRL_PIN(149, "vI2S2_SFRM"),
  198. PINCTRL_PIN(150, "vI2S2_TXD"),
  199. PINCTRL_PIN(151, "vI2S2_RXD"),
  200. PINCTRL_PIN(152, "vSD3_CD_B"),
  201. /* GPP_C */
  202. PINCTRL_PIN(153, "SMBCLK"),
  203. PINCTRL_PIN(154, "SMBDATA"),
  204. PINCTRL_PIN(155, "SMBALERTB"),
  205. PINCTRL_PIN(156, "SML0CLK"),
  206. PINCTRL_PIN(157, "SML0DATA"),
  207. PINCTRL_PIN(158, "SML0ALERTB"),
  208. PINCTRL_PIN(159, "SML1CLK"),
  209. PINCTRL_PIN(160, "SML1DATA"),
  210. PINCTRL_PIN(161, "UART0_RXD"),
  211. PINCTRL_PIN(162, "UART0_TXD"),
  212. PINCTRL_PIN(163, "UART0_RTSB"),
  213. PINCTRL_PIN(164, "UART0_CTSB"),
  214. PINCTRL_PIN(165, "UART1_RXD"),
  215. PINCTRL_PIN(166, "UART1_TXD"),
  216. PINCTRL_PIN(167, "UART1_RTSB"),
  217. PINCTRL_PIN(168, "UART1_CTSB"),
  218. PINCTRL_PIN(169, "I2C0_SDA"),
  219. PINCTRL_PIN(170, "I2C0_SCL"),
  220. PINCTRL_PIN(171, "I2C1_SDA"),
  221. PINCTRL_PIN(172, "I2C1_SCL"),
  222. PINCTRL_PIN(173, "UART2_RXD"),
  223. PINCTRL_PIN(174, "UART2_TXD"),
  224. PINCTRL_PIN(175, "UART2_RTSB"),
  225. PINCTRL_PIN(176, "UART2_CTSB"),
  226. /* HVCMOS */
  227. PINCTRL_PIN(177, "L_BKLTEN"),
  228. PINCTRL_PIN(178, "L_BKLTCTL"),
  229. PINCTRL_PIN(179, "L_VDDEN"),
  230. PINCTRL_PIN(180, "SYS_PWROK"),
  231. PINCTRL_PIN(181, "SYS_RESETB"),
  232. PINCTRL_PIN(182, "MLK_RSTB"),
  233. /* GPP_E */
  234. PINCTRL_PIN(183, "SATAXPCIE_0"),
  235. PINCTRL_PIN(184, "SPI1_IO_2"),
  236. PINCTRL_PIN(185, "SPI1_IO_3"),
  237. PINCTRL_PIN(186, "CPU_GP_0"),
  238. PINCTRL_PIN(187, "SATA_DEVSLP_0"),
  239. PINCTRL_PIN(188, "SATA_DEVSLP_1"),
  240. PINCTRL_PIN(189, "GPPC_E_6"),
  241. PINCTRL_PIN(190, "CPU_GP_1"),
  242. PINCTRL_PIN(191, "SATA_LEDB"),
  243. PINCTRL_PIN(192, "USB2_OCB_0"),
  244. PINCTRL_PIN(193, "SPI1_CSB"),
  245. PINCTRL_PIN(194, "SPI1_CLK"),
  246. PINCTRL_PIN(195, "SPI1_MISO_IO_1"),
  247. PINCTRL_PIN(196, "SPI1_MOSI_IO_0"),
  248. PINCTRL_PIN(197, "DDSP_HPD_A"),
  249. PINCTRL_PIN(198, "ISH_GP_6"),
  250. PINCTRL_PIN(199, "ISH_GP_7"),
  251. PINCTRL_PIN(200, "DISP_MISC_4"),
  252. PINCTRL_PIN(201, "DDP1_CTRLCLK"),
  253. PINCTRL_PIN(202, "DDP1_CTRLDATA"),
  254. PINCTRL_PIN(203, "DDP2_CTRLCLK"),
  255. PINCTRL_PIN(204, "DDP2_CTRLDATA"),
  256. PINCTRL_PIN(205, "DDPA_CTRLCLK"),
  257. PINCTRL_PIN(206, "DDPA_CTRLDATA"),
  258. /* JTAG */
  259. PINCTRL_PIN(207, "JTAG_TDO"),
  260. PINCTRL_PIN(208, "JTAGX"),
  261. PINCTRL_PIN(209, "PRDYB"),
  262. PINCTRL_PIN(210, "PREQB"),
  263. PINCTRL_PIN(211, "CPU_TRSTB"),
  264. PINCTRL_PIN(212, "JTAG_TDI"),
  265. PINCTRL_PIN(213, "JTAG_TMS"),
  266. PINCTRL_PIN(214, "JTAG_TCK"),
  267. PINCTRL_PIN(215, "ITP_PMODE"),
  268. /* GPP_R */
  269. PINCTRL_PIN(216, "HDA_BCLK"),
  270. PINCTRL_PIN(217, "HDA_SYNC"),
  271. PINCTRL_PIN(218, "HDA_SDO"),
  272. PINCTRL_PIN(219, "HDA_SDI_0"),
  273. PINCTRL_PIN(220, "HDA_RSTB"),
  274. PINCTRL_PIN(221, "HDA_SDI_1"),
  275. PINCTRL_PIN(222, "I2S1_TXD"),
  276. PINCTRL_PIN(223, "I2S1_RXD"),
  277. /* GPP_S */
  278. PINCTRL_PIN(224, "SNDW1_CLK"),
  279. PINCTRL_PIN(225, "SNDW1_DATA"),
  280. PINCTRL_PIN(226, "SNDW2_CLK"),
  281. PINCTRL_PIN(227, "SNDW2_DATA"),
  282. PINCTRL_PIN(228, "SNDW3_CLK"),
  283. PINCTRL_PIN(229, "SNDW3_DATA"),
  284. PINCTRL_PIN(230, "SNDW4_CLK"),
  285. PINCTRL_PIN(231, "SNDW4_DATA"),
  286. /* SPI */
  287. PINCTRL_PIN(232, "SPI0_IO_2"),
  288. PINCTRL_PIN(233, "SPI0_IO_3"),
  289. PINCTRL_PIN(234, "SPI0_MOSI_IO_0"),
  290. PINCTRL_PIN(235, "SPI0_MISO_IO_1"),
  291. PINCTRL_PIN(236, "SPI0_TPM_CSB"),
  292. PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"),
  293. PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"),
  294. PINCTRL_PIN(239, "SPI0_CLK"),
  295. PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"),
  296. };
  297. static const struct intel_padgroup icllp_community0_gpps[] = {
  298. ICL_GPP(0, 0, 7, 0), /* GPP_G */
  299. ICL_GPP(1, 8, 33, 32), /* GPP_B */
  300. ICL_GPP(2, 34, 58, 64), /* GPP_A */
  301. };
  302. static const struct intel_padgroup icllp_community1_gpps[] = {
  303. ICL_GPP(0, 59, 82, 96), /* GPP_H */
  304. ICL_GPP(1, 83, 103, 128), /* GPP_D */
  305. ICL_GPP(2, 104, 123, 160), /* GPP_F */
  306. ICL_GPP(3, 124, 152, 192), /* vGPIO */
  307. };
  308. static const struct intel_padgroup icllp_community4_gpps[] = {
  309. ICL_GPP(0, 153, 176, 224), /* GPP_C */
  310. ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
  311. ICL_GPP(2, 183, 206, 256), /* GPP_E */
  312. ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
  313. };
  314. static const struct intel_padgroup icllp_community5_gpps[] = {
  315. ICL_GPP(0, 216, 223, 288), /* GPP_R */
  316. ICL_GPP(1, 224, 231, 320), /* GPP_S */
  317. ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
  318. };
  319. static const struct intel_community icllp_communities[] = {
  320. ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),
  321. ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),
  322. ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),
  323. ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),
  324. };
  325. static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
  326. static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };
  327. static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };
  328. static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };
  329. static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };
  330. static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
  331. static const unsigned int icllp_i2c0_pins[] = { 169, 170 };
  332. static const unsigned int icllp_i2c1_pins[] = { 171, 172 };
  333. static const unsigned int icllp_i2c2_pins[] = { 63, 64 };
  334. static const unsigned int icllp_i2c3_pins[] = { 65, 66 };
  335. static const unsigned int icllp_i2c4_pins[] = { 67, 68 };
  336. static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };
  337. static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };
  338. static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };
  339. static const struct intel_pingroup icllp_groups[] = {
  340. PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes),
  341. PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes),
  342. PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes),
  343. PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1),
  344. PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1),
  345. PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1),
  346. PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1),
  347. PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1),
  348. PIN_GROUP("uart0_grp", icllp_uart0_pins, 1),
  349. PIN_GROUP("uart1_grp", icllp_uart1_pins, 1),
  350. PIN_GROUP("uart2_grp", icllp_uart2_pins, 1),
  351. };
  352. static const char * const icllp_spi0_groups[] = { "spi0_grp" };
  353. static const char * const icllp_spi1_groups[] = { "spi1_grp" };
  354. static const char * const icllp_spi2_groups[] = { "spi2_grp" };
  355. static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };
  356. static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };
  357. static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };
  358. static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };
  359. static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };
  360. static const char * const icllp_uart0_groups[] = { "uart0_grp" };
  361. static const char * const icllp_uart1_groups[] = { "uart1_grp" };
  362. static const char * const icllp_uart2_groups[] = { "uart2_grp" };
  363. static const struct intel_function icllp_functions[] = {
  364. FUNCTION("spi0", icllp_spi0_groups),
  365. FUNCTION("spi1", icllp_spi1_groups),
  366. FUNCTION("spi2", icllp_spi2_groups),
  367. FUNCTION("i2c0", icllp_i2c0_groups),
  368. FUNCTION("i2c1", icllp_i2c1_groups),
  369. FUNCTION("i2c2", icllp_i2c2_groups),
  370. FUNCTION("i2c3", icllp_i2c3_groups),
  371. FUNCTION("i2c4", icllp_i2c4_groups),
  372. FUNCTION("uart0", icllp_uart0_groups),
  373. FUNCTION("uart1", icllp_uart1_groups),
  374. FUNCTION("uart2", icllp_uart2_groups),
  375. };
  376. static const struct intel_pinctrl_soc_data icllp_soc_data = {
  377. .pins = icllp_pins,
  378. .npins = ARRAY_SIZE(icllp_pins),
  379. .groups = icllp_groups,
  380. .ngroups = ARRAY_SIZE(icllp_groups),
  381. .functions = icllp_functions,
  382. .nfunctions = ARRAY_SIZE(icllp_functions),
  383. .communities = icllp_communities,
  384. .ncommunities = ARRAY_SIZE(icllp_communities),
  385. };
  386. static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
  387. static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
  388. { "INT3455", (kernel_ulong_t)&icllp_soc_data },
  389. { }
  390. };
  391. MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
  392. static struct platform_driver icl_pinctrl_driver = {
  393. .probe = intel_pinctrl_probe_by_hid,
  394. .driver = {
  395. .name = "icelake-pinctrl",
  396. .acpi_match_table = icl_pinctrl_acpi_match,
  397. .pm = &icl_pinctrl_pm_ops,
  398. },
  399. };
  400. module_platform_driver(icl_pinctrl_driver);
  401. MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
  402. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  403. MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver");
  404. MODULE_LICENSE("GPL v2");