pinctrl-geminilake.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Gemini Lake SoC pinctrl/GPIO driver
  4. *
  5. * Copyright (C) 2017 Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. */
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include "pinctrl-intel.h"
  13. #define GLK_PAD_OWN 0x020
  14. #define GLK_PADCFGLOCK 0x080
  15. #define GLK_HOSTSW_OWN 0x0b0
  16. #define GLK_GPI_IS 0x100
  17. #define GLK_GPI_IE 0x110
  18. #define GLK_COMMUNITY(s, e) \
  19. { \
  20. .padown_offset = GLK_PAD_OWN, \
  21. .padcfglock_offset = GLK_PADCFGLOCK, \
  22. .hostown_offset = GLK_HOSTSW_OWN, \
  23. .is_offset = GLK_GPI_IS, \
  24. .ie_offset = GLK_GPI_IE, \
  25. .gpp_size = 32, \
  26. .pin_base = (s), \
  27. .npins = ((e) - (s) + 1), \
  28. }
  29. /* GLK */
  30. static const struct pinctrl_pin_desc glk_northwest_pins[] = {
  31. PINCTRL_PIN(0, "TCK"),
  32. PINCTRL_PIN(1, "TRST_B"),
  33. PINCTRL_PIN(2, "TMS"),
  34. PINCTRL_PIN(3, "TDI"),
  35. PINCTRL_PIN(4, "TDO"),
  36. PINCTRL_PIN(5, "JTAGX"),
  37. PINCTRL_PIN(6, "CX_PREQ_B"),
  38. PINCTRL_PIN(7, "CX_PRDY_B"),
  39. PINCTRL_PIN(8, "GPIO_8"),
  40. PINCTRL_PIN(9, "GPIO_9"),
  41. PINCTRL_PIN(10, "GPIO_10"),
  42. PINCTRL_PIN(11, "GPIO_11"),
  43. PINCTRL_PIN(12, "GPIO_12"),
  44. PINCTRL_PIN(13, "GPIO_13"),
  45. PINCTRL_PIN(14, "GPIO_14"),
  46. PINCTRL_PIN(15, "GPIO_15"),
  47. PINCTRL_PIN(16, "GPIO_16"),
  48. PINCTRL_PIN(17, "GPIO_17"),
  49. PINCTRL_PIN(18, "GPIO_18"),
  50. PINCTRL_PIN(19, "GPIO_19"),
  51. PINCTRL_PIN(20, "GPIO_20"),
  52. PINCTRL_PIN(21, "GPIO_21"),
  53. PINCTRL_PIN(22, "GPIO_22"),
  54. PINCTRL_PIN(23, "GPIO_23"),
  55. PINCTRL_PIN(24, "GPIO_24"),
  56. PINCTRL_PIN(25, "GPIO_25"),
  57. PINCTRL_PIN(26, "ISH_GPIO_0"),
  58. PINCTRL_PIN(27, "ISH_GPIO_1"),
  59. PINCTRL_PIN(28, "ISH_GPIO_2"),
  60. PINCTRL_PIN(29, "ISH_GPIO_3"),
  61. PINCTRL_PIN(30, "ISH_GPIO_4"),
  62. PINCTRL_PIN(31, "ISH_GPIO_5"),
  63. PINCTRL_PIN(32, "ISH_GPIO_6"),
  64. PINCTRL_PIN(33, "ISH_GPIO_7"),
  65. PINCTRL_PIN(34, "ISH_GPIO_8"),
  66. PINCTRL_PIN(35, "ISH_GPIO_9"),
  67. PINCTRL_PIN(36, "GPIO_36"),
  68. PINCTRL_PIN(37, "GPIO_37"),
  69. PINCTRL_PIN(38, "GPIO_38"),
  70. PINCTRL_PIN(39, "GPIO_39"),
  71. PINCTRL_PIN(40, "GPIO_40"),
  72. PINCTRL_PIN(41, "GPIO_41"),
  73. PINCTRL_PIN(42, "GP_INTD_DSI_TE1"),
  74. PINCTRL_PIN(43, "GP_INTD_DSI_TE2"),
  75. PINCTRL_PIN(44, "USB_OC0_B"),
  76. PINCTRL_PIN(45, "USB_OC1_B"),
  77. PINCTRL_PIN(46, "DSI_I2C_SDA"),
  78. PINCTRL_PIN(47, "DSI_I2C_SCL"),
  79. PINCTRL_PIN(48, "PMC_I2C_SDA"),
  80. PINCTRL_PIN(49, "PMC_I2C_SCL"),
  81. PINCTRL_PIN(50, "LPSS_I2C0_SDA"),
  82. PINCTRL_PIN(51, "LPSS_I2C0_SCL"),
  83. PINCTRL_PIN(52, "LPSS_I2C1_SDA"),
  84. PINCTRL_PIN(53, "LPSS_I2C1_SCL"),
  85. PINCTRL_PIN(54, "LPSS_I2C2_SDA"),
  86. PINCTRL_PIN(55, "LPSS_I2C2_SCL"),
  87. PINCTRL_PIN(56, "LPSS_I2C3_SDA"),
  88. PINCTRL_PIN(57, "LPSS_I2C3_SCL"),
  89. PINCTRL_PIN(58, "LPSS_I2C4_SDA"),
  90. PINCTRL_PIN(59, "LPSS_I2C4_SCL"),
  91. PINCTRL_PIN(60, "LPSS_UART0_RXD"),
  92. PINCTRL_PIN(61, "LPSS_UART0_TXD"),
  93. PINCTRL_PIN(62, "LPSS_UART0_RTS_B"),
  94. PINCTRL_PIN(63, "LPSS_UART0_CTS_B"),
  95. PINCTRL_PIN(64, "LPSS_UART2_RXD"),
  96. PINCTRL_PIN(65, "LPSS_UART2_TXD"),
  97. PINCTRL_PIN(66, "LPSS_UART2_RTS_B"),
  98. PINCTRL_PIN(67, "LPSS_UART2_CTS_B"),
  99. PINCTRL_PIN(68, "PMC_SPI_FS0"),
  100. PINCTRL_PIN(69, "PMC_SPI_FS1"),
  101. PINCTRL_PIN(70, "PMC_SPI_FS2"),
  102. PINCTRL_PIN(71, "PMC_SPI_RXD"),
  103. PINCTRL_PIN(72, "PMC_SPI_TXD"),
  104. PINCTRL_PIN(73, "PMC_SPI_CLK"),
  105. PINCTRL_PIN(74, "THERMTRIP_B"),
  106. PINCTRL_PIN(75, "PROCHOT_B"),
  107. PINCTRL_PIN(76, "EMMC_RST_B"),
  108. PINCTRL_PIN(77, "GPIO_212"),
  109. PINCTRL_PIN(78, "GPIO_213"),
  110. PINCTRL_PIN(79, "GPIO_214"),
  111. };
  112. static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 };
  113. static const unsigned int glk_northwest_pwm0_pins[] = { 42 };
  114. static const unsigned int glk_northwest_pwm1_pins[] = { 43 };
  115. static const unsigned int glk_northwest_pwm2_pins[] = { 44 };
  116. static const unsigned int glk_northwest_pwm3_pins[] = { 45 };
  117. static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 };
  118. static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 };
  119. static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 };
  120. static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 };
  121. static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 };
  122. static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 };
  123. static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 };
  124. static const struct intel_pingroup glk_northwest_groups[] = {
  125. PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2),
  126. PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2),
  127. PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2),
  128. PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2),
  129. PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2),
  130. PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1),
  131. PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1),
  132. PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1),
  133. PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1),
  134. PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1),
  135. PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1),
  136. PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1),
  137. };
  138. static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" };
  139. static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" };
  140. static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" };
  141. static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" };
  142. static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" };
  143. static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" };
  144. static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" };
  145. static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" };
  146. static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" };
  147. static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" };
  148. static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" };
  149. static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" };
  150. static const struct intel_function glk_northwest_functions[] = {
  151. FUNCTION("uart1", glk_northwest_uart1_groups),
  152. FUNCTION("pmw0", glk_northwest_pwm0_groups),
  153. FUNCTION("pmw1", glk_northwest_pwm1_groups),
  154. FUNCTION("pmw2", glk_northwest_pwm2_groups),
  155. FUNCTION("pmw3", glk_northwest_pwm3_groups),
  156. FUNCTION("i2c0", glk_northwest_i2c0_groups),
  157. FUNCTION("i2c1", glk_northwest_i2c1_groups),
  158. FUNCTION("i2c2", glk_northwest_i2c2_groups),
  159. FUNCTION("i2c3", glk_northwest_i2c3_groups),
  160. FUNCTION("i2c4", glk_northwest_i2c4_groups),
  161. FUNCTION("uart0", glk_northwest_uart0_groups),
  162. FUNCTION("uart2", glk_northwest_uart2_groups),
  163. };
  164. static const struct intel_community glk_northwest_communities[] = {
  165. GLK_COMMUNITY(0, 79),
  166. };
  167. static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {
  168. .uid = "1",
  169. .pins = glk_northwest_pins,
  170. .npins = ARRAY_SIZE(glk_northwest_pins),
  171. .groups = glk_northwest_groups,
  172. .ngroups = ARRAY_SIZE(glk_northwest_groups),
  173. .functions = glk_northwest_functions,
  174. .nfunctions = ARRAY_SIZE(glk_northwest_functions),
  175. .communities = glk_northwest_communities,
  176. .ncommunities = ARRAY_SIZE(glk_northwest_communities),
  177. };
  178. static const struct pinctrl_pin_desc glk_north_pins[] = {
  179. PINCTRL_PIN(0, "SVID0_ALERT_B"),
  180. PINCTRL_PIN(1, "SVID0_DATA"),
  181. PINCTRL_PIN(2, "SVID0_CLK"),
  182. PINCTRL_PIN(3, "LPSS_SPI_0_CLK"),
  183. PINCTRL_PIN(4, "LPSS_SPI_0_FS0"),
  184. PINCTRL_PIN(5, "LPSS_SPI_0_FS1"),
  185. PINCTRL_PIN(6, "LPSS_SPI_0_RXD"),
  186. PINCTRL_PIN(7, "LPSS_SPI_0_TXD"),
  187. PINCTRL_PIN(8, "LPSS_SPI_2_CLK"),
  188. PINCTRL_PIN(9, "LPSS_SPI_2_FS0"),
  189. PINCTRL_PIN(10, "LPSS_SPI_2_FS1"),
  190. PINCTRL_PIN(11, "LPSS_SPI_2_FS2"),
  191. PINCTRL_PIN(12, "LPSS_SPI_2_RXD"),
  192. PINCTRL_PIN(13, "LPSS_SPI_2_TXD"),
  193. PINCTRL_PIN(14, "FST_SPI_CS0_B"),
  194. PINCTRL_PIN(15, "FST_SPI_CS1_B"),
  195. PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"),
  196. PINCTRL_PIN(17, "FST_SPI_MISO_IO1"),
  197. PINCTRL_PIN(18, "FST_SPI_IO2"),
  198. PINCTRL_PIN(19, "FST_SPI_IO3"),
  199. PINCTRL_PIN(20, "FST_SPI_CLK"),
  200. PINCTRL_PIN(21, "FST_SPI_CLK_FB"),
  201. PINCTRL_PIN(22, "PMU_PLTRST_B"),
  202. PINCTRL_PIN(23, "PMU_PWRBTN_B"),
  203. PINCTRL_PIN(24, "PMU_SLP_S0_B"),
  204. PINCTRL_PIN(25, "PMU_SLP_S3_B"),
  205. PINCTRL_PIN(26, "PMU_SLP_S4_B"),
  206. PINCTRL_PIN(27, "SUSPWRDNACK"),
  207. PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"),
  208. PINCTRL_PIN(29, "GPIO_105"),
  209. PINCTRL_PIN(30, "PMU_BATLOW_B"),
  210. PINCTRL_PIN(31, "PMU_RESETBUTTON_B"),
  211. PINCTRL_PIN(32, "PMU_SUSCLK"),
  212. PINCTRL_PIN(33, "SUS_STAT_B"),
  213. PINCTRL_PIN(34, "LPSS_I2C5_SDA"),
  214. PINCTRL_PIN(35, "LPSS_I2C5_SCL"),
  215. PINCTRL_PIN(36, "LPSS_I2C6_SDA"),
  216. PINCTRL_PIN(37, "LPSS_I2C6_SCL"),
  217. PINCTRL_PIN(38, "LPSS_I2C7_SDA"),
  218. PINCTRL_PIN(39, "LPSS_I2C7_SCL"),
  219. PINCTRL_PIN(40, "PCIE_WAKE0_B"),
  220. PINCTRL_PIN(41, "PCIE_WAKE1_B"),
  221. PINCTRL_PIN(42, "PCIE_WAKE2_B"),
  222. PINCTRL_PIN(43, "PCIE_WAKE3_B"),
  223. PINCTRL_PIN(44, "PCIE_CLKREQ0_B"),
  224. PINCTRL_PIN(45, "PCIE_CLKREQ1_B"),
  225. PINCTRL_PIN(46, "PCIE_CLKREQ2_B"),
  226. PINCTRL_PIN(47, "PCIE_CLKREQ3_B"),
  227. PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"),
  228. PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"),
  229. PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"),
  230. PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"),
  231. PINCTRL_PIN(52, "PANEL0_VDDEN"),
  232. PINCTRL_PIN(53, "PANEL0_BKLTEN"),
  233. PINCTRL_PIN(54, "PANEL0_BKLTCTL"),
  234. PINCTRL_PIN(55, "HV_DDI0_HPD"),
  235. PINCTRL_PIN(56, "HV_DDI1_HPD"),
  236. PINCTRL_PIN(57, "HV_EDP_HPD"),
  237. PINCTRL_PIN(58, "GPIO_134"),
  238. PINCTRL_PIN(59, "GPIO_135"),
  239. PINCTRL_PIN(60, "GPIO_136"),
  240. PINCTRL_PIN(61, "GPIO_137"),
  241. PINCTRL_PIN(62, "GPIO_138"),
  242. PINCTRL_PIN(63, "GPIO_139"),
  243. PINCTRL_PIN(64, "GPIO_140"),
  244. PINCTRL_PIN(65, "GPIO_141"),
  245. PINCTRL_PIN(66, "GPIO_142"),
  246. PINCTRL_PIN(67, "GPIO_143"),
  247. PINCTRL_PIN(68, "GPIO_144"),
  248. PINCTRL_PIN(69, "GPIO_145"),
  249. PINCTRL_PIN(70, "GPIO_146"),
  250. PINCTRL_PIN(71, "LPC_ILB_SERIRQ"),
  251. PINCTRL_PIN(72, "LPC_CLKOUT0"),
  252. PINCTRL_PIN(73, "LPC_CLKOUT1"),
  253. PINCTRL_PIN(74, "LPC_AD0"),
  254. PINCTRL_PIN(75, "LPC_AD1"),
  255. PINCTRL_PIN(76, "LPC_AD2"),
  256. PINCTRL_PIN(77, "LPC_AD3"),
  257. PINCTRL_PIN(78, "LPC_CLKRUNB"),
  258. PINCTRL_PIN(79, "LPC_FRAMEB"),
  259. };
  260. static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 };
  261. static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 };
  262. static const unsigned int glk_north_i2c5_pins[] = { 34, 35 };
  263. static const unsigned int glk_north_i2c6_pins[] = { 36, 37 };
  264. static const unsigned int glk_north_i2c7_pins[] = { 38, 39 };
  265. static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 };
  266. static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 };
  267. static const struct intel_pingroup glk_north_groups[] = {
  268. PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1),
  269. PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1),
  270. PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1),
  271. PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1),
  272. PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1),
  273. PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2),
  274. PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2),
  275. };
  276. static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" };
  277. static const char * const glk_north_spi1_groups[] = { "spi1_grp" };
  278. static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" };
  279. static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" };
  280. static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" };
  281. static const char * const glk_north_uart0_groups[] = { "uart0_grp" };
  282. static const struct intel_function glk_north_functions[] = {
  283. FUNCTION("spi0", glk_north_spi0_groups),
  284. FUNCTION("spi1", glk_north_spi1_groups),
  285. FUNCTION("i2c5", glk_north_i2c5_groups),
  286. FUNCTION("i2c6", glk_north_i2c6_groups),
  287. FUNCTION("i2c7", glk_north_i2c7_groups),
  288. FUNCTION("uart0", glk_north_uart0_groups),
  289. };
  290. static const struct intel_community glk_north_communities[] = {
  291. GLK_COMMUNITY(0, 79),
  292. };
  293. static const struct intel_pinctrl_soc_data glk_north_soc_data = {
  294. .uid = "2",
  295. .pins = glk_north_pins,
  296. .npins = ARRAY_SIZE(glk_north_pins),
  297. .groups = glk_north_groups,
  298. .ngroups = ARRAY_SIZE(glk_north_groups),
  299. .functions = glk_north_functions,
  300. .nfunctions = ARRAY_SIZE(glk_north_functions),
  301. .communities = glk_north_communities,
  302. .ncommunities = ARRAY_SIZE(glk_north_communities),
  303. };
  304. static const struct pinctrl_pin_desc glk_audio_pins[] = {
  305. PINCTRL_PIN(0, "AVS_I2S0_MCLK"),
  306. PINCTRL_PIN(1, "AVS_I2S0_BCLK"),
  307. PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"),
  308. PINCTRL_PIN(3, "AVS_I2S0_SDI"),
  309. PINCTRL_PIN(4, "AVS_I2S0_SDO"),
  310. PINCTRL_PIN(5, "AVS_I2S1_MCLK"),
  311. PINCTRL_PIN(6, "AVS_I2S1_BCLK"),
  312. PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"),
  313. PINCTRL_PIN(8, "AVS_I2S1_SDI"),
  314. PINCTRL_PIN(9, "AVS_I2S1_SDO"),
  315. PINCTRL_PIN(10, "AVS_HDA_BCLK"),
  316. PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"),
  317. PINCTRL_PIN(12, "AVS_HDA_SDI"),
  318. PINCTRL_PIN(13, "AVS_HDA_SDO"),
  319. PINCTRL_PIN(14, "AVS_HDA_RSTB"),
  320. PINCTRL_PIN(15, "AVS_M_CLK_A1"),
  321. PINCTRL_PIN(16, "AVS_M_CLK_B1"),
  322. PINCTRL_PIN(17, "AVS_M_DATA_1"),
  323. PINCTRL_PIN(18, "AVS_M_CLK_AB2"),
  324. PINCTRL_PIN(19, "AVS_M_DATA_2"),
  325. };
  326. static const struct intel_community glk_audio_communities[] = {
  327. GLK_COMMUNITY(0, 19),
  328. };
  329. static const struct intel_pinctrl_soc_data glk_audio_soc_data = {
  330. .uid = "3",
  331. .pins = glk_audio_pins,
  332. .npins = ARRAY_SIZE(glk_audio_pins),
  333. .communities = glk_audio_communities,
  334. .ncommunities = ARRAY_SIZE(glk_audio_communities),
  335. };
  336. static const struct pinctrl_pin_desc glk_scc_pins[] = {
  337. PINCTRL_PIN(0, "SMB_ALERTB"),
  338. PINCTRL_PIN(1, "SMB_CLK"),
  339. PINCTRL_PIN(2, "SMB_DATA"),
  340. PINCTRL_PIN(3, "SDCARD_LVL_WP"),
  341. PINCTRL_PIN(4, "SDCARD_CLK"),
  342. PINCTRL_PIN(5, "SDCARD_CLK_FB"),
  343. PINCTRL_PIN(6, "SDCARD_D0"),
  344. PINCTRL_PIN(7, "SDCARD_D1"),
  345. PINCTRL_PIN(8, "SDCARD_D2"),
  346. PINCTRL_PIN(9, "SDCARD_D3"),
  347. PINCTRL_PIN(10, "SDCARD_CMD"),
  348. PINCTRL_PIN(11, "SDCARD_CD_B"),
  349. PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"),
  350. PINCTRL_PIN(13, "GPIO_210"),
  351. PINCTRL_PIN(14, "OSC_CLK_OUT_0"),
  352. PINCTRL_PIN(15, "OSC_CLK_OUT_1"),
  353. PINCTRL_PIN(16, "CNV_BRI_DT"),
  354. PINCTRL_PIN(17, "CNV_BRI_RSP"),
  355. PINCTRL_PIN(18, "CNV_RGI_DT"),
  356. PINCTRL_PIN(19, "CNV_RGI_RSP"),
  357. PINCTRL_PIN(20, "CNV_RF_RESET_B"),
  358. PINCTRL_PIN(21, "XTAL_CLKREQ"),
  359. PINCTRL_PIN(22, "SDIO_CLK_FB"),
  360. PINCTRL_PIN(23, "EMMC0_CLK"),
  361. PINCTRL_PIN(24, "EMMC0_CLK_FB"),
  362. PINCTRL_PIN(25, "EMMC0_D0"),
  363. PINCTRL_PIN(26, "EMMC0_D1"),
  364. PINCTRL_PIN(27, "EMMC0_D2"),
  365. PINCTRL_PIN(28, "EMMC0_D3"),
  366. PINCTRL_PIN(29, "EMMC0_D4"),
  367. PINCTRL_PIN(30, "EMMC0_D5"),
  368. PINCTRL_PIN(31, "EMMC0_D6"),
  369. PINCTRL_PIN(32, "EMMC0_D7"),
  370. PINCTRL_PIN(33, "EMMC0_CMD"),
  371. PINCTRL_PIN(34, "EMMC0_STROBE"),
  372. };
  373. static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 };
  374. static const unsigned int glk_scc_sdcard_pins[] = {
  375. 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
  376. };
  377. static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 };
  378. static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 };
  379. static const unsigned int glk_scc_emmc_pins[] = {
  380. 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
  381. };
  382. static const struct intel_pingroup glk_scc_groups[] = {
  383. PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2),
  384. PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1),
  385. PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2),
  386. PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3),
  387. PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1),
  388. };
  389. static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" };
  390. static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" };
  391. static const char * const glk_scc_sdio_groups[] = { "sdio_grp" };
  392. static const char * const glk_scc_uart1_groups[] = { "uart1_grp" };
  393. static const char * const glk_scc_emmc_groups[] = { "emmc_grp" };
  394. static const struct intel_function glk_scc_functions[] = {
  395. FUNCTION("i2c7", glk_scc_i2c7_groups),
  396. FUNCTION("sdcard", glk_scc_sdcard_groups),
  397. FUNCTION("sdio", glk_scc_sdio_groups),
  398. FUNCTION("uart1", glk_scc_uart1_groups),
  399. FUNCTION("emmc", glk_scc_emmc_groups),
  400. };
  401. static const struct intel_community glk_scc_communities[] = {
  402. GLK_COMMUNITY(0, 34),
  403. };
  404. static const struct intel_pinctrl_soc_data glk_scc_soc_data = {
  405. .uid = "4",
  406. .pins = glk_scc_pins,
  407. .npins = ARRAY_SIZE(glk_scc_pins),
  408. .groups = glk_scc_groups,
  409. .ngroups = ARRAY_SIZE(glk_scc_groups),
  410. .functions = glk_scc_functions,
  411. .nfunctions = ARRAY_SIZE(glk_scc_functions),
  412. .communities = glk_scc_communities,
  413. .ncommunities = ARRAY_SIZE(glk_scc_communities),
  414. };
  415. static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
  416. &glk_northwest_soc_data,
  417. &glk_north_soc_data,
  418. &glk_audio_soc_data,
  419. &glk_scc_soc_data,
  420. NULL
  421. };
  422. static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
  423. { "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data },
  424. { }
  425. };
  426. MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
  427. static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
  428. static struct platform_driver glk_pinctrl_driver = {
  429. .probe = intel_pinctrl_probe_by_uid,
  430. .driver = {
  431. .name = "geminilake-pinctrl",
  432. .acpi_match_table = glk_pinctrl_acpi_match,
  433. .pm = &glk_pinctrl_pm_ops,
  434. },
  435. };
  436. static int __init glk_pinctrl_init(void)
  437. {
  438. return platform_driver_register(&glk_pinctrl_driver);
  439. }
  440. subsys_initcall(glk_pinctrl_init);
  441. static void __exit glk_pinctrl_exit(void)
  442. {
  443. platform_driver_unregister(&glk_pinctrl_driver);
  444. }
  445. module_exit(glk_pinctrl_exit);
  446. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  447. MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver");
  448. MODULE_LICENSE("GPL v2");