pinctrl-denverton.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Denverton SoC pinctrl/GPIO driver
  4. *
  5. * Copyright (C) 2017, Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. */
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include "pinctrl-intel.h"
  13. #define DNV_PAD_OWN 0x020
  14. #define DNV_PADCFGLOCK 0x090
  15. #define DNV_HOSTSW_OWN 0x0C0
  16. #define DNV_GPI_IS 0x100
  17. #define DNV_GPI_IE 0x120
  18. #define DNV_GPP(n, s, e) \
  19. { \
  20. .reg_num = (n), \
  21. .base = (s), \
  22. .size = ((e) - (s) + 1), \
  23. }
  24. #define DNV_COMMUNITY(b, s, e, g) \
  25. { \
  26. .barno = (b), \
  27. .padown_offset = DNV_PAD_OWN, \
  28. .padcfglock_offset = DNV_PADCFGLOCK, \
  29. .hostown_offset = DNV_HOSTSW_OWN, \
  30. .is_offset = DNV_GPI_IS, \
  31. .ie_offset = DNV_GPI_IE, \
  32. .pin_base = (s), \
  33. .npins = ((e) - (s) + 1), \
  34. .gpps = (g), \
  35. .ngpps = ARRAY_SIZE(g), \
  36. }
  37. /* Denverton */
  38. static const struct pinctrl_pin_desc dnv_pins[] = {
  39. /* North ALL */
  40. PINCTRL_PIN(0, "GBE0_SDP0"),
  41. PINCTRL_PIN(1, "GBE1_SDP0"),
  42. PINCTRL_PIN(2, "GBE0_SDP1"),
  43. PINCTRL_PIN(3, "GBE1_SDP1"),
  44. PINCTRL_PIN(4, "GBE0_SDP2"),
  45. PINCTRL_PIN(5, "GBE1_SDP2"),
  46. PINCTRL_PIN(6, "GBE0_SDP3"),
  47. PINCTRL_PIN(7, "GBE1_SDP3"),
  48. PINCTRL_PIN(8, "GBE2_LED0"),
  49. PINCTRL_PIN(9, "GBE2_LED1"),
  50. PINCTRL_PIN(10, "GBE0_I2C_CLK"),
  51. PINCTRL_PIN(11, "GBE0_I2C_DATA"),
  52. PINCTRL_PIN(12, "GBE1_I2C_CLK"),
  53. PINCTRL_PIN(13, "GBE1_I2C_DATA"),
  54. PINCTRL_PIN(14, "NCSI_RXD0"),
  55. PINCTRL_PIN(15, "NCSI_CLK_IN"),
  56. PINCTRL_PIN(16, "NCSI_RXD1"),
  57. PINCTRL_PIN(17, "NCSI_CRS_DV"),
  58. PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"),
  59. PINCTRL_PIN(19, "NCSI_TX_EN"),
  60. PINCTRL_PIN(20, "NCSI_TXD0"),
  61. PINCTRL_PIN(21, "NCSI_TXD1"),
  62. PINCTRL_PIN(22, "NCSI_ARB_OUT"),
  63. PINCTRL_PIN(23, "GBE0_LED0"),
  64. PINCTRL_PIN(24, "GBE0_LED1"),
  65. PINCTRL_PIN(25, "GBE1_LED0"),
  66. PINCTRL_PIN(26, "GBE1_LED1"),
  67. PINCTRL_PIN(27, "SPARE_0"),
  68. PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
  69. PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
  70. PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
  71. PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
  72. PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
  73. PINCTRL_PIN(33, "GBE_MDC"),
  74. PINCTRL_PIN(34, "GBE_MDIO"),
  75. PINCTRL_PIN(35, "SVID_ALERT_N"),
  76. PINCTRL_PIN(36, "SVID_DATA"),
  77. PINCTRL_PIN(37, "SVID_CLK"),
  78. PINCTRL_PIN(38, "THERMTRIP_N"),
  79. PINCTRL_PIN(39, "PROCHOT_N"),
  80. PINCTRL_PIN(40, "MEMHOT_N"),
  81. /* South DFX */
  82. PINCTRL_PIN(41, "DFX_PORT_CLK0"),
  83. PINCTRL_PIN(42, "DFX_PORT_CLK1"),
  84. PINCTRL_PIN(43, "DFX_PORT0"),
  85. PINCTRL_PIN(44, "DFX_PORT1"),
  86. PINCTRL_PIN(45, "DFX_PORT2"),
  87. PINCTRL_PIN(46, "DFX_PORT3"),
  88. PINCTRL_PIN(47, "DFX_PORT4"),
  89. PINCTRL_PIN(48, "DFX_PORT5"),
  90. PINCTRL_PIN(49, "DFX_PORT6"),
  91. PINCTRL_PIN(50, "DFX_PORT7"),
  92. PINCTRL_PIN(51, "DFX_PORT8"),
  93. PINCTRL_PIN(52, "DFX_PORT9"),
  94. PINCTRL_PIN(53, "DFX_PORT10"),
  95. PINCTRL_PIN(54, "DFX_PORT11"),
  96. PINCTRL_PIN(55, "DFX_PORT12"),
  97. PINCTRL_PIN(56, "DFX_PORT13"),
  98. PINCTRL_PIN(57, "DFX_PORT14"),
  99. PINCTRL_PIN(58, "DFX_PORT15"),
  100. /* South GPP0 */
  101. PINCTRL_PIN(59, "SPI_TPM_CS_N"),
  102. PINCTRL_PIN(60, "UART2_CTS"),
  103. PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
  104. PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
  105. PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
  106. PINCTRL_PIN(64, "UART0_RXD"),
  107. PINCTRL_PIN(65, "UART0_TXD"),
  108. PINCTRL_PIN(66, "CPU_RESET_N"),
  109. PINCTRL_PIN(67, "NMI"),
  110. PINCTRL_PIN(68, "ERROR2_N"),
  111. PINCTRL_PIN(69, "ERROR1_N"),
  112. PINCTRL_PIN(70, "ERROR0_N"),
  113. PINCTRL_PIN(71, "IERR_N"),
  114. PINCTRL_PIN(72, "MCERR_N"),
  115. PINCTRL_PIN(73, "SMB0_LEG_CLK"),
  116. PINCTRL_PIN(74, "SMB0_LEG_DATA"),
  117. PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
  118. PINCTRL_PIN(76, "SMB1_HOST_DATA"),
  119. PINCTRL_PIN(77, "SMB1_HOST_CLK"),
  120. PINCTRL_PIN(78, "SMB2_PECI_DATA"),
  121. PINCTRL_PIN(79, "SMB2_PECI_CLK"),
  122. PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
  123. PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
  124. PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
  125. PINCTRL_PIN(83, "USB_OC0_N"),
  126. PINCTRL_PIN(84, "FLEX_CLK_SE0"),
  127. PINCTRL_PIN(85, "FLEX_CLK_SE1"),
  128. PINCTRL_PIN(86, "SPARE_4"),
  129. PINCTRL_PIN(87, "SMB3_IE0_CLK"),
  130. PINCTRL_PIN(88, "SMB3_IE0_DATA"),
  131. PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"),
  132. PINCTRL_PIN(90, "SATA0_LED_N"),
  133. PINCTRL_PIN(91, "SATA1_LED_N"),
  134. PINCTRL_PIN(92, "SATA_PDETECT0"),
  135. PINCTRL_PIN(93, "SATA_PDETECT1"),
  136. PINCTRL_PIN(94, "UART1_RTS"),
  137. PINCTRL_PIN(95, "UART1_CTS"),
  138. PINCTRL_PIN(96, "UART1_RXD"),
  139. PINCTRL_PIN(97, "UART1_TXD"),
  140. PINCTRL_PIN(98, "SPARE_8"),
  141. PINCTRL_PIN(99, "SPARE_9"),
  142. PINCTRL_PIN(100, "TCK"),
  143. PINCTRL_PIN(101, "TRST_N"),
  144. PINCTRL_PIN(102, "TMS"),
  145. PINCTRL_PIN(103, "TDI"),
  146. PINCTRL_PIN(104, "TDO"),
  147. PINCTRL_PIN(105, "CX_PRDY_N"),
  148. PINCTRL_PIN(106, "CX_PREQ_N"),
  149. PINCTRL_PIN(107, "TAP1_TCK"),
  150. PINCTRL_PIN(108, "TAP1_TRST_N"),
  151. PINCTRL_PIN(109, "TAP1_TMS"),
  152. PINCTRL_PIN(110, "TAP1_TDI"),
  153. PINCTRL_PIN(111, "TAP1_TDO"),
  154. /* South GPP1 */
  155. PINCTRL_PIN(112, "SUSPWRDNACK"),
  156. PINCTRL_PIN(113, "PMU_SUSCLK"),
  157. PINCTRL_PIN(114, "ADR_TRIGGER"),
  158. PINCTRL_PIN(115, "PMU_SLP_S45_N"),
  159. PINCTRL_PIN(116, "PMU_SLP_S3_N"),
  160. PINCTRL_PIN(117, "PMU_WAKE_N"),
  161. PINCTRL_PIN(118, "PMU_PWRBTN_N"),
  162. PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
  163. PINCTRL_PIN(120, "PMU_PLTRST_N"),
  164. PINCTRL_PIN(121, "SUS_STAT_N"),
  165. PINCTRL_PIN(122, "SLP_S0IX_N"),
  166. PINCTRL_PIN(123, "SPI_CS0_N"),
  167. PINCTRL_PIN(124, "SPI_CS1_N"),
  168. PINCTRL_PIN(125, "SPI_MOSI_IO0"),
  169. PINCTRL_PIN(126, "SPI_MISO_IO1"),
  170. PINCTRL_PIN(127, "SPI_IO2"),
  171. PINCTRL_PIN(128, "SPI_IO3"),
  172. PINCTRL_PIN(129, "SPI_CLK"),
  173. PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
  174. PINCTRL_PIN(131, "ESPI_IO0"),
  175. PINCTRL_PIN(132, "ESPI_IO1"),
  176. PINCTRL_PIN(133, "ESPI_IO2"),
  177. PINCTRL_PIN(134, "ESPI_IO3"),
  178. PINCTRL_PIN(135, "ESPI_CS0_N"),
  179. PINCTRL_PIN(136, "ESPI_CLK"),
  180. PINCTRL_PIN(137, "ESPI_RST_N"),
  181. PINCTRL_PIN(138, "ESPI_ALRT0_N"),
  182. PINCTRL_PIN(139, "ESPI_CS1_N"),
  183. PINCTRL_PIN(140, "ESPI_ALRT1_N"),
  184. PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
  185. PINCTRL_PIN(142, "EMMC_CMD"),
  186. PINCTRL_PIN(143, "EMMC_STROBE"),
  187. PINCTRL_PIN(144, "EMMC_CLK"),
  188. PINCTRL_PIN(145, "EMMC_D0"),
  189. PINCTRL_PIN(146, "EMMC_D1"),
  190. PINCTRL_PIN(147, "EMMC_D2"),
  191. PINCTRL_PIN(148, "EMMC_D3"),
  192. PINCTRL_PIN(149, "EMMC_D4"),
  193. PINCTRL_PIN(150, "EMMC_D5"),
  194. PINCTRL_PIN(151, "EMMC_D6"),
  195. PINCTRL_PIN(152, "EMMC_D7"),
  196. PINCTRL_PIN(153, "SPARE_3"),
  197. };
  198. static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
  199. static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
  200. static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
  201. static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
  202. static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };
  203. static const unsigned int dnv_emmc_pins[] = {
  204. 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
  205. };
  206. static const struct intel_pingroup dnv_groups[] = {
  207. PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
  208. PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
  209. PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
  210. PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
  211. };
  212. static const char * const dnv_uart0_groups[] = { "uart0_grp" };
  213. static const char * const dnv_uart1_groups[] = { "uart1_grp" };
  214. static const char * const dnv_uart2_groups[] = { "uart2_grp" };
  215. static const char * const dnv_emmc_groups[] = { "emmc_grp" };
  216. static const struct intel_function dnv_functions[] = {
  217. FUNCTION("uart0", dnv_uart0_groups),
  218. FUNCTION("uart1", dnv_uart1_groups),
  219. FUNCTION("uart2", dnv_uart2_groups),
  220. FUNCTION("emmc", dnv_emmc_groups),
  221. };
  222. static const struct intel_padgroup dnv_north_gpps[] = {
  223. DNV_GPP(0, 0, 31), /* North ALL_0 */
  224. DNV_GPP(1, 32, 40), /* North ALL_1 */
  225. };
  226. static const struct intel_padgroup dnv_south_gpps[] = {
  227. DNV_GPP(0, 41, 58), /* South DFX */
  228. DNV_GPP(1, 59, 90), /* South GPP0_0 */
  229. DNV_GPP(2, 91, 111), /* South GPP0_1 */
  230. DNV_GPP(3, 112, 143), /* South GPP1_0 */
  231. DNV_GPP(4, 144, 153), /* South GPP1_1 */
  232. };
  233. static const struct intel_community dnv_communities[] = {
  234. DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
  235. DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
  236. };
  237. static const struct intel_pinctrl_soc_data dnv_soc_data = {
  238. .pins = dnv_pins,
  239. .npins = ARRAY_SIZE(dnv_pins),
  240. .groups = dnv_groups,
  241. .ngroups = ARRAY_SIZE(dnv_groups),
  242. .functions = dnv_functions,
  243. .nfunctions = ARRAY_SIZE(dnv_functions),
  244. .communities = dnv_communities,
  245. .ncommunities = ARRAY_SIZE(dnv_communities),
  246. };
  247. static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
  248. static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
  249. { "INTC3000", (kernel_ulong_t)&dnv_soc_data },
  250. { }
  251. };
  252. MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
  253. static struct platform_driver dnv_pinctrl_driver = {
  254. .probe = intel_pinctrl_probe_by_hid,
  255. .driver = {
  256. .name = "denverton-pinctrl",
  257. .acpi_match_table = dnv_pinctrl_acpi_match,
  258. .pm = &dnv_pinctrl_pm_ops,
  259. },
  260. };
  261. static int __init dnv_pinctrl_init(void)
  262. {
  263. return platform_driver_register(&dnv_pinctrl_driver);
  264. }
  265. subsys_initcall(dnv_pinctrl_init);
  266. static void __exit dnv_pinctrl_exit(void)
  267. {
  268. platform_driver_unregister(&dnv_pinctrl_driver);
  269. }
  270. module_exit(dnv_pinctrl_exit);
  271. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  272. MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
  273. MODULE_LICENSE("GPL v2");