pinctrl-cherryview.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Cherryview/Braswell pinctrl driver
  4. *
  5. * Copyright (C) 2014, 2020 Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. *
  8. * This driver is based on the original Cherryview GPIO driver by
  9. * Ning Li <ning.li@intel.com>
  10. * Alan Cox <alan@linux.intel.com>
  11. */
  12. #include <linux/acpi.h>
  13. #include <linux/dmi.h>
  14. #include <linux/gpio/driver.h>
  15. #include <linux/kernel.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/types.h>
  19. #include <linux/pinctrl/pinctrl.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include <linux/pinctrl/pinconf.h>
  22. #include <linux/pinctrl/pinconf-generic.h>
  23. #include "pinctrl-intel.h"
  24. #define CHV_INTSTAT 0x300
  25. #define CHV_INTMASK 0x380
  26. #define FAMILY_PAD_REGS_OFF 0x4400
  27. #define FAMILY_PAD_REGS_SIZE 0x400
  28. #define MAX_FAMILY_PAD_GPIO_NO 15
  29. #define GPIO_REGS_SIZE 8
  30. #define CHV_PADCTRL0 0x000
  31. #define CHV_PADCTRL0_INTSEL_SHIFT 28
  32. #define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28)
  33. #define CHV_PADCTRL0_TERM_UP BIT(23)
  34. #define CHV_PADCTRL0_TERM_SHIFT 20
  35. #define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20)
  36. #define CHV_PADCTRL0_TERM_20K 1
  37. #define CHV_PADCTRL0_TERM_5K 2
  38. #define CHV_PADCTRL0_TERM_1K 4
  39. #define CHV_PADCTRL0_PMODE_SHIFT 16
  40. #define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16)
  41. #define CHV_PADCTRL0_GPIOEN BIT(15)
  42. #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
  43. #define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8)
  44. #define CHV_PADCTRL0_GPIOCFG_GPIO 0
  45. #define CHV_PADCTRL0_GPIOCFG_GPO 1
  46. #define CHV_PADCTRL0_GPIOCFG_GPI 2
  47. #define CHV_PADCTRL0_GPIOCFG_HIZ 3
  48. #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
  49. #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
  50. #define CHV_PADCTRL1 0x004
  51. #define CHV_PADCTRL1_CFGLOCK BIT(31)
  52. #define CHV_PADCTRL1_INVRXTX_SHIFT 4
  53. #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4)
  54. #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7)
  55. #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6)
  56. #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5)
  57. #define CHV_PADCTRL1_ODEN BIT(3)
  58. #define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0)
  59. #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
  60. #define CHV_PADCTRL1_INTWAKECFG_RISING 2
  61. #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
  62. #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
  63. struct intel_pad_context {
  64. u32 padctrl0;
  65. u32 padctrl1;
  66. };
  67. /**
  68. * struct intel_community_context - community context for Cherryview
  69. * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
  70. * @saved_intmask: Interrupt mask saved for system sleep
  71. */
  72. struct intel_community_context {
  73. unsigned int intr_lines[16];
  74. u32 saved_intmask;
  75. };
  76. #define PINMODE_INVERT_OE BIT(15)
  77. #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE))
  78. #define CHV_GPP(start, end) \
  79. { \
  80. .base = (start), \
  81. .size = (end) - (start) + 1, \
  82. }
  83. #define CHV_COMMUNITY(g, i, a) \
  84. { \
  85. .gpps = (g), \
  86. .ngpps = ARRAY_SIZE(g), \
  87. .nirqs = (i), \
  88. .acpi_space_id = (a), \
  89. }
  90. static const struct pinctrl_pin_desc southwest_pins[] = {
  91. PINCTRL_PIN(0, "FST_SPI_D2"),
  92. PINCTRL_PIN(1, "FST_SPI_D0"),
  93. PINCTRL_PIN(2, "FST_SPI_CLK"),
  94. PINCTRL_PIN(3, "FST_SPI_D3"),
  95. PINCTRL_PIN(4, "FST_SPI_CS1_B"),
  96. PINCTRL_PIN(5, "FST_SPI_D1"),
  97. PINCTRL_PIN(6, "FST_SPI_CS0_B"),
  98. PINCTRL_PIN(7, "FST_SPI_CS2_B"),
  99. PINCTRL_PIN(15, "UART1_RTS_B"),
  100. PINCTRL_PIN(16, "UART1_RXD"),
  101. PINCTRL_PIN(17, "UART2_RXD"),
  102. PINCTRL_PIN(18, "UART1_CTS_B"),
  103. PINCTRL_PIN(19, "UART2_RTS_B"),
  104. PINCTRL_PIN(20, "UART1_TXD"),
  105. PINCTRL_PIN(21, "UART2_TXD"),
  106. PINCTRL_PIN(22, "UART2_CTS_B"),
  107. PINCTRL_PIN(30, "MF_HDA_CLK"),
  108. PINCTRL_PIN(31, "MF_HDA_RSTB"),
  109. PINCTRL_PIN(32, "MF_HDA_SDIO"),
  110. PINCTRL_PIN(33, "MF_HDA_SDO"),
  111. PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
  112. PINCTRL_PIN(35, "MF_HDA_SYNC"),
  113. PINCTRL_PIN(36, "MF_HDA_SDI1"),
  114. PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
  115. PINCTRL_PIN(45, "I2C5_SDA"),
  116. PINCTRL_PIN(46, "I2C4_SDA"),
  117. PINCTRL_PIN(47, "I2C6_SDA"),
  118. PINCTRL_PIN(48, "I2C5_SCL"),
  119. PINCTRL_PIN(49, "I2C_NFC_SDA"),
  120. PINCTRL_PIN(50, "I2C4_SCL"),
  121. PINCTRL_PIN(51, "I2C6_SCL"),
  122. PINCTRL_PIN(52, "I2C_NFC_SCL"),
  123. PINCTRL_PIN(60, "I2C1_SDA"),
  124. PINCTRL_PIN(61, "I2C0_SDA"),
  125. PINCTRL_PIN(62, "I2C2_SDA"),
  126. PINCTRL_PIN(63, "I2C1_SCL"),
  127. PINCTRL_PIN(64, "I2C3_SDA"),
  128. PINCTRL_PIN(65, "I2C0_SCL"),
  129. PINCTRL_PIN(66, "I2C2_SCL"),
  130. PINCTRL_PIN(67, "I2C3_SCL"),
  131. PINCTRL_PIN(75, "SATA_GP0"),
  132. PINCTRL_PIN(76, "SATA_GP1"),
  133. PINCTRL_PIN(77, "SATA_LEDN"),
  134. PINCTRL_PIN(78, "SATA_GP2"),
  135. PINCTRL_PIN(79, "MF_SMB_ALERTB"),
  136. PINCTRL_PIN(80, "SATA_GP3"),
  137. PINCTRL_PIN(81, "MF_SMB_CLK"),
  138. PINCTRL_PIN(82, "MF_SMB_DATA"),
  139. PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
  140. PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
  141. PINCTRL_PIN(92, "GP_SSP_2_CLK"),
  142. PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
  143. PINCTRL_PIN(94, "GP_SSP_2_RXD"),
  144. PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
  145. PINCTRL_PIN(96, "GP_SSP_2_FS"),
  146. PINCTRL_PIN(97, "GP_SSP_2_TXD"),
  147. };
  148. static const unsigned southwest_uart0_pins[] = { 16, 20 };
  149. static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
  150. static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
  151. static const unsigned southwest_i2c0_pins[] = { 61, 65 };
  152. static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
  153. static const unsigned southwest_lpe_pins[] = {
  154. 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
  155. };
  156. static const unsigned southwest_i2c1_pins[] = { 60, 63 };
  157. static const unsigned southwest_i2c2_pins[] = { 62, 66 };
  158. static const unsigned southwest_i2c3_pins[] = { 64, 67 };
  159. static const unsigned southwest_i2c4_pins[] = { 46, 50 };
  160. static const unsigned southwest_i2c5_pins[] = { 45, 48 };
  161. static const unsigned southwest_i2c6_pins[] = { 47, 51 };
  162. static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
  163. static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
  164. /* Some of LPE I2S TXD pins need to have OE inversion set */
  165. static const unsigned int southwest_lpe_altfuncs[] = {
  166. PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
  167. PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
  168. PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
  169. };
  170. /*
  171. * Two spi3 chipselects are available in different mode than the main spi3
  172. * functionality, which is using mode 2.
  173. */
  174. static const unsigned int southwest_spi3_altfuncs[] = {
  175. PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
  176. PINMODE(2, 0), /* 82 */
  177. };
  178. static const struct intel_pingroup southwest_groups[] = {
  179. PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
  180. PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
  181. PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
  182. PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
  183. PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
  184. PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
  185. PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
  186. PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
  187. PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
  188. PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
  189. PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
  190. PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
  191. PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
  192. PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
  193. };
  194. static const char * const southwest_uart0_groups[] = { "uart0_grp" };
  195. static const char * const southwest_uart1_groups[] = { "uart1_grp" };
  196. static const char * const southwest_uart2_groups[] = { "uart2_grp" };
  197. static const char * const southwest_hda_groups[] = { "hda_grp" };
  198. static const char * const southwest_lpe_groups[] = { "lpe_grp" };
  199. static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
  200. static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
  201. static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
  202. static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
  203. static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
  204. static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
  205. static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
  206. static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
  207. static const char * const southwest_spi3_groups[] = { "spi3_grp" };
  208. /*
  209. * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
  210. * enabled only as GPIOs.
  211. */
  212. static const struct intel_function southwest_functions[] = {
  213. FUNCTION("uart0", southwest_uart0_groups),
  214. FUNCTION("uart1", southwest_uart1_groups),
  215. FUNCTION("uart2", southwest_uart2_groups),
  216. FUNCTION("hda", southwest_hda_groups),
  217. FUNCTION("lpe", southwest_lpe_groups),
  218. FUNCTION("i2c0", southwest_i2c0_groups),
  219. FUNCTION("i2c1", southwest_i2c1_groups),
  220. FUNCTION("i2c2", southwest_i2c2_groups),
  221. FUNCTION("i2c3", southwest_i2c3_groups),
  222. FUNCTION("i2c4", southwest_i2c4_groups),
  223. FUNCTION("i2c5", southwest_i2c5_groups),
  224. FUNCTION("i2c6", southwest_i2c6_groups),
  225. FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
  226. FUNCTION("spi3", southwest_spi3_groups),
  227. };
  228. static const struct intel_padgroup southwest_gpps[] = {
  229. CHV_GPP(0, 7),
  230. CHV_GPP(15, 22),
  231. CHV_GPP(30, 37),
  232. CHV_GPP(45, 52),
  233. CHV_GPP(60, 67),
  234. CHV_GPP(75, 82),
  235. CHV_GPP(90, 97),
  236. };
  237. /*
  238. * Southwest community can generate GPIO interrupts only for the first 8
  239. * interrupts. The upper half (8-15) can only be used to trigger GPEs.
  240. */
  241. static const struct intel_community southwest_communities[] = {
  242. CHV_COMMUNITY(southwest_gpps, 8, 0x91),
  243. };
  244. static const struct intel_pinctrl_soc_data southwest_soc_data = {
  245. .uid = "1",
  246. .pins = southwest_pins,
  247. .npins = ARRAY_SIZE(southwest_pins),
  248. .groups = southwest_groups,
  249. .ngroups = ARRAY_SIZE(southwest_groups),
  250. .functions = southwest_functions,
  251. .nfunctions = ARRAY_SIZE(southwest_functions),
  252. .communities = southwest_communities,
  253. .ncommunities = ARRAY_SIZE(southwest_communities),
  254. };
  255. static const struct pinctrl_pin_desc north_pins[] = {
  256. PINCTRL_PIN(0, "GPIO_DFX_0"),
  257. PINCTRL_PIN(1, "GPIO_DFX_3"),
  258. PINCTRL_PIN(2, "GPIO_DFX_7"),
  259. PINCTRL_PIN(3, "GPIO_DFX_1"),
  260. PINCTRL_PIN(4, "GPIO_DFX_5"),
  261. PINCTRL_PIN(5, "GPIO_DFX_4"),
  262. PINCTRL_PIN(6, "GPIO_DFX_8"),
  263. PINCTRL_PIN(7, "GPIO_DFX_2"),
  264. PINCTRL_PIN(8, "GPIO_DFX_6"),
  265. PINCTRL_PIN(15, "GPIO_SUS0"),
  266. PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
  267. PINCTRL_PIN(17, "GPIO_SUS3"),
  268. PINCTRL_PIN(18, "GPIO_SUS7"),
  269. PINCTRL_PIN(19, "GPIO_SUS1"),
  270. PINCTRL_PIN(20, "GPIO_SUS5"),
  271. PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
  272. PINCTRL_PIN(22, "GPIO_SUS4"),
  273. PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
  274. PINCTRL_PIN(24, "GPIO_SUS2"),
  275. PINCTRL_PIN(25, "GPIO_SUS6"),
  276. PINCTRL_PIN(26, "CX_PREQ_B"),
  277. PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
  278. PINCTRL_PIN(30, "TRST_B"),
  279. PINCTRL_PIN(31, "TCK"),
  280. PINCTRL_PIN(32, "PROCHOT_B"),
  281. PINCTRL_PIN(33, "SVIDO_DATA"),
  282. PINCTRL_PIN(34, "TMS"),
  283. PINCTRL_PIN(35, "CX_PRDY_B_2"),
  284. PINCTRL_PIN(36, "TDO_2"),
  285. PINCTRL_PIN(37, "CX_PRDY_B"),
  286. PINCTRL_PIN(38, "SVIDO_ALERT_B"),
  287. PINCTRL_PIN(39, "TDO"),
  288. PINCTRL_PIN(40, "SVIDO_CLK"),
  289. PINCTRL_PIN(41, "TDI"),
  290. PINCTRL_PIN(45, "GP_CAMERASB_05"),
  291. PINCTRL_PIN(46, "GP_CAMERASB_02"),
  292. PINCTRL_PIN(47, "GP_CAMERASB_08"),
  293. PINCTRL_PIN(48, "GP_CAMERASB_00"),
  294. PINCTRL_PIN(49, "GP_CAMERASB_06"),
  295. PINCTRL_PIN(50, "GP_CAMERASB_10"),
  296. PINCTRL_PIN(51, "GP_CAMERASB_03"),
  297. PINCTRL_PIN(52, "GP_CAMERASB_09"),
  298. PINCTRL_PIN(53, "GP_CAMERASB_01"),
  299. PINCTRL_PIN(54, "GP_CAMERASB_07"),
  300. PINCTRL_PIN(55, "GP_CAMERASB_11"),
  301. PINCTRL_PIN(56, "GP_CAMERASB_04"),
  302. PINCTRL_PIN(60, "PANEL0_BKLTEN"),
  303. PINCTRL_PIN(61, "HV_DDI0_HPD"),
  304. PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
  305. PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
  306. PINCTRL_PIN(64, "HV_DDI1_HPD"),
  307. PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
  308. PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
  309. PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
  310. PINCTRL_PIN(68, "HV_DDI2_HPD"),
  311. PINCTRL_PIN(69, "PANEL1_VDDEN"),
  312. PINCTRL_PIN(70, "PANEL1_BKLTEN"),
  313. PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
  314. PINCTRL_PIN(72, "PANEL0_VDDEN"),
  315. };
  316. static const struct intel_padgroup north_gpps[] = {
  317. CHV_GPP(0, 8),
  318. CHV_GPP(15, 27),
  319. CHV_GPP(30, 41),
  320. CHV_GPP(45, 56),
  321. CHV_GPP(60, 72),
  322. };
  323. /*
  324. * North community can generate GPIO interrupts only for the first 8
  325. * interrupts. The upper half (8-15) can only be used to trigger GPEs.
  326. */
  327. static const struct intel_community north_communities[] = {
  328. CHV_COMMUNITY(north_gpps, 8, 0x92),
  329. };
  330. static const struct intel_pinctrl_soc_data north_soc_data = {
  331. .uid = "2",
  332. .pins = north_pins,
  333. .npins = ARRAY_SIZE(north_pins),
  334. .communities = north_communities,
  335. .ncommunities = ARRAY_SIZE(north_communities),
  336. };
  337. static const struct pinctrl_pin_desc east_pins[] = {
  338. PINCTRL_PIN(0, "PMU_SLP_S3_B"),
  339. PINCTRL_PIN(1, "PMU_BATLOW_B"),
  340. PINCTRL_PIN(2, "SUS_STAT_B"),
  341. PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
  342. PINCTRL_PIN(4, "PMU_AC_PRESENT"),
  343. PINCTRL_PIN(5, "PMU_PLTRST_B"),
  344. PINCTRL_PIN(6, "PMU_SUSCLK"),
  345. PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
  346. PINCTRL_PIN(8, "PMU_PWRBTN_B"),
  347. PINCTRL_PIN(9, "PMU_SLP_S4_B"),
  348. PINCTRL_PIN(10, "PMU_WAKE_B"),
  349. PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
  350. PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
  351. PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
  352. PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
  353. PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
  354. PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
  355. PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
  356. PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
  357. PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
  358. PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
  359. PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
  360. PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
  361. PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
  362. };
  363. static const struct intel_padgroup east_gpps[] = {
  364. CHV_GPP(0, 11),
  365. CHV_GPP(15, 26),
  366. };
  367. static const struct intel_community east_communities[] = {
  368. CHV_COMMUNITY(east_gpps, 16, 0x93),
  369. };
  370. static const struct intel_pinctrl_soc_data east_soc_data = {
  371. .uid = "3",
  372. .pins = east_pins,
  373. .npins = ARRAY_SIZE(east_pins),
  374. .communities = east_communities,
  375. .ncommunities = ARRAY_SIZE(east_communities),
  376. };
  377. static const struct pinctrl_pin_desc southeast_pins[] = {
  378. PINCTRL_PIN(0, "MF_PLT_CLK0"),
  379. PINCTRL_PIN(1, "PWM1"),
  380. PINCTRL_PIN(2, "MF_PLT_CLK1"),
  381. PINCTRL_PIN(3, "MF_PLT_CLK4"),
  382. PINCTRL_PIN(4, "MF_PLT_CLK3"),
  383. PINCTRL_PIN(5, "PWM0"),
  384. PINCTRL_PIN(6, "MF_PLT_CLK5"),
  385. PINCTRL_PIN(7, "MF_PLT_CLK2"),
  386. PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
  387. PINCTRL_PIN(16, "SDMMC1_CLK"),
  388. PINCTRL_PIN(17, "SDMMC1_D0"),
  389. PINCTRL_PIN(18, "SDMMC2_D1"),
  390. PINCTRL_PIN(19, "SDMMC2_CLK"),
  391. PINCTRL_PIN(20, "SDMMC1_D2"),
  392. PINCTRL_PIN(21, "SDMMC2_D2"),
  393. PINCTRL_PIN(22, "SDMMC2_CMD"),
  394. PINCTRL_PIN(23, "SDMMC1_CMD"),
  395. PINCTRL_PIN(24, "SDMMC1_D1"),
  396. PINCTRL_PIN(25, "SDMMC2_D0"),
  397. PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
  398. PINCTRL_PIN(30, "SDMMC3_D1"),
  399. PINCTRL_PIN(31, "SDMMC3_CLK"),
  400. PINCTRL_PIN(32, "SDMMC3_D3"),
  401. PINCTRL_PIN(33, "SDMMC3_D2"),
  402. PINCTRL_PIN(34, "SDMMC3_CMD"),
  403. PINCTRL_PIN(35, "SDMMC3_D0"),
  404. PINCTRL_PIN(45, "MF_LPC_AD2"),
  405. PINCTRL_PIN(46, "LPC_CLKRUNB"),
  406. PINCTRL_PIN(47, "MF_LPC_AD0"),
  407. PINCTRL_PIN(48, "LPC_FRAMEB"),
  408. PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
  409. PINCTRL_PIN(50, "MF_LPC_AD3"),
  410. PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
  411. PINCTRL_PIN(52, "MF_LPC_AD1"),
  412. PINCTRL_PIN(60, "SPI1_MISO"),
  413. PINCTRL_PIN(61, "SPI1_CSO_B"),
  414. PINCTRL_PIN(62, "SPI1_CLK"),
  415. PINCTRL_PIN(63, "MMC1_D6"),
  416. PINCTRL_PIN(64, "SPI1_MOSI"),
  417. PINCTRL_PIN(65, "MMC1_D5"),
  418. PINCTRL_PIN(66, "SPI1_CS1_B"),
  419. PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
  420. PINCTRL_PIN(68, "MMC1_D7"),
  421. PINCTRL_PIN(69, "MMC1_RCLK"),
  422. PINCTRL_PIN(75, "USB_OC1_B"),
  423. PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
  424. PINCTRL_PIN(77, "GPIO_ALERT"),
  425. PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
  426. PINCTRL_PIN(79, "ILB_SERIRQ"),
  427. PINCTRL_PIN(80, "USB_OC0_B"),
  428. PINCTRL_PIN(81, "SDMMC3_CD_B"),
  429. PINCTRL_PIN(82, "SPKR"),
  430. PINCTRL_PIN(83, "SUSPWRDNACK"),
  431. PINCTRL_PIN(84, "SPARE_PIN"),
  432. PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
  433. };
  434. static const unsigned southeast_pwm0_pins[] = { 5 };
  435. static const unsigned southeast_pwm1_pins[] = { 1 };
  436. static const unsigned southeast_sdmmc1_pins[] = {
  437. 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
  438. };
  439. static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
  440. static const unsigned southeast_sdmmc3_pins[] = {
  441. 30, 31, 32, 33, 34, 35, 78, 81, 85,
  442. };
  443. static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
  444. static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
  445. static const struct intel_pingroup southeast_groups[] = {
  446. PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
  447. PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
  448. PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
  449. PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
  450. PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
  451. PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
  452. PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
  453. };
  454. static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
  455. static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
  456. static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
  457. static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
  458. static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
  459. static const char * const southeast_spi1_groups[] = { "spi1_grp" };
  460. static const char * const southeast_spi2_groups[] = { "spi2_grp" };
  461. static const struct intel_function southeast_functions[] = {
  462. FUNCTION("pwm0", southeast_pwm0_groups),
  463. FUNCTION("pwm1", southeast_pwm1_groups),
  464. FUNCTION("sdmmc1", southeast_sdmmc1_groups),
  465. FUNCTION("sdmmc2", southeast_sdmmc2_groups),
  466. FUNCTION("sdmmc3", southeast_sdmmc3_groups),
  467. FUNCTION("spi1", southeast_spi1_groups),
  468. FUNCTION("spi2", southeast_spi2_groups),
  469. };
  470. static const struct intel_padgroup southeast_gpps[] = {
  471. CHV_GPP(0, 7),
  472. CHV_GPP(15, 26),
  473. CHV_GPP(30, 35),
  474. CHV_GPP(45, 52),
  475. CHV_GPP(60, 69),
  476. CHV_GPP(75, 85),
  477. };
  478. static const struct intel_community southeast_communities[] = {
  479. CHV_COMMUNITY(southeast_gpps, 16, 0x94),
  480. };
  481. static const struct intel_pinctrl_soc_data southeast_soc_data = {
  482. .uid = "4",
  483. .pins = southeast_pins,
  484. .npins = ARRAY_SIZE(southeast_pins),
  485. .groups = southeast_groups,
  486. .ngroups = ARRAY_SIZE(southeast_groups),
  487. .functions = southeast_functions,
  488. .nfunctions = ARRAY_SIZE(southeast_functions),
  489. .communities = southeast_communities,
  490. .ncommunities = ARRAY_SIZE(southeast_communities),
  491. };
  492. static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
  493. &southwest_soc_data,
  494. &north_soc_data,
  495. &east_soc_data,
  496. &southeast_soc_data,
  497. NULL
  498. };
  499. /*
  500. * Lock to serialize register accesses
  501. *
  502. * Due to a silicon issue, a shared lock must be used to prevent
  503. * concurrent accesses across the 4 GPIO controllers.
  504. *
  505. * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
  506. * errata #CHT34, for further information.
  507. */
  508. static DEFINE_RAW_SPINLOCK(chv_lock);
  509. static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
  510. {
  511. const struct intel_community *community = &pctrl->communities[0];
  512. return readl(community->regs + offset);
  513. }
  514. static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
  515. {
  516. const struct intel_community *community = &pctrl->communities[0];
  517. void __iomem *reg = community->regs + offset;
  518. /* Write and simple read back to confirm the bus transferring done */
  519. writel(value, reg);
  520. readl(reg);
  521. }
  522. static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
  523. unsigned int reg)
  524. {
  525. const struct intel_community *community = &pctrl->communities[0];
  526. unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
  527. unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
  528. offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
  529. return community->pad_regs + offset + reg;
  530. }
  531. static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
  532. {
  533. return readl(chv_padreg(pctrl, pin, offset));
  534. }
  535. static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
  536. {
  537. void __iomem *reg = chv_padreg(pctrl, pin, offset);
  538. /* Write and simple read back to confirm the bus transferring done */
  539. writel(value, reg);
  540. readl(reg);
  541. }
  542. /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
  543. static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
  544. {
  545. return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
  546. }
  547. static int chv_get_groups_count(struct pinctrl_dev *pctldev)
  548. {
  549. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  550. return pctrl->soc->ngroups;
  551. }
  552. static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
  553. unsigned int group)
  554. {
  555. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  556. return pctrl->soc->groups[group].name;
  557. }
  558. static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
  559. const unsigned int **pins, unsigned int *npins)
  560. {
  561. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  562. *pins = pctrl->soc->groups[group].pins;
  563. *npins = pctrl->soc->groups[group].npins;
  564. return 0;
  565. }
  566. static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  567. unsigned int offset)
  568. {
  569. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  570. unsigned long flags;
  571. u32 ctrl0, ctrl1;
  572. bool locked;
  573. raw_spin_lock_irqsave(&chv_lock, flags);
  574. ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
  575. ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
  576. locked = chv_pad_locked(pctrl, offset);
  577. raw_spin_unlock_irqrestore(&chv_lock, flags);
  578. if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
  579. seq_puts(s, "GPIO ");
  580. } else {
  581. u32 mode;
  582. mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
  583. mode >>= CHV_PADCTRL0_PMODE_SHIFT;
  584. seq_printf(s, "mode %d ", mode);
  585. }
  586. seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
  587. if (locked)
  588. seq_puts(s, " [LOCKED]");
  589. }
  590. static const struct pinctrl_ops chv_pinctrl_ops = {
  591. .get_groups_count = chv_get_groups_count,
  592. .get_group_name = chv_get_group_name,
  593. .get_group_pins = chv_get_group_pins,
  594. .pin_dbg_show = chv_pin_dbg_show,
  595. };
  596. static int chv_get_functions_count(struct pinctrl_dev *pctldev)
  597. {
  598. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  599. return pctrl->soc->nfunctions;
  600. }
  601. static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
  602. unsigned int function)
  603. {
  604. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  605. return pctrl->soc->functions[function].name;
  606. }
  607. static int chv_get_function_groups(struct pinctrl_dev *pctldev,
  608. unsigned int function,
  609. const char * const **groups,
  610. unsigned int * const ngroups)
  611. {
  612. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  613. *groups = pctrl->soc->functions[function].groups;
  614. *ngroups = pctrl->soc->functions[function].ngroups;
  615. return 0;
  616. }
  617. static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
  618. unsigned int function, unsigned int group)
  619. {
  620. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  621. const struct intel_pingroup *grp;
  622. unsigned long flags;
  623. int i;
  624. grp = &pctrl->soc->groups[group];
  625. raw_spin_lock_irqsave(&chv_lock, flags);
  626. /* Check first that the pad is not locked */
  627. for (i = 0; i < grp->npins; i++) {
  628. if (chv_pad_locked(pctrl, grp->pins[i])) {
  629. dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
  630. grp->pins[i]);
  631. raw_spin_unlock_irqrestore(&chv_lock, flags);
  632. return -EBUSY;
  633. }
  634. }
  635. for (i = 0; i < grp->npins; i++) {
  636. int pin = grp->pins[i];
  637. unsigned int mode;
  638. bool invert_oe;
  639. u32 value;
  640. /* Check if there is pin-specific config */
  641. if (grp->modes)
  642. mode = grp->modes[i];
  643. else
  644. mode = grp->mode;
  645. /* Extract OE inversion */
  646. invert_oe = mode & PINMODE_INVERT_OE;
  647. mode &= ~PINMODE_INVERT_OE;
  648. value = chv_readl(pctrl, pin, CHV_PADCTRL0);
  649. /* Disable GPIO mode */
  650. value &= ~CHV_PADCTRL0_GPIOEN;
  651. /* Set to desired mode */
  652. value &= ~CHV_PADCTRL0_PMODE_MASK;
  653. value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
  654. chv_writel(pctrl, pin, CHV_PADCTRL0, value);
  655. /* Update for invert_oe */
  656. value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
  657. if (invert_oe)
  658. value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
  659. chv_writel(pctrl, pin, CHV_PADCTRL1, value);
  660. dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
  661. pin, mode, invert_oe ? "" : "not ");
  662. }
  663. raw_spin_unlock_irqrestore(&chv_lock, flags);
  664. return 0;
  665. }
  666. static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
  667. unsigned int offset)
  668. {
  669. u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
  670. u32 value;
  671. /*
  672. * One some devices the GPIO should output the inverted value from what
  673. * device-drivers / ACPI code expects (inverted external buffer?). The
  674. * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
  675. * preserve this flag if the pin is already setup as GPIO.
  676. */
  677. value = chv_readl(pctrl, offset, CHV_PADCTRL0);
  678. if (value & CHV_PADCTRL0_GPIOEN)
  679. invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
  680. value = chv_readl(pctrl, offset, CHV_PADCTRL1);
  681. value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
  682. value &= ~invrxtx_mask;
  683. chv_writel(pctrl, offset, CHV_PADCTRL1, value);
  684. }
  685. static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
  686. struct pinctrl_gpio_range *range,
  687. unsigned int offset)
  688. {
  689. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  690. unsigned long flags;
  691. u32 value;
  692. raw_spin_lock_irqsave(&chv_lock, flags);
  693. if (chv_pad_locked(pctrl, offset)) {
  694. value = chv_readl(pctrl, offset, CHV_PADCTRL0);
  695. if (!(value & CHV_PADCTRL0_GPIOEN)) {
  696. /* Locked so cannot enable */
  697. raw_spin_unlock_irqrestore(&chv_lock, flags);
  698. return -EBUSY;
  699. }
  700. } else {
  701. struct intel_community_context *cctx = &pctrl->context.communities[0];
  702. int i;
  703. /* Reset the interrupt mapping */
  704. for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
  705. if (cctx->intr_lines[i] == offset) {
  706. cctx->intr_lines[i] = 0;
  707. break;
  708. }
  709. }
  710. /* Disable interrupt generation */
  711. chv_gpio_clear_triggering(pctrl, offset);
  712. value = chv_readl(pctrl, offset, CHV_PADCTRL0);
  713. /*
  714. * If the pin is in HiZ mode (both TX and RX buffers are
  715. * disabled) we turn it to be input now.
  716. */
  717. if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
  718. (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
  719. value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
  720. value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
  721. }
  722. /* Switch to a GPIO mode */
  723. value |= CHV_PADCTRL0_GPIOEN;
  724. chv_writel(pctrl, offset, CHV_PADCTRL0, value);
  725. }
  726. raw_spin_unlock_irqrestore(&chv_lock, flags);
  727. return 0;
  728. }
  729. static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
  730. struct pinctrl_gpio_range *range,
  731. unsigned int offset)
  732. {
  733. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  734. unsigned long flags;
  735. raw_spin_lock_irqsave(&chv_lock, flags);
  736. if (!chv_pad_locked(pctrl, offset))
  737. chv_gpio_clear_triggering(pctrl, offset);
  738. raw_spin_unlock_irqrestore(&chv_lock, flags);
  739. }
  740. static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
  741. struct pinctrl_gpio_range *range,
  742. unsigned int offset, bool input)
  743. {
  744. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  745. unsigned long flags;
  746. u32 ctrl0;
  747. raw_spin_lock_irqsave(&chv_lock, flags);
  748. ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
  749. if (input)
  750. ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
  751. else
  752. ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
  753. chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
  754. raw_spin_unlock_irqrestore(&chv_lock, flags);
  755. return 0;
  756. }
  757. static const struct pinmux_ops chv_pinmux_ops = {
  758. .get_functions_count = chv_get_functions_count,
  759. .get_function_name = chv_get_function_name,
  760. .get_function_groups = chv_get_function_groups,
  761. .set_mux = chv_pinmux_set_mux,
  762. .gpio_request_enable = chv_gpio_request_enable,
  763. .gpio_disable_free = chv_gpio_disable_free,
  764. .gpio_set_direction = chv_gpio_set_direction,
  765. };
  766. static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
  767. unsigned long *config)
  768. {
  769. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  770. enum pin_config_param param = pinconf_to_config_param(*config);
  771. unsigned long flags;
  772. u32 ctrl0, ctrl1;
  773. u16 arg = 0;
  774. u32 term;
  775. raw_spin_lock_irqsave(&chv_lock, flags);
  776. ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
  777. ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
  778. raw_spin_unlock_irqrestore(&chv_lock, flags);
  779. term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
  780. switch (param) {
  781. case PIN_CONFIG_BIAS_DISABLE:
  782. if (term)
  783. return -EINVAL;
  784. break;
  785. case PIN_CONFIG_BIAS_PULL_UP:
  786. if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
  787. return -EINVAL;
  788. switch (term) {
  789. case CHV_PADCTRL0_TERM_20K:
  790. arg = 20000;
  791. break;
  792. case CHV_PADCTRL0_TERM_5K:
  793. arg = 5000;
  794. break;
  795. case CHV_PADCTRL0_TERM_1K:
  796. arg = 1000;
  797. break;
  798. }
  799. break;
  800. case PIN_CONFIG_BIAS_PULL_DOWN:
  801. if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
  802. return -EINVAL;
  803. switch (term) {
  804. case CHV_PADCTRL0_TERM_20K:
  805. arg = 20000;
  806. break;
  807. case CHV_PADCTRL0_TERM_5K:
  808. arg = 5000;
  809. break;
  810. }
  811. break;
  812. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  813. if (!(ctrl1 & CHV_PADCTRL1_ODEN))
  814. return -EINVAL;
  815. break;
  816. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
  817. u32 cfg;
  818. cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
  819. cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
  820. if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
  821. return -EINVAL;
  822. break;
  823. }
  824. default:
  825. return -ENOTSUPP;
  826. }
  827. *config = pinconf_to_config_packed(param, arg);
  828. return 0;
  829. }
  830. static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
  831. enum pin_config_param param, u32 arg)
  832. {
  833. unsigned long flags;
  834. u32 ctrl0, pull;
  835. raw_spin_lock_irqsave(&chv_lock, flags);
  836. ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
  837. switch (param) {
  838. case PIN_CONFIG_BIAS_DISABLE:
  839. ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
  840. break;
  841. case PIN_CONFIG_BIAS_PULL_UP:
  842. ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
  843. switch (arg) {
  844. case 1000:
  845. /* For 1k there is only pull up */
  846. pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
  847. break;
  848. case 5000:
  849. pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
  850. break;
  851. case 20000:
  852. pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
  853. break;
  854. default:
  855. raw_spin_unlock_irqrestore(&chv_lock, flags);
  856. return -EINVAL;
  857. }
  858. ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
  859. break;
  860. case PIN_CONFIG_BIAS_PULL_DOWN:
  861. ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
  862. switch (arg) {
  863. case 5000:
  864. pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
  865. break;
  866. case 20000:
  867. pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
  868. break;
  869. default:
  870. raw_spin_unlock_irqrestore(&chv_lock, flags);
  871. return -EINVAL;
  872. }
  873. ctrl0 |= pull;
  874. break;
  875. default:
  876. raw_spin_unlock_irqrestore(&chv_lock, flags);
  877. return -EINVAL;
  878. }
  879. chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
  880. raw_spin_unlock_irqrestore(&chv_lock, flags);
  881. return 0;
  882. }
  883. static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
  884. bool enable)
  885. {
  886. unsigned long flags;
  887. u32 ctrl1;
  888. raw_spin_lock_irqsave(&chv_lock, flags);
  889. ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
  890. if (enable)
  891. ctrl1 |= CHV_PADCTRL1_ODEN;
  892. else
  893. ctrl1 &= ~CHV_PADCTRL1_ODEN;
  894. chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
  895. raw_spin_unlock_irqrestore(&chv_lock, flags);
  896. return 0;
  897. }
  898. static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
  899. unsigned long *configs, unsigned int nconfigs)
  900. {
  901. struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
  902. enum pin_config_param param;
  903. int i, ret;
  904. u32 arg;
  905. if (chv_pad_locked(pctrl, pin))
  906. return -EBUSY;
  907. for (i = 0; i < nconfigs; i++) {
  908. param = pinconf_to_config_param(configs[i]);
  909. arg = pinconf_to_config_argument(configs[i]);
  910. switch (param) {
  911. case PIN_CONFIG_BIAS_DISABLE:
  912. case PIN_CONFIG_BIAS_PULL_UP:
  913. case PIN_CONFIG_BIAS_PULL_DOWN:
  914. ret = chv_config_set_pull(pctrl, pin, param, arg);
  915. if (ret)
  916. return ret;
  917. break;
  918. case PIN_CONFIG_DRIVE_PUSH_PULL:
  919. ret = chv_config_set_oden(pctrl, pin, false);
  920. if (ret)
  921. return ret;
  922. break;
  923. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  924. ret = chv_config_set_oden(pctrl, pin, true);
  925. if (ret)
  926. return ret;
  927. break;
  928. default:
  929. return -ENOTSUPP;
  930. }
  931. dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
  932. param, arg);
  933. }
  934. return 0;
  935. }
  936. static int chv_config_group_get(struct pinctrl_dev *pctldev,
  937. unsigned int group,
  938. unsigned long *config)
  939. {
  940. const unsigned int *pins;
  941. unsigned int npins;
  942. int ret;
  943. ret = chv_get_group_pins(pctldev, group, &pins, &npins);
  944. if (ret)
  945. return ret;
  946. ret = chv_config_get(pctldev, pins[0], config);
  947. if (ret)
  948. return ret;
  949. return 0;
  950. }
  951. static int chv_config_group_set(struct pinctrl_dev *pctldev,
  952. unsigned int group, unsigned long *configs,
  953. unsigned int num_configs)
  954. {
  955. const unsigned int *pins;
  956. unsigned int npins;
  957. int i, ret;
  958. ret = chv_get_group_pins(pctldev, group, &pins, &npins);
  959. if (ret)
  960. return ret;
  961. for (i = 0; i < npins; i++) {
  962. ret = chv_config_set(pctldev, pins[i], configs, num_configs);
  963. if (ret)
  964. return ret;
  965. }
  966. return 0;
  967. }
  968. static const struct pinconf_ops chv_pinconf_ops = {
  969. .is_generic = true,
  970. .pin_config_set = chv_config_set,
  971. .pin_config_get = chv_config_get,
  972. .pin_config_group_get = chv_config_group_get,
  973. .pin_config_group_set = chv_config_group_set,
  974. };
  975. static struct pinctrl_desc chv_pinctrl_desc = {
  976. .pctlops = &chv_pinctrl_ops,
  977. .pmxops = &chv_pinmux_ops,
  978. .confops = &chv_pinconf_ops,
  979. .owner = THIS_MODULE,
  980. };
  981. static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
  982. {
  983. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  984. unsigned long flags;
  985. u32 ctrl0, cfg;
  986. raw_spin_lock_irqsave(&chv_lock, flags);
  987. ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
  988. raw_spin_unlock_irqrestore(&chv_lock, flags);
  989. cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
  990. cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
  991. if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
  992. return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
  993. return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
  994. }
  995. static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
  996. {
  997. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  998. unsigned long flags;
  999. u32 ctrl0;
  1000. raw_spin_lock_irqsave(&chv_lock, flags);
  1001. ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
  1002. if (value)
  1003. ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
  1004. else
  1005. ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
  1006. chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
  1007. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1008. }
  1009. static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  1010. {
  1011. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  1012. u32 ctrl0, direction;
  1013. unsigned long flags;
  1014. raw_spin_lock_irqsave(&chv_lock, flags);
  1015. ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
  1016. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1017. direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
  1018. direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
  1019. if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
  1020. return GPIO_LINE_DIRECTION_OUT;
  1021. return GPIO_LINE_DIRECTION_IN;
  1022. }
  1023. static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
  1024. {
  1025. return pinctrl_gpio_direction_input(chip->base + offset);
  1026. }
  1027. static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
  1028. int value)
  1029. {
  1030. chv_gpio_set(chip, offset, value);
  1031. return pinctrl_gpio_direction_output(chip->base + offset);
  1032. }
  1033. static const struct gpio_chip chv_gpio_chip = {
  1034. .owner = THIS_MODULE,
  1035. .request = gpiochip_generic_request,
  1036. .free = gpiochip_generic_free,
  1037. .get_direction = chv_gpio_get_direction,
  1038. .direction_input = chv_gpio_direction_input,
  1039. .direction_output = chv_gpio_direction_output,
  1040. .get = chv_gpio_get,
  1041. .set = chv_gpio_set,
  1042. };
  1043. static void chv_gpio_irq_ack(struct irq_data *d)
  1044. {
  1045. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1046. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  1047. int pin = irqd_to_hwirq(d);
  1048. u32 intr_line;
  1049. raw_spin_lock(&chv_lock);
  1050. intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
  1051. intr_line &= CHV_PADCTRL0_INTSEL_MASK;
  1052. intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
  1053. chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
  1054. raw_spin_unlock(&chv_lock);
  1055. }
  1056. static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
  1057. {
  1058. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1059. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  1060. int pin = irqd_to_hwirq(d);
  1061. u32 value, intr_line;
  1062. unsigned long flags;
  1063. raw_spin_lock_irqsave(&chv_lock, flags);
  1064. intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
  1065. intr_line &= CHV_PADCTRL0_INTSEL_MASK;
  1066. intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
  1067. value = chv_pctrl_readl(pctrl, CHV_INTMASK);
  1068. if (mask)
  1069. value &= ~BIT(intr_line);
  1070. else
  1071. value |= BIT(intr_line);
  1072. chv_pctrl_writel(pctrl, CHV_INTMASK, value);
  1073. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1074. }
  1075. static void chv_gpio_irq_mask(struct irq_data *d)
  1076. {
  1077. chv_gpio_irq_mask_unmask(d, true);
  1078. }
  1079. static void chv_gpio_irq_unmask(struct irq_data *d)
  1080. {
  1081. chv_gpio_irq_mask_unmask(d, false);
  1082. }
  1083. static unsigned chv_gpio_irq_startup(struct irq_data *d)
  1084. {
  1085. /*
  1086. * Check if the interrupt has been requested with 0 as triggering
  1087. * type. In that case it is assumed that the current values
  1088. * programmed to the hardware are used (e.g BIOS configured
  1089. * defaults).
  1090. *
  1091. * In that case ->irq_set_type() will never be called so we need to
  1092. * read back the values from hardware now, set correct flow handler
  1093. * and update mappings before the interrupt is being used.
  1094. */
  1095. if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
  1096. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1097. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  1098. struct intel_community_context *cctx = &pctrl->context.communities[0];
  1099. unsigned int pin = irqd_to_hwirq(d);
  1100. irq_flow_handler_t handler;
  1101. unsigned long flags;
  1102. u32 intsel, value;
  1103. raw_spin_lock_irqsave(&chv_lock, flags);
  1104. intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
  1105. intsel &= CHV_PADCTRL0_INTSEL_MASK;
  1106. intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
  1107. value = chv_readl(pctrl, pin, CHV_PADCTRL1);
  1108. if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
  1109. handler = handle_level_irq;
  1110. else
  1111. handler = handle_edge_irq;
  1112. if (!cctx->intr_lines[intsel]) {
  1113. irq_set_handler_locked(d, handler);
  1114. cctx->intr_lines[intsel] = pin;
  1115. }
  1116. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1117. }
  1118. chv_gpio_irq_unmask(d);
  1119. return 0;
  1120. }
  1121. static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
  1122. {
  1123. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1124. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  1125. struct intel_community_context *cctx = &pctrl->context.communities[0];
  1126. unsigned int pin = irqd_to_hwirq(d);
  1127. unsigned long flags;
  1128. u32 value;
  1129. raw_spin_lock_irqsave(&chv_lock, flags);
  1130. /*
  1131. * Pins which can be used as shared interrupt are configured in
  1132. * BIOS. Driver trusts BIOS configurations and assigns different
  1133. * handler according to the irq type.
  1134. *
  1135. * Driver needs to save the mapping between each pin and
  1136. * its interrupt line.
  1137. * 1. If the pin cfg is locked in BIOS:
  1138. * Trust BIOS has programmed IntWakeCfg bits correctly,
  1139. * driver just needs to save the mapping.
  1140. * 2. If the pin cfg is not locked in BIOS:
  1141. * Driver programs the IntWakeCfg bits and save the mapping.
  1142. */
  1143. if (!chv_pad_locked(pctrl, pin)) {
  1144. value = chv_readl(pctrl, pin, CHV_PADCTRL1);
  1145. value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
  1146. value &= ~CHV_PADCTRL1_INVRXTX_MASK;
  1147. if (type & IRQ_TYPE_EDGE_BOTH) {
  1148. if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
  1149. value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
  1150. else if (type & IRQ_TYPE_EDGE_RISING)
  1151. value |= CHV_PADCTRL1_INTWAKECFG_RISING;
  1152. else if (type & IRQ_TYPE_EDGE_FALLING)
  1153. value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
  1154. } else if (type & IRQ_TYPE_LEVEL_MASK) {
  1155. value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
  1156. if (type & IRQ_TYPE_LEVEL_LOW)
  1157. value |= CHV_PADCTRL1_INVRXTX_RXDATA;
  1158. }
  1159. chv_writel(pctrl, pin, CHV_PADCTRL1, value);
  1160. }
  1161. value = chv_readl(pctrl, pin, CHV_PADCTRL0);
  1162. value &= CHV_PADCTRL0_INTSEL_MASK;
  1163. value >>= CHV_PADCTRL0_INTSEL_SHIFT;
  1164. cctx->intr_lines[value] = pin;
  1165. if (type & IRQ_TYPE_EDGE_BOTH)
  1166. irq_set_handler_locked(d, handle_edge_irq);
  1167. else if (type & IRQ_TYPE_LEVEL_MASK)
  1168. irq_set_handler_locked(d, handle_level_irq);
  1169. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1170. return 0;
  1171. }
  1172. static void chv_gpio_irq_handler(struct irq_desc *desc)
  1173. {
  1174. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  1175. struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
  1176. const struct intel_community *community = &pctrl->communities[0];
  1177. struct intel_community_context *cctx = &pctrl->context.communities[0];
  1178. struct irq_chip *chip = irq_desc_get_chip(desc);
  1179. unsigned long pending;
  1180. unsigned long flags;
  1181. u32 intr_line;
  1182. chained_irq_enter(chip, desc);
  1183. raw_spin_lock_irqsave(&chv_lock, flags);
  1184. pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
  1185. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1186. for_each_set_bit(intr_line, &pending, community->nirqs) {
  1187. unsigned int irq, offset;
  1188. offset = cctx->intr_lines[intr_line];
  1189. irq = irq_find_mapping(gc->irq.domain, offset);
  1190. generic_handle_irq(irq);
  1191. }
  1192. chained_irq_exit(chip, desc);
  1193. }
  1194. /*
  1195. * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
  1196. * tables. Since we leave GPIOs that are not capable of generating
  1197. * interrupts out of the irqdomain the numbering will be different and
  1198. * cause devices using the hardcoded IRQ numbers fail. In order not to
  1199. * break such machines we will only mask pins from irqdomain if the machine
  1200. * is not listed below.
  1201. */
  1202. static const struct dmi_system_id chv_no_valid_mask[] = {
  1203. /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
  1204. {
  1205. .ident = "Intel_Strago based Chromebooks (All models)",
  1206. .matches = {
  1207. DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
  1208. DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
  1209. },
  1210. },
  1211. {
  1212. .ident = "HP Chromebook 11 G5 (Setzer)",
  1213. .matches = {
  1214. DMI_MATCH(DMI_SYS_VENDOR, "HP"),
  1215. DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
  1216. },
  1217. },
  1218. {
  1219. .ident = "Acer Chromebook R11 (Cyan)",
  1220. .matches = {
  1221. DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
  1222. DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
  1223. },
  1224. },
  1225. {
  1226. .ident = "Samsung Chromebook 3 (Celes)",
  1227. .matches = {
  1228. DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
  1229. DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
  1230. },
  1231. },
  1232. {}
  1233. };
  1234. static void chv_init_irq_valid_mask(struct gpio_chip *chip,
  1235. unsigned long *valid_mask,
  1236. unsigned int ngpios)
  1237. {
  1238. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  1239. const struct intel_community *community = &pctrl->communities[0];
  1240. int i;
  1241. /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
  1242. for (i = 0; i < pctrl->soc->npins; i++) {
  1243. const struct pinctrl_pin_desc *desc;
  1244. u32 intsel;
  1245. desc = &pctrl->soc->pins[i];
  1246. intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
  1247. intsel &= CHV_PADCTRL0_INTSEL_MASK;
  1248. intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
  1249. if (intsel >= community->nirqs)
  1250. clear_bit(desc->number, valid_mask);
  1251. }
  1252. }
  1253. static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
  1254. {
  1255. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  1256. const struct intel_community *community = &pctrl->communities[0];
  1257. /*
  1258. * The same set of machines in chv_no_valid_mask[] have incorrectly
  1259. * configured GPIOs that generate spurious interrupts so we use
  1260. * this same list to apply another quirk for them.
  1261. *
  1262. * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
  1263. */
  1264. if (!pctrl->chip.irq.init_valid_mask) {
  1265. /*
  1266. * Mask all interrupts the community is able to generate
  1267. * but leave the ones that can only generate GPEs unmasked.
  1268. */
  1269. chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
  1270. }
  1271. /* Clear all interrupts */
  1272. chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
  1273. return 0;
  1274. }
  1275. static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
  1276. {
  1277. struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
  1278. const struct intel_community *community = &pctrl->communities[0];
  1279. const struct intel_padgroup *gpp;
  1280. int ret, i;
  1281. for (i = 0; i < community->ngpps; i++) {
  1282. gpp = &community->gpps[i];
  1283. ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
  1284. gpp->base, gpp->base,
  1285. gpp->size);
  1286. if (ret) {
  1287. dev_err(pctrl->dev, "failed to add GPIO pin range\n");
  1288. return ret;
  1289. }
  1290. }
  1291. return 0;
  1292. }
  1293. static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
  1294. {
  1295. const struct intel_community *community = &pctrl->communities[0];
  1296. const struct intel_padgroup *gpp;
  1297. struct gpio_chip *chip = &pctrl->chip;
  1298. bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
  1299. int ret, i, irq_base;
  1300. *chip = chv_gpio_chip;
  1301. chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
  1302. chip->label = dev_name(pctrl->dev);
  1303. chip->add_pin_ranges = chv_gpio_add_pin_ranges;
  1304. chip->parent = pctrl->dev;
  1305. chip->base = -1;
  1306. pctrl->irq = irq;
  1307. pctrl->irqchip.name = "chv-gpio";
  1308. pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
  1309. pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
  1310. pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
  1311. pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
  1312. pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
  1313. pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
  1314. chip->irq.chip = &pctrl->irqchip;
  1315. chip->irq.init_hw = chv_gpio_irq_init_hw;
  1316. chip->irq.parent_handler = chv_gpio_irq_handler;
  1317. chip->irq.num_parents = 1;
  1318. chip->irq.parents = &pctrl->irq;
  1319. chip->irq.default_type = IRQ_TYPE_NONE;
  1320. chip->irq.handler = handle_bad_irq;
  1321. if (need_valid_mask) {
  1322. chip->irq.init_valid_mask = chv_init_irq_valid_mask;
  1323. } else {
  1324. irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
  1325. pctrl->soc->npins, NUMA_NO_NODE);
  1326. if (irq_base < 0) {
  1327. dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
  1328. return irq_base;
  1329. }
  1330. }
  1331. ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
  1332. if (ret) {
  1333. dev_err(pctrl->dev, "Failed to register gpiochip\n");
  1334. return ret;
  1335. }
  1336. if (!need_valid_mask) {
  1337. for (i = 0; i < community->ngpps; i++) {
  1338. gpp = &community->gpps[i];
  1339. irq_domain_associate_many(chip->irq.domain, irq_base,
  1340. gpp->base, gpp->size);
  1341. irq_base += gpp->size;
  1342. }
  1343. }
  1344. return 0;
  1345. }
  1346. static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
  1347. acpi_physical_address address, u32 bits, u64 *value,
  1348. void *handler_context, void *region_context)
  1349. {
  1350. struct intel_pinctrl *pctrl = region_context;
  1351. unsigned long flags;
  1352. acpi_status ret = AE_OK;
  1353. raw_spin_lock_irqsave(&chv_lock, flags);
  1354. if (function == ACPI_WRITE)
  1355. chv_pctrl_writel(pctrl, address, *value);
  1356. else if (function == ACPI_READ)
  1357. *value = chv_pctrl_readl(pctrl, address);
  1358. else
  1359. ret = AE_BAD_PARAMETER;
  1360. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1361. return ret;
  1362. }
  1363. static int chv_pinctrl_probe(struct platform_device *pdev)
  1364. {
  1365. const struct intel_pinctrl_soc_data *soc_data;
  1366. struct intel_community *community;
  1367. struct device *dev = &pdev->dev;
  1368. struct acpi_device *adev = ACPI_COMPANION(dev);
  1369. struct intel_pinctrl *pctrl;
  1370. acpi_status status;
  1371. int ret, irq;
  1372. soc_data = intel_pinctrl_get_soc_data(pdev);
  1373. if (IS_ERR(soc_data))
  1374. return PTR_ERR(soc_data);
  1375. pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
  1376. if (!pctrl)
  1377. return -ENOMEM;
  1378. pctrl->dev = dev;
  1379. pctrl->soc = soc_data;
  1380. pctrl->ncommunities = pctrl->soc->ncommunities;
  1381. pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
  1382. pctrl->ncommunities * sizeof(*pctrl->communities),
  1383. GFP_KERNEL);
  1384. if (!pctrl->communities)
  1385. return -ENOMEM;
  1386. community = &pctrl->communities[0];
  1387. community->regs = devm_platform_ioremap_resource(pdev, 0);
  1388. if (IS_ERR(community->regs))
  1389. return PTR_ERR(community->regs);
  1390. community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
  1391. #ifdef CONFIG_PM_SLEEP
  1392. pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
  1393. sizeof(*pctrl->context.pads),
  1394. GFP_KERNEL);
  1395. if (!pctrl->context.pads)
  1396. return -ENOMEM;
  1397. #endif
  1398. pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
  1399. sizeof(*pctrl->context.communities),
  1400. GFP_KERNEL);
  1401. if (!pctrl->context.communities)
  1402. return -ENOMEM;
  1403. irq = platform_get_irq(pdev, 0);
  1404. if (irq < 0)
  1405. return irq;
  1406. pctrl->pctldesc = chv_pinctrl_desc;
  1407. pctrl->pctldesc.name = dev_name(dev);
  1408. pctrl->pctldesc.pins = pctrl->soc->pins;
  1409. pctrl->pctldesc.npins = pctrl->soc->npins;
  1410. pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
  1411. if (IS_ERR(pctrl->pctldev)) {
  1412. dev_err(dev, "failed to register pinctrl driver\n");
  1413. return PTR_ERR(pctrl->pctldev);
  1414. }
  1415. ret = chv_gpio_probe(pctrl, irq);
  1416. if (ret)
  1417. return ret;
  1418. status = acpi_install_address_space_handler(adev->handle,
  1419. community->acpi_space_id,
  1420. chv_pinctrl_mmio_access_handler,
  1421. NULL, pctrl);
  1422. if (ACPI_FAILURE(status))
  1423. dev_err(dev, "failed to install ACPI addr space handler\n");
  1424. platform_set_drvdata(pdev, pctrl);
  1425. return 0;
  1426. }
  1427. static int chv_pinctrl_remove(struct platform_device *pdev)
  1428. {
  1429. struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
  1430. const struct intel_community *community = &pctrl->communities[0];
  1431. acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
  1432. community->acpi_space_id,
  1433. chv_pinctrl_mmio_access_handler);
  1434. return 0;
  1435. }
  1436. #ifdef CONFIG_PM_SLEEP
  1437. static int chv_pinctrl_suspend_noirq(struct device *dev)
  1438. {
  1439. struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
  1440. struct intel_community_context *cctx = &pctrl->context.communities[0];
  1441. unsigned long flags;
  1442. int i;
  1443. raw_spin_lock_irqsave(&chv_lock, flags);
  1444. cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
  1445. for (i = 0; i < pctrl->soc->npins; i++) {
  1446. const struct pinctrl_pin_desc *desc;
  1447. struct intel_pad_context *ctx = &pctrl->context.pads[i];
  1448. desc = &pctrl->soc->pins[i];
  1449. if (chv_pad_locked(pctrl, desc->number))
  1450. continue;
  1451. ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
  1452. ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
  1453. ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
  1454. }
  1455. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1456. return 0;
  1457. }
  1458. static int chv_pinctrl_resume_noirq(struct device *dev)
  1459. {
  1460. struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
  1461. struct intel_community_context *cctx = &pctrl->context.communities[0];
  1462. unsigned long flags;
  1463. int i;
  1464. raw_spin_lock_irqsave(&chv_lock, flags);
  1465. /*
  1466. * Mask all interrupts before restoring per-pin configuration
  1467. * registers because we don't know in which state BIOS left them
  1468. * upon exiting suspend.
  1469. */
  1470. chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
  1471. for (i = 0; i < pctrl->soc->npins; i++) {
  1472. const struct pinctrl_pin_desc *desc;
  1473. struct intel_pad_context *ctx = &pctrl->context.pads[i];
  1474. u32 val;
  1475. desc = &pctrl->soc->pins[i];
  1476. if (chv_pad_locked(pctrl, desc->number))
  1477. continue;
  1478. /* Only restore if our saved state differs from the current */
  1479. val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
  1480. val &= ~CHV_PADCTRL0_GPIORXSTATE;
  1481. if (ctx->padctrl0 != val) {
  1482. chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
  1483. dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
  1484. desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
  1485. }
  1486. val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
  1487. if (ctx->padctrl1 != val) {
  1488. chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
  1489. dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
  1490. desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
  1491. }
  1492. }
  1493. /*
  1494. * Now that all pins are restored to known state, we can restore
  1495. * the interrupt mask register as well.
  1496. */
  1497. chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
  1498. chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
  1499. raw_spin_unlock_irqrestore(&chv_lock, flags);
  1500. return 0;
  1501. }
  1502. #endif
  1503. static const struct dev_pm_ops chv_pinctrl_pm_ops = {
  1504. SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
  1505. chv_pinctrl_resume_noirq)
  1506. };
  1507. static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
  1508. { "INT33FF", (kernel_ulong_t)chv_soc_data },
  1509. { }
  1510. };
  1511. MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
  1512. static struct platform_driver chv_pinctrl_driver = {
  1513. .probe = chv_pinctrl_probe,
  1514. .remove = chv_pinctrl_remove,
  1515. .driver = {
  1516. .name = "cherryview-pinctrl",
  1517. .pm = &chv_pinctrl_pm_ops,
  1518. .acpi_match_table = chv_pinctrl_acpi_match,
  1519. },
  1520. };
  1521. static int __init chv_pinctrl_init(void)
  1522. {
  1523. return platform_driver_register(&chv_pinctrl_driver);
  1524. }
  1525. subsys_initcall(chv_pinctrl_init);
  1526. static void __exit chv_pinctrl_exit(void)
  1527. {
  1528. platform_driver_unregister(&chv_pinctrl_driver);
  1529. }
  1530. module_exit(chv_pinctrl_exit);
  1531. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  1532. MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
  1533. MODULE_LICENSE("GPL v2");