pinctrl-cedarfork.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Cedar Fork PCH pinctrl/GPIO driver
  4. *
  5. * Copyright (C) 2017, Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. */
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include "pinctrl-intel.h"
  13. #define CDF_PAD_OWN 0x020
  14. #define CDF_PADCFGLOCK 0x0c0
  15. #define CDF_HOSTSW_OWN 0x120
  16. #define CDF_GPI_IS 0x200
  17. #define CDF_GPI_IE 0x230
  18. #define CDF_GPP(r, s, e) \
  19. { \
  20. .reg_num = (r), \
  21. .base = (s), \
  22. .size = ((e) - (s) + 1), \
  23. }
  24. #define CDF_COMMUNITY(b, s, e, g) \
  25. { \
  26. .barno = (b), \
  27. .padown_offset = CDF_PAD_OWN, \
  28. .padcfglock_offset = CDF_PADCFGLOCK, \
  29. .hostown_offset = CDF_HOSTSW_OWN, \
  30. .is_offset = CDF_GPI_IS, \
  31. .ie_offset = CDF_GPI_IE, \
  32. .pin_base = (s), \
  33. .npins = ((e) - (s) + 1), \
  34. .gpps = (g), \
  35. .ngpps = ARRAY_SIZE(g), \
  36. }
  37. /* Cedar Fork PCH */
  38. static const struct pinctrl_pin_desc cdf_pins[] = {
  39. /* WEST2 */
  40. PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"),
  41. PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"),
  42. PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"),
  43. PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"),
  44. PINCTRL_PIN(4, "GBE0_I2C_CLK"),
  45. PINCTRL_PIN(5, "GBE0_I2C_DATA"),
  46. PINCTRL_PIN(6, "GBE1_I2C_CLK"),
  47. PINCTRL_PIN(7, "GBE1_I2C_DATA"),
  48. PINCTRL_PIN(8, "GBE2_I2C_CLK"),
  49. PINCTRL_PIN(9, "GBE2_I2C_DATA"),
  50. PINCTRL_PIN(10, "GBE3_I2C_CLK"),
  51. PINCTRL_PIN(11, "GBE3_I2C_DATA"),
  52. PINCTRL_PIN(12, "GBE0_LED0"),
  53. PINCTRL_PIN(13, "GBE0_LED1"),
  54. PINCTRL_PIN(14, "GBE0_LED2"),
  55. PINCTRL_PIN(15, "GBE1_LED0"),
  56. PINCTRL_PIN(16, "GBE1_LED1"),
  57. PINCTRL_PIN(17, "GBE1_LED2"),
  58. PINCTRL_PIN(18, "GBE2_LED0"),
  59. PINCTRL_PIN(19, "GBE2_LED1"),
  60. PINCTRL_PIN(20, "GBE2_LED2"),
  61. PINCTRL_PIN(21, "GBE3_LED0"),
  62. PINCTRL_PIN(22, "GBE3_LED1"),
  63. PINCTRL_PIN(23, "GBE3_LED2"),
  64. /* WEST3 */
  65. PINCTRL_PIN(24, "NCSI_RXD0"),
  66. PINCTRL_PIN(25, "NCSI_CLK_IN"),
  67. PINCTRL_PIN(26, "NCSI_RXD1"),
  68. PINCTRL_PIN(27, "NCSI_CRS_DV"),
  69. PINCTRL_PIN(28, "NCSI_ARB_IN"),
  70. PINCTRL_PIN(29, "NCSI_TX_EN"),
  71. PINCTRL_PIN(30, "NCSI_TXD0"),
  72. PINCTRL_PIN(31, "NCSI_TXD1"),
  73. PINCTRL_PIN(32, "NCSI_ARB_OUT"),
  74. PINCTRL_PIN(33, "GBE_SMB_CLK"),
  75. PINCTRL_PIN(34, "GBE_SMB_DATA"),
  76. PINCTRL_PIN(35, "GBE_SMB_ALRT_N"),
  77. PINCTRL_PIN(36, "THERMTRIP_N"),
  78. PINCTRL_PIN(37, "PCHHOT_N"),
  79. PINCTRL_PIN(38, "ERROR0_N"),
  80. PINCTRL_PIN(39, "ERROR1_N"),
  81. PINCTRL_PIN(40, "ERROR2_N"),
  82. PINCTRL_PIN(41, "MSMI_N"),
  83. PINCTRL_PIN(42, "CATERR_N"),
  84. PINCTRL_PIN(43, "MEMTRIP_N"),
  85. PINCTRL_PIN(44, "UART0_RXD"),
  86. PINCTRL_PIN(45, "UART0_TXD"),
  87. PINCTRL_PIN(46, "GBE_UART_RXD"),
  88. PINCTRL_PIN(47, "GBE_UART_TXD"),
  89. /* WEST01 */
  90. PINCTRL_PIN(48, "GBE_GPIO13"),
  91. PINCTRL_PIN(49, "AUX_PWR"),
  92. PINCTRL_PIN(50, "UART0_RTS"),
  93. PINCTRL_PIN(51, "UART0_CTS"),
  94. PINCTRL_PIN(52, "FAN_PWM_0"),
  95. PINCTRL_PIN(53, "FAN_PWM_1"),
  96. PINCTRL_PIN(54, "FAN_PWM_2"),
  97. PINCTRL_PIN(55, "FAN_PWM_3"),
  98. PINCTRL_PIN(56, "FAN_TACH_0"),
  99. PINCTRL_PIN(57, "FAN_TACH_1"),
  100. PINCTRL_PIN(58, "FAN_TACH_2"),
  101. PINCTRL_PIN(59, "FAN_TACH_3"),
  102. PINCTRL_PIN(60, "ME_SMB0_CLK"),
  103. PINCTRL_PIN(61, "ME_SMB0_DATA"),
  104. PINCTRL_PIN(62, "ME_SMB0_ALRT_N"),
  105. PINCTRL_PIN(63, "ME_SMB1_CLK"),
  106. PINCTRL_PIN(64, "ME_SMB1_DATA"),
  107. PINCTRL_PIN(65, "ME_SMB1_ALRT_N"),
  108. PINCTRL_PIN(66, "ME_SMB2_CLK"),
  109. PINCTRL_PIN(67, "ME_SMB2_DATA"),
  110. PINCTRL_PIN(68, "ME_SMB2_ALRT_N"),
  111. PINCTRL_PIN(69, "GBE_MNG_I2C_CLK"),
  112. PINCTRL_PIN(70, "GBE_MNG_I2C_DATA"),
  113. /* WEST5 */
  114. PINCTRL_PIN(71, "IE_UART_RXD"),
  115. PINCTRL_PIN(72, "IE_UART_TXD"),
  116. PINCTRL_PIN(73, "VPP_SMB_CLK"),
  117. PINCTRL_PIN(74, "VPP_SMB_DATA"),
  118. PINCTRL_PIN(75, "VPP_SMB_ALRT_N"),
  119. PINCTRL_PIN(76, "PCIE_CLKREQ0_N"),
  120. PINCTRL_PIN(77, "PCIE_CLKREQ1_N"),
  121. PINCTRL_PIN(78, "PCIE_CLKREQ2_N"),
  122. PINCTRL_PIN(79, "PCIE_CLKREQ3_N"),
  123. PINCTRL_PIN(80, "PCIE_CLKREQ4_N"),
  124. PINCTRL_PIN(81, "PCIE_CLKREQ5_N"),
  125. PINCTRL_PIN(82, "PCIE_CLKREQ6_N"),
  126. PINCTRL_PIN(83, "PCIE_CLKREQ7_N"),
  127. PINCTRL_PIN(84, "PCIE_CLKREQ8_N"),
  128. PINCTRL_PIN(85, "PCIE_CLKREQ9_N"),
  129. PINCTRL_PIN(86, "FLEX_CLK_SE0"),
  130. PINCTRL_PIN(87, "FLEX_CLK_SE1"),
  131. PINCTRL_PIN(88, "FLEX_CLK1_50"),
  132. PINCTRL_PIN(89, "FLEX_CLK2_50"),
  133. PINCTRL_PIN(90, "FLEX_CLK_125"),
  134. /* WESTC */
  135. PINCTRL_PIN(91, "TCK_PCH"),
  136. PINCTRL_PIN(92, "JTAGX_PCH"),
  137. PINCTRL_PIN(93, "TRST_N_PCH"),
  138. PINCTRL_PIN(94, "TMS_PCH"),
  139. PINCTRL_PIN(95, "TDI_PCH"),
  140. PINCTRL_PIN(96, "TDO_PCH"),
  141. /* WESTC_DFX */
  142. PINCTRL_PIN(97, "CX_PRDY_N"),
  143. PINCTRL_PIN(98, "CX_PREQ_N"),
  144. PINCTRL_PIN(99, "CPU_FBREAK_OUT_N"),
  145. PINCTRL_PIN(100, "TRIGGER0_N"),
  146. PINCTRL_PIN(101, "TRIGGER1_N"),
  147. /* WESTA */
  148. PINCTRL_PIN(102, "DBG_PTI_CLK0"),
  149. PINCTRL_PIN(103, "DBG_PTI_CLK3"),
  150. PINCTRL_PIN(104, "DBG_PTI_DATA0"),
  151. PINCTRL_PIN(105, "DBG_PTI_DATA1"),
  152. PINCTRL_PIN(106, "DBG_PTI_DATA2"),
  153. PINCTRL_PIN(107, "DBG_PTI_DATA3"),
  154. PINCTRL_PIN(108, "DBG_PTI_DATA4"),
  155. PINCTRL_PIN(109, "DBG_PTI_DATA5"),
  156. PINCTRL_PIN(110, "DBG_PTI_DATA6"),
  157. PINCTRL_PIN(111, "DBG_PTI_DATA7"),
  158. /* WESTB */
  159. PINCTRL_PIN(112, "DBG_PTI_DATA8"),
  160. PINCTRL_PIN(113, "DBG_PTI_DATA9"),
  161. PINCTRL_PIN(114, "DBG_PTI_DATA10"),
  162. PINCTRL_PIN(115, "DBG_PTI_DATA11"),
  163. PINCTRL_PIN(116, "DBG_PTI_DATA12"),
  164. PINCTRL_PIN(117, "DBG_PTI_DATA13"),
  165. PINCTRL_PIN(118, "DBG_PTI_DATA14"),
  166. PINCTRL_PIN(119, "DBG_PTI_DATA15"),
  167. PINCTRL_PIN(120, "DBG_SPARE0"),
  168. PINCTRL_PIN(121, "DBG_SPARE1"),
  169. PINCTRL_PIN(122, "DBG_SPARE2"),
  170. PINCTRL_PIN(123, "DBG_SPARE3"),
  171. /* WESTD */
  172. PINCTRL_PIN(124, "CPU_PWR_GOOD"),
  173. PINCTRL_PIN(125, "PLTRST_CPU_N"),
  174. PINCTRL_PIN(126, "NAC_RESET_NAC_N"),
  175. PINCTRL_PIN(127, "PCH_SBLINK_RX"),
  176. PINCTRL_PIN(128, "PCH_SBLINK_TX"),
  177. PINCTRL_PIN(129, "PMSYNC_CLK"),
  178. PINCTRL_PIN(130, "CPU_ERR0_N"),
  179. PINCTRL_PIN(131, "CPU_ERR1_N"),
  180. PINCTRL_PIN(132, "CPU_ERR2_N"),
  181. PINCTRL_PIN(133, "CPU_THERMTRIP_N"),
  182. PINCTRL_PIN(134, "CPU_MSMI_N"),
  183. PINCTRL_PIN(135, "CPU_CATERR_N"),
  184. PINCTRL_PIN(136, "CPU_MEMTRIP_N"),
  185. PINCTRL_PIN(137, "NAC_GR_N"),
  186. PINCTRL_PIN(138, "NAC_XTAL_VALID"),
  187. PINCTRL_PIN(139, "NAC_WAKE_N"),
  188. PINCTRL_PIN(140, "NAC_SBLINK_CLK_S2N"),
  189. PINCTRL_PIN(141, "NAC_SBLINK_N2S"),
  190. PINCTRL_PIN(142, "NAC_SBLINK_S2N"),
  191. PINCTRL_PIN(143, "NAC_SBLINK_CLK_N2S"),
  192. /* WESTD_PECI */
  193. PINCTRL_PIN(144, "ME_PECI"),
  194. /* WESTF */
  195. PINCTRL_PIN(145, "NAC_RMII_CLK"),
  196. PINCTRL_PIN(146, "NAC_RGMII_CLK"),
  197. PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
  198. PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
  199. PINCTRL_PIN(149, "NAC_SPARE2"),
  200. PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
  201. PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
  202. PINCTRL_PIN(152, "NAC_GBE_GPIO1_S2N"),
  203. PINCTRL_PIN(153, "NAC_GBE_GPIO2_S2N"),
  204. PINCTRL_PIN(154, "NAC_GBE_GPIO3_S2N"),
  205. PINCTRL_PIN(155, "NAC_NCSI_RXD0"),
  206. PINCTRL_PIN(156, "NAC_NCSI_CLK_IN"),
  207. PINCTRL_PIN(157, "NAC_NCSI_RXD1"),
  208. PINCTRL_PIN(158, "NAC_NCSI_CRS_DV"),
  209. PINCTRL_PIN(159, "NAC_NCSI_ARB_IN"),
  210. PINCTRL_PIN(160, "NAC_NCSI_TX_EN"),
  211. PINCTRL_PIN(161, "NAC_NCSI_TXD0"),
  212. PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
  213. PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
  214. PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
  215. PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
  216. PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
  217. PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
  218. /* EAST2 */
  219. PINCTRL_PIN(168, "USB_OC0_N"),
  220. PINCTRL_PIN(169, "GBE_GPIO0"),
  221. PINCTRL_PIN(170, "GBE_GPIO1"),
  222. PINCTRL_PIN(171, "GBE_GPIO2"),
  223. PINCTRL_PIN(172, "GBE_GPIO3"),
  224. PINCTRL_PIN(173, "GBE_GPIO4"),
  225. PINCTRL_PIN(174, "GBE_GPIO5"),
  226. PINCTRL_PIN(175, "GBE_GPIO6"),
  227. PINCTRL_PIN(176, "GBE_GPIO7"),
  228. PINCTRL_PIN(177, "SPI_TPM_CS_N"),
  229. PINCTRL_PIN(178, "GBE_GPIO9"),
  230. PINCTRL_PIN(179, "GBE_GPIO10"),
  231. PINCTRL_PIN(180, "GBE_GPIO11"),
  232. PINCTRL_PIN(181, "GBE_GPIO12"),
  233. PINCTRL_PIN(182, "PECI_SMB_DATA"),
  234. PINCTRL_PIN(183, "SATA0_LED_N"),
  235. PINCTRL_PIN(184, "SATA1_LED_N"),
  236. PINCTRL_PIN(185, "SATA_PDETECT0"),
  237. PINCTRL_PIN(186, "SATA_PDETECT1"),
  238. PINCTRL_PIN(187, "SATA0_SDOUT"),
  239. PINCTRL_PIN(188, "SATA1_SDOUT"),
  240. PINCTRL_PIN(189, "SATA2_LED_N"),
  241. PINCTRL_PIN(190, "SATA_PDETECT2"),
  242. PINCTRL_PIN(191, "SATA2_SDOUT"),
  243. /* EAST3 */
  244. PINCTRL_PIN(192, "ESPI_IO0"),
  245. PINCTRL_PIN(193, "ESPI_IO1"),
  246. PINCTRL_PIN(194, "ESPI_IO2"),
  247. PINCTRL_PIN(195, "ESPI_IO3"),
  248. PINCTRL_PIN(196, "ESPI_CLK"),
  249. PINCTRL_PIN(197, "ESPI_RST_N"),
  250. PINCTRL_PIN(198, "ESPI_CS0_N"),
  251. PINCTRL_PIN(199, "ESPI_ALRT0_N"),
  252. PINCTRL_PIN(200, "ESPI_CS1_N"),
  253. PINCTRL_PIN(201, "ESPI_ALRT1_N"),
  254. PINCTRL_PIN(202, "ESPI_CLK_LOOPBK"),
  255. /* EAST0 */
  256. PINCTRL_PIN(203, "SPI_CS0_N"),
  257. PINCTRL_PIN(204, "SPI_CS1_N"),
  258. PINCTRL_PIN(205, "SPI_MOSI_IO0"),
  259. PINCTRL_PIN(206, "SPI_MISO_IO1"),
  260. PINCTRL_PIN(207, "SPI_IO2"),
  261. PINCTRL_PIN(208, "SPI_IO3"),
  262. PINCTRL_PIN(209, "SPI_CLK"),
  263. PINCTRL_PIN(210, "SPI_CLK_LOOPBK"),
  264. PINCTRL_PIN(211, "SUSPWRDNACK"),
  265. PINCTRL_PIN(212, "PMU_SUSCLK"),
  266. PINCTRL_PIN(213, "ADR_COMPLETE"),
  267. PINCTRL_PIN(214, "ADR_TRIGGER_N"),
  268. PINCTRL_PIN(215, "PMU_SLP_S45_N"),
  269. PINCTRL_PIN(216, "PMU_SLP_S3_N"),
  270. PINCTRL_PIN(217, "PMU_WAKE_N"),
  271. PINCTRL_PIN(218, "PMU_PWRBTN_N"),
  272. PINCTRL_PIN(219, "PMU_RESETBUTTON_N"),
  273. PINCTRL_PIN(220, "PMU_PLTRST_N"),
  274. PINCTRL_PIN(221, "SUS_STAT_N"),
  275. PINCTRL_PIN(222, "PMU_I2C_CLK"),
  276. PINCTRL_PIN(223, "PMU_I2C_DATA"),
  277. PINCTRL_PIN(224, "PECI_SMB_CLK"),
  278. PINCTRL_PIN(225, "PECI_SMB_ALRT_N"),
  279. /* EMMC */
  280. PINCTRL_PIN(226, "EMMC_CMD"),
  281. PINCTRL_PIN(227, "EMMC_STROBE"),
  282. PINCTRL_PIN(228, "EMMC_CLK"),
  283. PINCTRL_PIN(229, "EMMC_D0"),
  284. PINCTRL_PIN(230, "EMMC_D1"),
  285. PINCTRL_PIN(231, "EMMC_D2"),
  286. PINCTRL_PIN(232, "EMMC_D3"),
  287. PINCTRL_PIN(233, "EMMC_D4"),
  288. PINCTRL_PIN(234, "EMMC_D5"),
  289. PINCTRL_PIN(235, "EMMC_D6"),
  290. PINCTRL_PIN(236, "EMMC_D7"),
  291. };
  292. static const struct intel_padgroup cdf_community0_gpps[] = {
  293. CDF_GPP(0, 0, 23), /* WEST2 */
  294. CDF_GPP(1, 24, 47), /* WEST3 */
  295. CDF_GPP(2, 48, 70), /* WEST01 */
  296. CDF_GPP(3, 71, 90), /* WEST5 */
  297. CDF_GPP(4, 91, 96), /* WESTC */
  298. CDF_GPP(5, 97, 101), /* WESTC_DFX */
  299. CDF_GPP(6, 102, 111), /* WESTA */
  300. CDF_GPP(7, 112, 123), /* WESTB */
  301. CDF_GPP(8, 124, 143), /* WESTD */
  302. CDF_GPP(9, 144, 144), /* WESTD_PECI */
  303. CDF_GPP(10, 145, 167), /* WESTF */
  304. };
  305. static const struct intel_padgroup cdf_community1_gpps[] = {
  306. CDF_GPP(0, 168, 191), /* EAST2 */
  307. CDF_GPP(1, 192, 202), /* EAST3 */
  308. CDF_GPP(2, 203, 225), /* EAST0 */
  309. CDF_GPP(3, 226, 236), /* EMMC */
  310. };
  311. static const struct intel_community cdf_communities[] = {
  312. CDF_COMMUNITY(0, 0, 167, cdf_community0_gpps), /* West */
  313. CDF_COMMUNITY(1, 168, 236, cdf_community1_gpps), /* East */
  314. };
  315. static const struct intel_pinctrl_soc_data cdf_soc_data = {
  316. .pins = cdf_pins,
  317. .npins = ARRAY_SIZE(cdf_pins),
  318. .communities = cdf_communities,
  319. .ncommunities = ARRAY_SIZE(cdf_communities),
  320. };
  321. static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
  322. static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
  323. { "INTC3001", (kernel_ulong_t)&cdf_soc_data },
  324. { }
  325. };
  326. MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match);
  327. static struct platform_driver cdf_pinctrl_driver = {
  328. .probe = intel_pinctrl_probe_by_hid,
  329. .driver = {
  330. .name = "cedarfork-pinctrl",
  331. .acpi_match_table = cdf_pinctrl_acpi_match,
  332. .pm = &cdf_pinctrl_pm_ops,
  333. },
  334. };
  335. static int __init cdf_pinctrl_init(void)
  336. {
  337. return platform_driver_register(&cdf_pinctrl_driver);
  338. }
  339. subsys_initcall(cdf_pinctrl_init);
  340. static void __exit cdf_pinctrl_exit(void)
  341. {
  342. platform_driver_unregister(&cdf_pinctrl_driver);
  343. }
  344. module_exit(cdf_pinctrl_exit);
  345. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  346. MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver");
  347. MODULE_LICENSE("GPL v2");