pinctrl-broxton.c 35 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Intel Broxton SoC pinctrl/GPIO driver
  4. *
  5. * Copyright (C) 2015, 2016 Intel Corporation
  6. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7. */
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include "pinctrl-intel.h"
  13. #define BXT_PAD_OWN 0x020
  14. #define BXT_PADCFGLOCK 0x060
  15. #define BXT_HOSTSW_OWN 0x080
  16. #define BXT_GPI_IS 0x100
  17. #define BXT_GPI_IE 0x110
  18. #define BXT_COMMUNITY(s, e) \
  19. { \
  20. .padown_offset = BXT_PAD_OWN, \
  21. .padcfglock_offset = BXT_PADCFGLOCK, \
  22. .hostown_offset = BXT_HOSTSW_OWN, \
  23. .is_offset = BXT_GPI_IS, \
  24. .ie_offset = BXT_GPI_IE, \
  25. .gpp_size = 32, \
  26. .pin_base = (s), \
  27. .npins = ((e) - (s) + 1), \
  28. }
  29. /* BXT */
  30. static const struct pinctrl_pin_desc bxt_north_pins[] = {
  31. PINCTRL_PIN(0, "GPIO_0"),
  32. PINCTRL_PIN(1, "GPIO_1"),
  33. PINCTRL_PIN(2, "GPIO_2"),
  34. PINCTRL_PIN(3, "GPIO_3"),
  35. PINCTRL_PIN(4, "GPIO_4"),
  36. PINCTRL_PIN(5, "GPIO_5"),
  37. PINCTRL_PIN(6, "GPIO_6"),
  38. PINCTRL_PIN(7, "GPIO_7"),
  39. PINCTRL_PIN(8, "GPIO_8"),
  40. PINCTRL_PIN(9, "GPIO_9"),
  41. PINCTRL_PIN(10, "GPIO_10"),
  42. PINCTRL_PIN(11, "GPIO_11"),
  43. PINCTRL_PIN(12, "GPIO_12"),
  44. PINCTRL_PIN(13, "GPIO_13"),
  45. PINCTRL_PIN(14, "GPIO_14"),
  46. PINCTRL_PIN(15, "GPIO_15"),
  47. PINCTRL_PIN(16, "GPIO_16"),
  48. PINCTRL_PIN(17, "GPIO_17"),
  49. PINCTRL_PIN(18, "GPIO_18"),
  50. PINCTRL_PIN(19, "GPIO_19"),
  51. PINCTRL_PIN(20, "GPIO_20"),
  52. PINCTRL_PIN(21, "GPIO_21"),
  53. PINCTRL_PIN(22, "GPIO_22"),
  54. PINCTRL_PIN(23, "GPIO_23"),
  55. PINCTRL_PIN(24, "GPIO_24"),
  56. PINCTRL_PIN(25, "GPIO_25"),
  57. PINCTRL_PIN(26, "GPIO_26"),
  58. PINCTRL_PIN(27, "GPIO_27"),
  59. PINCTRL_PIN(28, "GPIO_28"),
  60. PINCTRL_PIN(29, "GPIO_29"),
  61. PINCTRL_PIN(30, "GPIO_30"),
  62. PINCTRL_PIN(31, "GPIO_31"),
  63. PINCTRL_PIN(32, "GPIO_32"),
  64. PINCTRL_PIN(33, "GPIO_33"),
  65. PINCTRL_PIN(34, "PWM0"),
  66. PINCTRL_PIN(35, "PWM1"),
  67. PINCTRL_PIN(36, "PWM2"),
  68. PINCTRL_PIN(37, "PWM3"),
  69. PINCTRL_PIN(38, "LPSS_UART0_RXD"),
  70. PINCTRL_PIN(39, "LPSS_UART0_TXD"),
  71. PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
  72. PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
  73. PINCTRL_PIN(42, "LPSS_UART1_RXD"),
  74. PINCTRL_PIN(43, "LPSS_UART1_TXD"),
  75. PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
  76. PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
  77. PINCTRL_PIN(46, "LPSS_UART2_RXD"),
  78. PINCTRL_PIN(47, "LPSS_UART2_TXD"),
  79. PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
  80. PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
  81. PINCTRL_PIN(50, "ISH_UART0_RXD"),
  82. PINCTRL_PIN(51, "ISH_UART0_TXT"),
  83. PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
  84. PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
  85. PINCTRL_PIN(54, "ISH_UART1_RXD"),
  86. PINCTRL_PIN(55, "ISH_UART1_TXT"),
  87. PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
  88. PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
  89. PINCTRL_PIN(58, "ISH_UART2_RXD"),
  90. PINCTRL_PIN(59, "ISH_UART2_TXD"),
  91. PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
  92. PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
  93. PINCTRL_PIN(62, "GP_CAMERASB00"),
  94. PINCTRL_PIN(63, "GP_CAMERASB01"),
  95. PINCTRL_PIN(64, "GP_CAMERASB02"),
  96. PINCTRL_PIN(65, "GP_CAMERASB03"),
  97. PINCTRL_PIN(66, "GP_CAMERASB04"),
  98. PINCTRL_PIN(67, "GP_CAMERASB05"),
  99. PINCTRL_PIN(68, "GP_CAMERASB06"),
  100. PINCTRL_PIN(69, "GP_CAMERASB07"),
  101. PINCTRL_PIN(70, "GP_CAMERASB08"),
  102. PINCTRL_PIN(71, "GP_CAMERASB09"),
  103. PINCTRL_PIN(72, "GP_CAMERASB10"),
  104. PINCTRL_PIN(73, "GP_CAMERASB11"),
  105. PINCTRL_PIN(74, "TCK"),
  106. PINCTRL_PIN(75, "TRST_B"),
  107. PINCTRL_PIN(76, "TMS"),
  108. PINCTRL_PIN(77, "TDI"),
  109. PINCTRL_PIN(78, "CX_PMODE"),
  110. PINCTRL_PIN(79, "CX_PREQ_B"),
  111. PINCTRL_PIN(80, "JTAGX"),
  112. PINCTRL_PIN(81, "CX_PRDY_B"),
  113. PINCTRL_PIN(82, "TDO"),
  114. };
  115. static const unsigned int bxt_north_pwm0_pins[] = { 34 };
  116. static const unsigned int bxt_north_pwm1_pins[] = { 35 };
  117. static const unsigned int bxt_north_pwm2_pins[] = { 36 };
  118. static const unsigned int bxt_north_pwm3_pins[] = { 37 };
  119. static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
  120. static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
  121. static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
  122. static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
  123. static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
  124. static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
  125. static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
  126. static const struct intel_pingroup bxt_north_groups[] = {
  127. PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
  128. PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1),
  129. PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1),
  130. PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1),
  131. PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1),
  132. PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1),
  133. PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1),
  134. PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2),
  135. PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2),
  136. PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2),
  137. PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3),
  138. };
  139. static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };
  140. static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };
  141. static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };
  142. static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };
  143. static const char * const bxt_north_uart0_groups[] = {
  144. "uart0_grp", "uart0b_grp",
  145. };
  146. static const char * const bxt_north_uart1_groups[] = {
  147. "uart1_grp", "uart1b_grp",
  148. };
  149. static const char * const bxt_north_uart2_groups[] = {
  150. "uart2_grp", "uart2b_grp",
  151. };
  152. static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };
  153. static const struct intel_function bxt_north_functions[] = {
  154. FUNCTION("pwm0", bxt_north_pwm0_groups),
  155. FUNCTION("pwm1", bxt_north_pwm1_groups),
  156. FUNCTION("pwm2", bxt_north_pwm2_groups),
  157. FUNCTION("pwm3", bxt_north_pwm3_groups),
  158. FUNCTION("uart0", bxt_north_uart0_groups),
  159. FUNCTION("uart1", bxt_north_uart1_groups),
  160. FUNCTION("uart2", bxt_north_uart2_groups),
  161. FUNCTION("uart3", bxt_north_uart3_groups),
  162. };
  163. static const struct intel_community bxt_north_communities[] = {
  164. BXT_COMMUNITY(0, 82),
  165. };
  166. static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
  167. .uid = "1",
  168. .pins = bxt_north_pins,
  169. .npins = ARRAY_SIZE(bxt_north_pins),
  170. .groups = bxt_north_groups,
  171. .ngroups = ARRAY_SIZE(bxt_north_groups),
  172. .functions = bxt_north_functions,
  173. .nfunctions = ARRAY_SIZE(bxt_north_functions),
  174. .communities = bxt_north_communities,
  175. .ncommunities = ARRAY_SIZE(bxt_north_communities),
  176. };
  177. static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
  178. PINCTRL_PIN(0, "PMC_SPI_FS0"),
  179. PINCTRL_PIN(1, "PMC_SPI_FS1"),
  180. PINCTRL_PIN(2, "PMC_SPI_FS2"),
  181. PINCTRL_PIN(3, "PMC_SPI_RXD"),
  182. PINCTRL_PIN(4, "PMC_SPI_TXD"),
  183. PINCTRL_PIN(5, "PMC_SPI_CLK"),
  184. PINCTRL_PIN(6, "PMC_UART_RXD"),
  185. PINCTRL_PIN(7, "PMC_UART_TXD"),
  186. PINCTRL_PIN(8, "PMIC_PWRGOOD"),
  187. PINCTRL_PIN(9, "PMIC_RESET_B"),
  188. PINCTRL_PIN(10, "RTC_CLK"),
  189. PINCTRL_PIN(11, "PMIC_SDWN_B"),
  190. PINCTRL_PIN(12, "PMIC_BCUDISW2"),
  191. PINCTRL_PIN(13, "PMIC_BCUDISCRIT"),
  192. PINCTRL_PIN(14, "PMIC_THERMTRIP_B"),
  193. PINCTRL_PIN(15, "PMIC_STDBY"),
  194. PINCTRL_PIN(16, "SVID0_ALERT_B"),
  195. PINCTRL_PIN(17, "SVID0_DATA"),
  196. PINCTRL_PIN(18, "SVID0_CLK"),
  197. PINCTRL_PIN(19, "PMIC_I2C_SCL"),
  198. PINCTRL_PIN(20, "PMIC_I2C_SDA"),
  199. PINCTRL_PIN(21, "AVS_I2S1_MCLK"),
  200. PINCTRL_PIN(22, "AVS_I2S1_BCLK"),
  201. PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"),
  202. PINCTRL_PIN(24, "AVS_I2S1_SDI"),
  203. PINCTRL_PIN(25, "AVS_I2S1_SDO"),
  204. PINCTRL_PIN(26, "AVS_M_CLK_A1"),
  205. PINCTRL_PIN(27, "AVS_M_CLK_B1"),
  206. PINCTRL_PIN(28, "AVS_M_DATA_1"),
  207. PINCTRL_PIN(29, "AVS_M_CLK_AB2"),
  208. PINCTRL_PIN(30, "AVS_M_DATA_2"),
  209. PINCTRL_PIN(31, "AVS_I2S2_MCLK"),
  210. PINCTRL_PIN(32, "AVS_I2S2_BCLK"),
  211. PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"),
  212. PINCTRL_PIN(34, "AVS_I2S2_SDI"),
  213. PINCTRL_PIN(35, "AVS_I2S2_SDOK"),
  214. PINCTRL_PIN(36, "AVS_I2S3_BCLK"),
  215. PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"),
  216. PINCTRL_PIN(38, "AVS_I2S3_SDI"),
  217. PINCTRL_PIN(39, "AVS_I2S3_SDO"),
  218. PINCTRL_PIN(40, "AVS_I2S4_BCLK"),
  219. PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"),
  220. PINCTRL_PIN(42, "AVS_I2S4_SDI"),
  221. PINCTRL_PIN(43, "AVS_I2S4_SDO"),
  222. PINCTRL_PIN(44, "PROCHOT_B"),
  223. PINCTRL_PIN(45, "FST_SPI_CS0_B"),
  224. PINCTRL_PIN(46, "FST_SPI_CS1_B"),
  225. PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"),
  226. PINCTRL_PIN(48, "FST_SPI_MISO_IO1"),
  227. PINCTRL_PIN(49, "FST_SPI_IO2"),
  228. PINCTRL_PIN(50, "FST_SPI_IO3"),
  229. PINCTRL_PIN(51, "FST_SPI_CLK"),
  230. PINCTRL_PIN(52, "FST_SPI_CLK_FB"),
  231. PINCTRL_PIN(53, "GP_SSP_0_CLK"),
  232. PINCTRL_PIN(54, "GP_SSP_0_FS0"),
  233. PINCTRL_PIN(55, "GP_SSP_0_FS1"),
  234. PINCTRL_PIN(56, "GP_SSP_0_FS2"),
  235. PINCTRL_PIN(57, "GP_SSP_0_RXD"),
  236. PINCTRL_PIN(58, "GP_SSP_0_TXD"),
  237. PINCTRL_PIN(59, "GP_SSP_1_CLK"),
  238. PINCTRL_PIN(60, "GP_SSP_1_FS0"),
  239. PINCTRL_PIN(61, "GP_SSP_1_FS1"),
  240. PINCTRL_PIN(62, "GP_SSP_1_FS2"),
  241. PINCTRL_PIN(63, "GP_SSP_1_FS3"),
  242. PINCTRL_PIN(64, "GP_SSP_1_RXD"),
  243. PINCTRL_PIN(65, "GP_SSP_1_TXD"),
  244. PINCTRL_PIN(66, "GP_SSP_2_CLK"),
  245. PINCTRL_PIN(67, "GP_SSP_2_FS0"),
  246. PINCTRL_PIN(68, "GP_SSP_2_FS1"),
  247. PINCTRL_PIN(69, "GP_SSP_2_FS2"),
  248. PINCTRL_PIN(70, "GP_SSP_2_RXD"),
  249. PINCTRL_PIN(71, "GP_SSP_2_TXD"),
  250. };
  251. static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
  252. static const unsigned int bxt_northwest_ssp1_pins[] = {
  253. 59, 60, 61, 62, 63, 64, 65
  254. };
  255. static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
  256. static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
  257. static const struct intel_pingroup bxt_northwest_groups[] = {
  258. PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
  259. PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1),
  260. PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1),
  261. PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2),
  262. };
  263. static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };
  264. static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };
  265. static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };
  266. static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };
  267. static const struct intel_function bxt_northwest_functions[] = {
  268. FUNCTION("ssp0", bxt_northwest_ssp0_groups),
  269. FUNCTION("ssp1", bxt_northwest_ssp1_groups),
  270. FUNCTION("ssp2", bxt_northwest_ssp2_groups),
  271. FUNCTION("uart3", bxt_northwest_uart3_groups),
  272. };
  273. static const struct intel_community bxt_northwest_communities[] = {
  274. BXT_COMMUNITY(0, 71),
  275. };
  276. static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
  277. .uid = "2",
  278. .pins = bxt_northwest_pins,
  279. .npins = ARRAY_SIZE(bxt_northwest_pins),
  280. .groups = bxt_northwest_groups,
  281. .ngroups = ARRAY_SIZE(bxt_northwest_groups),
  282. .functions = bxt_northwest_functions,
  283. .nfunctions = ARRAY_SIZE(bxt_northwest_functions),
  284. .communities = bxt_northwest_communities,
  285. .ncommunities = ARRAY_SIZE(bxt_northwest_communities),
  286. };
  287. static const struct pinctrl_pin_desc bxt_west_pins[] = {
  288. PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
  289. PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
  290. PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
  291. PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
  292. PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
  293. PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
  294. PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
  295. PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
  296. PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
  297. PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
  298. PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
  299. PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
  300. PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
  301. PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
  302. PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
  303. PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
  304. PINCTRL_PIN(16, "ISH_I2C0_SDA"),
  305. PINCTRL_PIN(17, "ISH_I2C0_SCL"),
  306. PINCTRL_PIN(18, "ISH_I2C1_SDA"),
  307. PINCTRL_PIN(19, "ISH_I2C1_SCL"),
  308. PINCTRL_PIN(20, "ISH_I2C2_SDA"),
  309. PINCTRL_PIN(21, "ISH_I2C2_SCL"),
  310. PINCTRL_PIN(22, "ISH_GPIO_0"),
  311. PINCTRL_PIN(23, "ISH_GPIO_1"),
  312. PINCTRL_PIN(24, "ISH_GPIO_2"),
  313. PINCTRL_PIN(25, "ISH_GPIO_3"),
  314. PINCTRL_PIN(26, "ISH_GPIO_4"),
  315. PINCTRL_PIN(27, "ISH_GPIO_5"),
  316. PINCTRL_PIN(28, "ISH_GPIO_6"),
  317. PINCTRL_PIN(29, "ISH_GPIO_7"),
  318. PINCTRL_PIN(30, "ISH_GPIO_8"),
  319. PINCTRL_PIN(31, "ISH_GPIO_9"),
  320. PINCTRL_PIN(32, "MODEM_CLKREQ"),
  321. PINCTRL_PIN(33, "DGCLKDBG_PMC_0"),
  322. PINCTRL_PIN(34, "DGCLKDBG_PMC_1"),
  323. PINCTRL_PIN(35, "DGCLKDBG_PMC_2"),
  324. PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"),
  325. PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"),
  326. PINCTRL_PIN(38, "OSC_CLK_OUT_0"),
  327. PINCTRL_PIN(39, "OSC_CLK_OUT_1"),
  328. PINCTRL_PIN(40, "OSC_CLK_OUT_2"),
  329. PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
  330. };
  331. static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 };
  332. static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 };
  333. static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 };
  334. static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 };
  335. static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 };
  336. static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 };
  337. static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 };
  338. static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 };
  339. static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 };
  340. static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 };
  341. static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 };
  342. static const struct intel_pingroup bxt_west_groups[] = {
  343. PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
  344. PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1),
  345. PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1),
  346. PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1),
  347. PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1),
  348. PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1),
  349. PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1),
  350. PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1),
  351. PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2),
  352. PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2),
  353. PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2),
  354. };
  355. static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };
  356. static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };
  357. static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };
  358. static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };
  359. static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };
  360. static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" };
  361. static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" };
  362. static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" };
  363. static const struct intel_function bxt_west_functions[] = {
  364. FUNCTION("i2c0", bxt_west_i2c0_groups),
  365. FUNCTION("i2c1", bxt_west_i2c1_groups),
  366. FUNCTION("i2c2", bxt_west_i2c2_groups),
  367. FUNCTION("i2c3", bxt_west_i2c3_groups),
  368. FUNCTION("i2c4", bxt_west_i2c4_groups),
  369. FUNCTION("i2c5", bxt_west_i2c5_groups),
  370. FUNCTION("i2c6", bxt_west_i2c6_groups),
  371. FUNCTION("i2c7", bxt_west_i2c7_groups),
  372. };
  373. static const struct intel_community bxt_west_communities[] = {
  374. BXT_COMMUNITY(0, 41),
  375. };
  376. static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
  377. .uid = "3",
  378. .pins = bxt_west_pins,
  379. .npins = ARRAY_SIZE(bxt_west_pins),
  380. .groups = bxt_west_groups,
  381. .ngroups = ARRAY_SIZE(bxt_west_groups),
  382. .functions = bxt_west_functions,
  383. .nfunctions = ARRAY_SIZE(bxt_west_functions),
  384. .communities = bxt_west_communities,
  385. .ncommunities = ARRAY_SIZE(bxt_west_communities),
  386. };
  387. static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
  388. PINCTRL_PIN(0, "EMMC0_CLK"),
  389. PINCTRL_PIN(1, "EMMC0_D0"),
  390. PINCTRL_PIN(2, "EMMC0_D1"),
  391. PINCTRL_PIN(3, "EMMC0_D2"),
  392. PINCTRL_PIN(4, "EMMC0_D3"),
  393. PINCTRL_PIN(5, "EMMC0_D4"),
  394. PINCTRL_PIN(6, "EMMC0_D5"),
  395. PINCTRL_PIN(7, "EMMC0_D6"),
  396. PINCTRL_PIN(8, "EMMC0_D7"),
  397. PINCTRL_PIN(9, "EMMC0_CMD"),
  398. PINCTRL_PIN(10, "SDIO_CLK"),
  399. PINCTRL_PIN(11, "SDIO_D0"),
  400. PINCTRL_PIN(12, "SDIO_D1"),
  401. PINCTRL_PIN(13, "SDIO_D2"),
  402. PINCTRL_PIN(14, "SDIO_D3"),
  403. PINCTRL_PIN(15, "SDIO_CMD"),
  404. PINCTRL_PIN(16, "SDCARD_CLK"),
  405. PINCTRL_PIN(17, "SDCARD_D0"),
  406. PINCTRL_PIN(18, "SDCARD_D1"),
  407. PINCTRL_PIN(19, "SDCARD_D2"),
  408. PINCTRL_PIN(20, "SDCARD_D3"),
  409. PINCTRL_PIN(21, "SDCARD_CD_B"),
  410. PINCTRL_PIN(22, "SDCARD_CMD"),
  411. PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"),
  412. PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"),
  413. PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"),
  414. PINCTRL_PIN(26, "EMMC0_STROBE"),
  415. PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"),
  416. PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"),
  417. PINCTRL_PIN(29, "SDCARD_LVL_SEL"),
  418. PINCTRL_PIN(30, "SDCARD_LVL_WP"),
  419. };
  420. static const unsigned int bxt_southwest_emmc0_pins[] = {
  421. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
  422. };
  423. static const unsigned int bxt_southwest_sdio_pins[] = {
  424. 10, 11, 12, 13, 14, 15, 27,
  425. };
  426. static const unsigned int bxt_southwest_sdcard_pins[] = {
  427. 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
  428. };
  429. static const struct intel_pingroup bxt_southwest_groups[] = {
  430. PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1),
  431. PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1),
  432. PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1),
  433. };
  434. static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };
  435. static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };
  436. static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };
  437. static const struct intel_function bxt_southwest_functions[] = {
  438. FUNCTION("emmc0", bxt_southwest_emmc0_groups),
  439. FUNCTION("sdio", bxt_southwest_sdio_groups),
  440. FUNCTION("sdcard", bxt_southwest_sdcard_groups),
  441. };
  442. static const struct intel_community bxt_southwest_communities[] = {
  443. BXT_COMMUNITY(0, 30),
  444. };
  445. static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
  446. .uid = "4",
  447. .pins = bxt_southwest_pins,
  448. .npins = ARRAY_SIZE(bxt_southwest_pins),
  449. .groups = bxt_southwest_groups,
  450. .ngroups = ARRAY_SIZE(bxt_southwest_groups),
  451. .functions = bxt_southwest_functions,
  452. .nfunctions = ARRAY_SIZE(bxt_southwest_functions),
  453. .communities = bxt_southwest_communities,
  454. .ncommunities = ARRAY_SIZE(bxt_southwest_communities),
  455. };
  456. static const struct pinctrl_pin_desc bxt_south_pins[] = {
  457. PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
  458. PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
  459. PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
  460. PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
  461. PINCTRL_PIN(4, "DBI_SDA"),
  462. PINCTRL_PIN(5, "DBI_SCL"),
  463. PINCTRL_PIN(6, "PANEL0_VDDEN"),
  464. PINCTRL_PIN(7, "PANEL0_BKLTEN"),
  465. PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
  466. PINCTRL_PIN(9, "PANEL1_VDDEN"),
  467. PINCTRL_PIN(10, "PANEL1_BKLTEN"),
  468. PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
  469. PINCTRL_PIN(12, "DBI_CSX"),
  470. PINCTRL_PIN(13, "DBI_RESX"),
  471. PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
  472. PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
  473. PINCTRL_PIN(16, "USB_OC0_B"),
  474. PINCTRL_PIN(17, "USB_OC1_B"),
  475. PINCTRL_PIN(18, "MEX_WAKE0_B"),
  476. PINCTRL_PIN(19, "MEX_WAKE1_B"),
  477. };
  478. static const struct intel_community bxt_south_communities[] = {
  479. BXT_COMMUNITY(0, 19),
  480. };
  481. static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
  482. .uid = "5",
  483. .pins = bxt_south_pins,
  484. .npins = ARRAY_SIZE(bxt_south_pins),
  485. .communities = bxt_south_communities,
  486. .ncommunities = ARRAY_SIZE(bxt_south_communities),
  487. };
  488. static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
  489. &bxt_north_soc_data,
  490. &bxt_northwest_soc_data,
  491. &bxt_west_soc_data,
  492. &bxt_southwest_soc_data,
  493. &bxt_south_soc_data,
  494. NULL
  495. };
  496. /* APL */
  497. static const struct pinctrl_pin_desc apl_north_pins[] = {
  498. PINCTRL_PIN(0, "GPIO_0"),
  499. PINCTRL_PIN(1, "GPIO_1"),
  500. PINCTRL_PIN(2, "GPIO_2"),
  501. PINCTRL_PIN(3, "GPIO_3"),
  502. PINCTRL_PIN(4, "GPIO_4"),
  503. PINCTRL_PIN(5, "GPIO_5"),
  504. PINCTRL_PIN(6, "GPIO_6"),
  505. PINCTRL_PIN(7, "GPIO_7"),
  506. PINCTRL_PIN(8, "GPIO_8"),
  507. PINCTRL_PIN(9, "GPIO_9"),
  508. PINCTRL_PIN(10, "GPIO_10"),
  509. PINCTRL_PIN(11, "GPIO_11"),
  510. PINCTRL_PIN(12, "GPIO_12"),
  511. PINCTRL_PIN(13, "GPIO_13"),
  512. PINCTRL_PIN(14, "GPIO_14"),
  513. PINCTRL_PIN(15, "GPIO_15"),
  514. PINCTRL_PIN(16, "GPIO_16"),
  515. PINCTRL_PIN(17, "GPIO_17"),
  516. PINCTRL_PIN(18, "GPIO_18"),
  517. PINCTRL_PIN(19, "GPIO_19"),
  518. PINCTRL_PIN(20, "GPIO_20"),
  519. PINCTRL_PIN(21, "GPIO_21"),
  520. PINCTRL_PIN(22, "GPIO_22"),
  521. PINCTRL_PIN(23, "GPIO_23"),
  522. PINCTRL_PIN(24, "GPIO_24"),
  523. PINCTRL_PIN(25, "GPIO_25"),
  524. PINCTRL_PIN(26, "GPIO_26"),
  525. PINCTRL_PIN(27, "GPIO_27"),
  526. PINCTRL_PIN(28, "GPIO_28"),
  527. PINCTRL_PIN(29, "GPIO_29"),
  528. PINCTRL_PIN(30, "GPIO_30"),
  529. PINCTRL_PIN(31, "GPIO_31"),
  530. PINCTRL_PIN(32, "GPIO_32"),
  531. PINCTRL_PIN(33, "GPIO_33"),
  532. PINCTRL_PIN(34, "PWM0"),
  533. PINCTRL_PIN(35, "PWM1"),
  534. PINCTRL_PIN(36, "PWM2"),
  535. PINCTRL_PIN(37, "PWM3"),
  536. PINCTRL_PIN(38, "LPSS_UART0_RXD"),
  537. PINCTRL_PIN(39, "LPSS_UART0_TXD"),
  538. PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
  539. PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
  540. PINCTRL_PIN(42, "LPSS_UART1_RXD"),
  541. PINCTRL_PIN(43, "LPSS_UART1_TXD"),
  542. PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
  543. PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
  544. PINCTRL_PIN(46, "LPSS_UART2_RXD"),
  545. PINCTRL_PIN(47, "LPSS_UART2_TXD"),
  546. PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
  547. PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
  548. PINCTRL_PIN(50, "GP_CAMERASB00"),
  549. PINCTRL_PIN(51, "GP_CAMERASB01"),
  550. PINCTRL_PIN(52, "GP_CAMERASB02"),
  551. PINCTRL_PIN(53, "GP_CAMERASB03"),
  552. PINCTRL_PIN(54, "GP_CAMERASB04"),
  553. PINCTRL_PIN(55, "GP_CAMERASB05"),
  554. PINCTRL_PIN(56, "GP_CAMERASB06"),
  555. PINCTRL_PIN(57, "GP_CAMERASB07"),
  556. PINCTRL_PIN(58, "GP_CAMERASB08"),
  557. PINCTRL_PIN(59, "GP_CAMERASB09"),
  558. PINCTRL_PIN(60, "GP_CAMERASB10"),
  559. PINCTRL_PIN(61, "GP_CAMERASB11"),
  560. PINCTRL_PIN(62, "TCK"),
  561. PINCTRL_PIN(63, "TRST_B"),
  562. PINCTRL_PIN(64, "TMS"),
  563. PINCTRL_PIN(65, "TDI"),
  564. PINCTRL_PIN(66, "CX_PMODE"),
  565. PINCTRL_PIN(67, "CX_PREQ_B"),
  566. PINCTRL_PIN(68, "JTAGX"),
  567. PINCTRL_PIN(69, "CX_PRDY_B"),
  568. PINCTRL_PIN(70, "TDO"),
  569. PINCTRL_PIN(71, "CNV_BRI_DT"),
  570. PINCTRL_PIN(72, "CNV_BRI_RSP"),
  571. PINCTRL_PIN(73, "CNV_RGI_DT"),
  572. PINCTRL_PIN(74, "CNV_RGI_RSP"),
  573. PINCTRL_PIN(75, "SVID0_ALERT_B"),
  574. PINCTRL_PIN(76, "SVID0_DATA"),
  575. PINCTRL_PIN(77, "SVID0_CLK"),
  576. };
  577. static const unsigned int apl_north_pwm0_pins[] = { 34 };
  578. static const unsigned int apl_north_pwm1_pins[] = { 35 };
  579. static const unsigned int apl_north_pwm2_pins[] = { 36 };
  580. static const unsigned int apl_north_pwm3_pins[] = { 37 };
  581. static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 };
  582. static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 };
  583. static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 };
  584. static const struct intel_pingroup apl_north_groups[] = {
  585. PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
  586. PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1),
  587. PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1),
  588. PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1),
  589. PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1),
  590. PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1),
  591. PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1),
  592. };
  593. static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };
  594. static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };
  595. static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };
  596. static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };
  597. static const char * const apl_north_uart0_groups[] = { "uart0_grp" };
  598. static const char * const apl_north_uart1_groups[] = { "uart1_grp" };
  599. static const char * const apl_north_uart2_groups[] = { "uart2_grp" };
  600. static const struct intel_function apl_north_functions[] = {
  601. FUNCTION("pwm0", apl_north_pwm0_groups),
  602. FUNCTION("pwm1", apl_north_pwm1_groups),
  603. FUNCTION("pwm2", apl_north_pwm2_groups),
  604. FUNCTION("pwm3", apl_north_pwm3_groups),
  605. FUNCTION("uart0", apl_north_uart0_groups),
  606. FUNCTION("uart1", apl_north_uart1_groups),
  607. FUNCTION("uart2", apl_north_uart2_groups),
  608. };
  609. static const struct intel_community apl_north_communities[] = {
  610. BXT_COMMUNITY(0, 77),
  611. };
  612. static const struct intel_pinctrl_soc_data apl_north_soc_data = {
  613. .uid = "1",
  614. .pins = apl_north_pins,
  615. .npins = ARRAY_SIZE(apl_north_pins),
  616. .groups = apl_north_groups,
  617. .ngroups = ARRAY_SIZE(apl_north_groups),
  618. .functions = apl_north_functions,
  619. .nfunctions = ARRAY_SIZE(apl_north_functions),
  620. .communities = apl_north_communities,
  621. .ncommunities = ARRAY_SIZE(apl_north_communities),
  622. };
  623. static const struct pinctrl_pin_desc apl_northwest_pins[] = {
  624. PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
  625. PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
  626. PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
  627. PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
  628. PINCTRL_PIN(4, "DBI_SDA"),
  629. PINCTRL_PIN(5, "DBI_SCL"),
  630. PINCTRL_PIN(6, "PANEL0_VDDEN"),
  631. PINCTRL_PIN(7, "PANEL0_BKLTEN"),
  632. PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
  633. PINCTRL_PIN(9, "PANEL1_VDDEN"),
  634. PINCTRL_PIN(10, "PANEL1_BKLTEN"),
  635. PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
  636. PINCTRL_PIN(12, "DBI_CSX"),
  637. PINCTRL_PIN(13, "DBI_RESX"),
  638. PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
  639. PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
  640. PINCTRL_PIN(16, "USB_OC0_B"),
  641. PINCTRL_PIN(17, "USB_OC1_B"),
  642. PINCTRL_PIN(18, "PMC_SPI_FS0"),
  643. PINCTRL_PIN(19, "PMC_SPI_FS1"),
  644. PINCTRL_PIN(20, "PMC_SPI_FS2"),
  645. PINCTRL_PIN(21, "PMC_SPI_RXD"),
  646. PINCTRL_PIN(22, "PMC_SPI_TXD"),
  647. PINCTRL_PIN(23, "PMC_SPI_CLK"),
  648. PINCTRL_PIN(24, "PMIC_PWRGOOD"),
  649. PINCTRL_PIN(25, "PMIC_RESET_B"),
  650. PINCTRL_PIN(26, "PMIC_SDWN_B"),
  651. PINCTRL_PIN(27, "PMIC_BCUDISW2"),
  652. PINCTRL_PIN(28, "PMIC_BCUDISCRIT"),
  653. PINCTRL_PIN(29, "PMIC_THERMTRIP_B"),
  654. PINCTRL_PIN(30, "PMIC_STDBY"),
  655. PINCTRL_PIN(31, "PROCHOT_B"),
  656. PINCTRL_PIN(32, "PMIC_I2C_SCL"),
  657. PINCTRL_PIN(33, "PMIC_I2C_SDA"),
  658. PINCTRL_PIN(34, "AVS_I2S1_MCLK"),
  659. PINCTRL_PIN(35, "AVS_I2S1_BCLK"),
  660. PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"),
  661. PINCTRL_PIN(37, "AVS_I2S1_SDI"),
  662. PINCTRL_PIN(38, "AVS_I2S1_SDO"),
  663. PINCTRL_PIN(39, "AVS_M_CLK_A1"),
  664. PINCTRL_PIN(40, "AVS_M_CLK_B1"),
  665. PINCTRL_PIN(41, "AVS_M_DATA_1"),
  666. PINCTRL_PIN(42, "AVS_M_CLK_AB2"),
  667. PINCTRL_PIN(43, "AVS_M_DATA_2"),
  668. PINCTRL_PIN(44, "AVS_I2S2_MCLK"),
  669. PINCTRL_PIN(45, "AVS_I2S2_BCLK"),
  670. PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"),
  671. PINCTRL_PIN(47, "AVS_I2S2_SDI"),
  672. PINCTRL_PIN(48, "AVS_I2S2_SDO"),
  673. PINCTRL_PIN(49, "AVS_I2S3_BCLK"),
  674. PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"),
  675. PINCTRL_PIN(51, "AVS_I2S3_SDI"),
  676. PINCTRL_PIN(52, "AVS_I2S3_SDO"),
  677. PINCTRL_PIN(53, "FST_SPI_CS0_B"),
  678. PINCTRL_PIN(54, "FST_SPI_CS1_B"),
  679. PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"),
  680. PINCTRL_PIN(56, "FST_SPI_MISO_IO1"),
  681. PINCTRL_PIN(57, "FST_SPI_IO2"),
  682. PINCTRL_PIN(58, "FST_SPI_IO3"),
  683. PINCTRL_PIN(59, "FST_SPI_CLK"),
  684. PINCTRL_PIN(60, "FST_SPI_CLK_FB"),
  685. PINCTRL_PIN(61, "GP_SSP_0_CLK"),
  686. PINCTRL_PIN(62, "GP_SSP_0_FS0"),
  687. PINCTRL_PIN(63, "GP_SSP_0_FS1"),
  688. PINCTRL_PIN(64, "GP_SSP_0_RXD"),
  689. PINCTRL_PIN(65, "GP_SSP_0_TXD"),
  690. PINCTRL_PIN(66, "GP_SSP_1_CLK"),
  691. PINCTRL_PIN(67, "GP_SSP_1_FS0"),
  692. PINCTRL_PIN(68, "GP_SSP_1_FS1"),
  693. PINCTRL_PIN(69, "GP_SSP_1_RXD"),
  694. PINCTRL_PIN(70, "GP_SSP_1_TXD"),
  695. PINCTRL_PIN(71, "GP_SSP_2_CLK"),
  696. PINCTRL_PIN(72, "GP_SSP_2_FS0"),
  697. PINCTRL_PIN(73, "GP_SSP_2_FS1"),
  698. PINCTRL_PIN(74, "GP_SSP_2_FS2"),
  699. PINCTRL_PIN(75, "GP_SSP_2_RXD"),
  700. PINCTRL_PIN(76, "GP_SSP_2_TXD"),
  701. };
  702. static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
  703. static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
  704. static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
  705. static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
  706. static const struct intel_pingroup apl_northwest_groups[] = {
  707. PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
  708. PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1),
  709. PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1),
  710. PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2),
  711. };
  712. static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };
  713. static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };
  714. static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };
  715. static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };
  716. static const struct intel_function apl_northwest_functions[] = {
  717. FUNCTION("ssp0", apl_northwest_ssp0_groups),
  718. FUNCTION("ssp1", apl_northwest_ssp1_groups),
  719. FUNCTION("ssp2", apl_northwest_ssp2_groups),
  720. FUNCTION("uart3", apl_northwest_uart3_groups),
  721. };
  722. static const struct intel_community apl_northwest_communities[] = {
  723. BXT_COMMUNITY(0, 76),
  724. };
  725. static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
  726. .uid = "2",
  727. .pins = apl_northwest_pins,
  728. .npins = ARRAY_SIZE(apl_northwest_pins),
  729. .groups = apl_northwest_groups,
  730. .ngroups = ARRAY_SIZE(apl_northwest_groups),
  731. .functions = apl_northwest_functions,
  732. .nfunctions = ARRAY_SIZE(apl_northwest_functions),
  733. .communities = apl_northwest_communities,
  734. .ncommunities = ARRAY_SIZE(apl_northwest_communities),
  735. };
  736. static const struct pinctrl_pin_desc apl_west_pins[] = {
  737. PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
  738. PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
  739. PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
  740. PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
  741. PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
  742. PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
  743. PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
  744. PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
  745. PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
  746. PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
  747. PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
  748. PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
  749. PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
  750. PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
  751. PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
  752. PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
  753. PINCTRL_PIN(16, "ISH_GPIO_0"),
  754. PINCTRL_PIN(17, "ISH_GPIO_1"),
  755. PINCTRL_PIN(18, "ISH_GPIO_2"),
  756. PINCTRL_PIN(19, "ISH_GPIO_3"),
  757. PINCTRL_PIN(20, "ISH_GPIO_4"),
  758. PINCTRL_PIN(21, "ISH_GPIO_5"),
  759. PINCTRL_PIN(22, "ISH_GPIO_6"),
  760. PINCTRL_PIN(23, "ISH_GPIO_7"),
  761. PINCTRL_PIN(24, "ISH_GPIO_8"),
  762. PINCTRL_PIN(25, "ISH_GPIO_9"),
  763. PINCTRL_PIN(26, "PCIE_CLKREQ0_B"),
  764. PINCTRL_PIN(27, "PCIE_CLKREQ1_B"),
  765. PINCTRL_PIN(28, "PCIE_CLKREQ2_B"),
  766. PINCTRL_PIN(29, "PCIE_CLKREQ3_B"),
  767. PINCTRL_PIN(30, "OSC_CLK_OUT_0"),
  768. PINCTRL_PIN(31, "OSC_CLK_OUT_1"),
  769. PINCTRL_PIN(32, "OSC_CLK_OUT_2"),
  770. PINCTRL_PIN(33, "OSC_CLK_OUT_3"),
  771. PINCTRL_PIN(34, "OSC_CLK_OUT_4"),
  772. PINCTRL_PIN(35, "PMU_AC_PRESENT"),
  773. PINCTRL_PIN(36, "PMU_BATLOW_B"),
  774. PINCTRL_PIN(37, "PMU_PLTRST_B"),
  775. PINCTRL_PIN(38, "PMU_PWRBTN_B"),
  776. PINCTRL_PIN(39, "PMU_RESETBUTTON_B"),
  777. PINCTRL_PIN(40, "PMU_SLP_S0_B"),
  778. PINCTRL_PIN(41, "PMU_SLP_S3_B"),
  779. PINCTRL_PIN(42, "PMU_SLP_S4_B"),
  780. PINCTRL_PIN(43, "PMU_SUSCLK"),
  781. PINCTRL_PIN(44, "PMU_WAKE_B"),
  782. PINCTRL_PIN(45, "SUS_STAT_B"),
  783. PINCTRL_PIN(46, "SUSPWRDNACK"),
  784. };
  785. static const unsigned int apl_west_i2c0_pins[] = { 0, 1 };
  786. static const unsigned int apl_west_i2c1_pins[] = { 2, 3 };
  787. static const unsigned int apl_west_i2c2_pins[] = { 4, 5 };
  788. static const unsigned int apl_west_i2c3_pins[] = { 6, 7 };
  789. static const unsigned int apl_west_i2c4_pins[] = { 8, 9 };
  790. static const unsigned int apl_west_i2c5_pins[] = { 10, 11 };
  791. static const unsigned int apl_west_i2c6_pins[] = { 12, 13 };
  792. static const unsigned int apl_west_i2c7_pins[] = { 14, 15 };
  793. static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 };
  794. static const struct intel_pingroup apl_west_groups[] = {
  795. PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
  796. PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1),
  797. PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1),
  798. PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1),
  799. PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1),
  800. PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1),
  801. PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1),
  802. PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1),
  803. PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3),
  804. };
  805. static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };
  806. static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };
  807. static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };
  808. static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };
  809. static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };
  810. static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };
  811. static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };
  812. static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };
  813. static const char * const apl_west_uart2_groups[] = { "uart2_grp" };
  814. static const struct intel_function apl_west_functions[] = {
  815. FUNCTION("i2c0", apl_west_i2c0_groups),
  816. FUNCTION("i2c1", apl_west_i2c1_groups),
  817. FUNCTION("i2c2", apl_west_i2c2_groups),
  818. FUNCTION("i2c3", apl_west_i2c3_groups),
  819. FUNCTION("i2c4", apl_west_i2c4_groups),
  820. FUNCTION("i2c5", apl_west_i2c5_groups),
  821. FUNCTION("i2c6", apl_west_i2c6_groups),
  822. FUNCTION("i2c7", apl_west_i2c7_groups),
  823. FUNCTION("uart2", apl_west_uart2_groups),
  824. };
  825. static const struct intel_community apl_west_communities[] = {
  826. BXT_COMMUNITY(0, 46),
  827. };
  828. static const struct intel_pinctrl_soc_data apl_west_soc_data = {
  829. .uid = "3",
  830. .pins = apl_west_pins,
  831. .npins = ARRAY_SIZE(apl_west_pins),
  832. .groups = apl_west_groups,
  833. .ngroups = ARRAY_SIZE(apl_west_groups),
  834. .functions = apl_west_functions,
  835. .nfunctions = ARRAY_SIZE(apl_west_functions),
  836. .communities = apl_west_communities,
  837. .ncommunities = ARRAY_SIZE(apl_west_communities),
  838. };
  839. static const struct pinctrl_pin_desc apl_southwest_pins[] = {
  840. PINCTRL_PIN(0, "PCIE_WAKE0_B"),
  841. PINCTRL_PIN(1, "PCIE_WAKE1_B"),
  842. PINCTRL_PIN(2, "PCIE_WAKE2_B"),
  843. PINCTRL_PIN(3, "PCIE_WAKE3_B"),
  844. PINCTRL_PIN(4, "EMMC0_CLK"),
  845. PINCTRL_PIN(5, "EMMC0_D0"),
  846. PINCTRL_PIN(6, "EMMC0_D1"),
  847. PINCTRL_PIN(7, "EMMC0_D2"),
  848. PINCTRL_PIN(8, "EMMC0_D3"),
  849. PINCTRL_PIN(9, "EMMC0_D4"),
  850. PINCTRL_PIN(10, "EMMC0_D5"),
  851. PINCTRL_PIN(11, "EMMC0_D6"),
  852. PINCTRL_PIN(12, "EMMC0_D7"),
  853. PINCTRL_PIN(13, "EMMC0_CMD"),
  854. PINCTRL_PIN(14, "SDIO_CLK"),
  855. PINCTRL_PIN(15, "SDIO_D0"),
  856. PINCTRL_PIN(16, "SDIO_D1"),
  857. PINCTRL_PIN(17, "SDIO_D2"),
  858. PINCTRL_PIN(18, "SDIO_D3"),
  859. PINCTRL_PIN(19, "SDIO_CMD"),
  860. PINCTRL_PIN(20, "SDCARD_CLK"),
  861. PINCTRL_PIN(21, "SDCARD_CLK_FB"),
  862. PINCTRL_PIN(22, "SDCARD_D0"),
  863. PINCTRL_PIN(23, "SDCARD_D1"),
  864. PINCTRL_PIN(24, "SDCARD_D2"),
  865. PINCTRL_PIN(25, "SDCARD_D3"),
  866. PINCTRL_PIN(26, "SDCARD_CD_B"),
  867. PINCTRL_PIN(27, "SDCARD_CMD"),
  868. PINCTRL_PIN(28, "SDCARD_LVL_WP"),
  869. PINCTRL_PIN(29, "EMMC0_STROBE"),
  870. PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"),
  871. PINCTRL_PIN(31, "SMB_ALERTB"),
  872. PINCTRL_PIN(32, "SMB_CLK"),
  873. PINCTRL_PIN(33, "SMB_DATA"),
  874. PINCTRL_PIN(34, "LPC_ILB_SERIRQ"),
  875. PINCTRL_PIN(35, "LPC_CLKOUT0"),
  876. PINCTRL_PIN(36, "LPC_CLKOUT1"),
  877. PINCTRL_PIN(37, "LPC_AD0"),
  878. PINCTRL_PIN(38, "LPC_AD1"),
  879. PINCTRL_PIN(39, "LPC_AD2"),
  880. PINCTRL_PIN(40, "LPC_AD3"),
  881. PINCTRL_PIN(41, "LPC_CLKRUNB"),
  882. PINCTRL_PIN(42, "LPC_FRAMEB"),
  883. };
  884. static const unsigned int apl_southwest_emmc0_pins[] = {
  885. 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
  886. };
  887. static const unsigned int apl_southwest_sdio_pins[] = {
  888. 14, 15, 16, 17, 18, 19, 30,
  889. };
  890. static const unsigned int apl_southwest_sdcard_pins[] = {
  891. 20, 21, 22, 23, 24, 25, 26, 27, 28,
  892. };
  893. static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 };
  894. static const struct intel_pingroup apl_southwest_groups[] = {
  895. PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
  896. PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1),
  897. PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1),
  898. PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2),
  899. };
  900. static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };
  901. static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };
  902. static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };
  903. static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };
  904. static const struct intel_function apl_southwest_functions[] = {
  905. FUNCTION("emmc0", apl_southwest_emmc0_groups),
  906. FUNCTION("sdio", apl_southwest_sdio_groups),
  907. FUNCTION("sdcard", apl_southwest_sdcard_groups),
  908. FUNCTION("i2c7", apl_southwest_i2c7_groups),
  909. };
  910. static const struct intel_community apl_southwest_communities[] = {
  911. BXT_COMMUNITY(0, 42),
  912. };
  913. static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
  914. .uid = "4",
  915. .pins = apl_southwest_pins,
  916. .npins = ARRAY_SIZE(apl_southwest_pins),
  917. .groups = apl_southwest_groups,
  918. .ngroups = ARRAY_SIZE(apl_southwest_groups),
  919. .functions = apl_southwest_functions,
  920. .nfunctions = ARRAY_SIZE(apl_southwest_functions),
  921. .communities = apl_southwest_communities,
  922. .ncommunities = ARRAY_SIZE(apl_southwest_communities),
  923. };
  924. static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
  925. &apl_north_soc_data,
  926. &apl_northwest_soc_data,
  927. &apl_west_soc_data,
  928. &apl_southwest_soc_data,
  929. NULL
  930. };
  931. static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
  932. { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data },
  933. { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data },
  934. { }
  935. };
  936. MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
  937. static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
  938. { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },
  939. { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
  940. { }
  941. };
  942. static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
  943. static struct platform_driver bxt_pinctrl_driver = {
  944. .probe = intel_pinctrl_probe_by_uid,
  945. .driver = {
  946. .name = "broxton-pinctrl",
  947. .acpi_match_table = bxt_pinctrl_acpi_match,
  948. .pm = &bxt_pinctrl_pm_ops,
  949. },
  950. .id_table = bxt_pinctrl_platform_ids,
  951. };
  952. static int __init bxt_pinctrl_init(void)
  953. {
  954. return platform_driver_register(&bxt_pinctrl_driver);
  955. }
  956. subsys_initcall(bxt_pinctrl_init);
  957. static void __exit bxt_pinctrl_exit(void)
  958. {
  959. platform_driver_unregister(&bxt_pinctrl_driver);
  960. }
  961. module_exit(bxt_pinctrl_exit);
  962. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  963. MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
  964. MODULE_LICENSE("GPL v2");
  965. MODULE_ALIAS("platform:broxton-pinctrl");