pinctrl-baytrail.c 48 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Pinctrl GPIO driver for Intel Baytrail
  4. *
  5. * Copyright (c) 2012-2013, Intel Corporation
  6. * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
  7. */
  8. #include <linux/acpi.h>
  9. #include <linux/bitops.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/kernel.h>
  15. #include <linux/types.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/property.h>
  19. #include <linux/seq_file.h>
  20. #include <linux/pinctrl/pinctrl.h>
  21. #include <linux/pinctrl/pinmux.h>
  22. #include <linux/pinctrl/pinconf.h>
  23. #include <linux/pinctrl/pinconf-generic.h>
  24. #include "pinctrl-intel.h"
  25. /* memory mapped register offsets */
  26. #define BYT_CONF0_REG 0x000
  27. #define BYT_CONF1_REG 0x004
  28. #define BYT_VAL_REG 0x008
  29. #define BYT_DFT_REG 0x00c
  30. #define BYT_INT_STAT_REG 0x800
  31. #define BYT_DEBOUNCE_REG 0x9d0
  32. /* BYT_CONF0_REG register bits */
  33. #define BYT_IODEN BIT(31)
  34. #define BYT_DIRECT_IRQ_EN BIT(27)
  35. #define BYT_TRIG_MASK GENMASK(26, 24)
  36. #define BYT_TRIG_NEG BIT(26)
  37. #define BYT_TRIG_POS BIT(25)
  38. #define BYT_TRIG_LVL BIT(24)
  39. #define BYT_DEBOUNCE_EN BIT(20)
  40. #define BYT_GLITCH_FILTER_EN BIT(19)
  41. #define BYT_GLITCH_F_SLOW_CLK BIT(17)
  42. #define BYT_GLITCH_F_FAST_CLK BIT(16)
  43. #define BYT_PULL_STR_SHIFT 9
  44. #define BYT_PULL_STR_MASK GENMASK(10, 9)
  45. #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
  46. #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
  47. #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
  48. #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
  49. #define BYT_PULL_ASSIGN_SHIFT 7
  50. #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
  51. #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
  52. #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
  53. #define BYT_PIN_MUX GENMASK(2, 0)
  54. /* BYT_VAL_REG register bits */
  55. #define BYT_DIR_MASK GENMASK(2, 1)
  56. #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
  57. #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
  58. #define BYT_LEVEL BIT(0)
  59. #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
  60. #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
  61. /* BYT_DEBOUNCE_REG bits */
  62. #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0)
  63. #define BYT_DEBOUNCE_PULSE_375US 1
  64. #define BYT_DEBOUNCE_PULSE_750US 2
  65. #define BYT_DEBOUNCE_PULSE_1500US 3
  66. #define BYT_DEBOUNCE_PULSE_3MS 4
  67. #define BYT_DEBOUNCE_PULSE_6MS 5
  68. #define BYT_DEBOUNCE_PULSE_12MS 6
  69. #define BYT_DEBOUNCE_PULSE_24MS 7
  70. #define BYT_NGPIO_SCORE 102
  71. #define BYT_NGPIO_NCORE 28
  72. #define BYT_NGPIO_SUS 44
  73. #define BYT_SCORE_ACPI_UID "1"
  74. #define BYT_NCORE_ACPI_UID "2"
  75. #define BYT_SUS_ACPI_UID "3"
  76. /*
  77. * This is the function value most pins have for GPIO muxing. If the value
  78. * differs from the default one, it must be explicitly mentioned. Otherwise, the
  79. * pin control implementation will set the muxing value to default GPIO if it
  80. * does not find a match for the requested function.
  81. */
  82. #define BYT_DEFAULT_GPIO_MUX 0
  83. #define BYT_ALTER_GPIO_MUX 1
  84. struct intel_pad_context {
  85. u32 conf0;
  86. u32 val;
  87. };
  88. #define COMMUNITY(p, n, map) \
  89. { \
  90. .pin_base = (p), \
  91. .npins = (n), \
  92. .pad_map = (map),\
  93. }
  94. /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
  95. static const struct pinctrl_pin_desc byt_score_pins[] = {
  96. PINCTRL_PIN(0, "SATA_GP0"),
  97. PINCTRL_PIN(1, "SATA_GP1"),
  98. PINCTRL_PIN(2, "SATA_LED#"),
  99. PINCTRL_PIN(3, "PCIE_CLKREQ0"),
  100. PINCTRL_PIN(4, "PCIE_CLKREQ1"),
  101. PINCTRL_PIN(5, "PCIE_CLKREQ2"),
  102. PINCTRL_PIN(6, "PCIE_CLKREQ3"),
  103. PINCTRL_PIN(7, "SD3_WP"),
  104. PINCTRL_PIN(8, "HDA_RST"),
  105. PINCTRL_PIN(9, "HDA_SYNC"),
  106. PINCTRL_PIN(10, "HDA_CLK"),
  107. PINCTRL_PIN(11, "HDA_SDO"),
  108. PINCTRL_PIN(12, "HDA_SDI0"),
  109. PINCTRL_PIN(13, "HDA_SDI1"),
  110. PINCTRL_PIN(14, "GPIO_S0_SC14"),
  111. PINCTRL_PIN(15, "GPIO_S0_SC15"),
  112. PINCTRL_PIN(16, "MMC1_CLK"),
  113. PINCTRL_PIN(17, "MMC1_D0"),
  114. PINCTRL_PIN(18, "MMC1_D1"),
  115. PINCTRL_PIN(19, "MMC1_D2"),
  116. PINCTRL_PIN(20, "MMC1_D3"),
  117. PINCTRL_PIN(21, "MMC1_D4"),
  118. PINCTRL_PIN(22, "MMC1_D5"),
  119. PINCTRL_PIN(23, "MMC1_D6"),
  120. PINCTRL_PIN(24, "MMC1_D7"),
  121. PINCTRL_PIN(25, "MMC1_CMD"),
  122. PINCTRL_PIN(26, "MMC1_RST"),
  123. PINCTRL_PIN(27, "SD2_CLK"),
  124. PINCTRL_PIN(28, "SD2_D0"),
  125. PINCTRL_PIN(29, "SD2_D1"),
  126. PINCTRL_PIN(30, "SD2_D2"),
  127. PINCTRL_PIN(31, "SD2_D3_CD"),
  128. PINCTRL_PIN(32, "SD2_CMD"),
  129. PINCTRL_PIN(33, "SD3_CLK"),
  130. PINCTRL_PIN(34, "SD3_D0"),
  131. PINCTRL_PIN(35, "SD3_D1"),
  132. PINCTRL_PIN(36, "SD3_D2"),
  133. PINCTRL_PIN(37, "SD3_D3"),
  134. PINCTRL_PIN(38, "SD3_CD"),
  135. PINCTRL_PIN(39, "SD3_CMD"),
  136. PINCTRL_PIN(40, "SD3_1P8EN"),
  137. PINCTRL_PIN(41, "SD3_PWREN#"),
  138. PINCTRL_PIN(42, "ILB_LPC_AD0"),
  139. PINCTRL_PIN(43, "ILB_LPC_AD1"),
  140. PINCTRL_PIN(44, "ILB_LPC_AD2"),
  141. PINCTRL_PIN(45, "ILB_LPC_AD3"),
  142. PINCTRL_PIN(46, "ILB_LPC_FRAME"),
  143. PINCTRL_PIN(47, "ILB_LPC_CLK0"),
  144. PINCTRL_PIN(48, "ILB_LPC_CLK1"),
  145. PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
  146. PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
  147. PINCTRL_PIN(51, "PCU_SMB_DATA"),
  148. PINCTRL_PIN(52, "PCU_SMB_CLK"),
  149. PINCTRL_PIN(53, "PCU_SMB_ALERT"),
  150. PINCTRL_PIN(54, "ILB_8254_SPKR"),
  151. PINCTRL_PIN(55, "GPIO_S0_SC55"),
  152. PINCTRL_PIN(56, "GPIO_S0_SC56"),
  153. PINCTRL_PIN(57, "GPIO_S0_SC57"),
  154. PINCTRL_PIN(58, "GPIO_S0_SC58"),
  155. PINCTRL_PIN(59, "GPIO_S0_SC59"),
  156. PINCTRL_PIN(60, "GPIO_S0_SC60"),
  157. PINCTRL_PIN(61, "GPIO_S0_SC61"),
  158. PINCTRL_PIN(62, "LPE_I2S2_CLK"),
  159. PINCTRL_PIN(63, "LPE_I2S2_FRM"),
  160. PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
  161. PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
  162. PINCTRL_PIN(66, "SIO_SPI_CS"),
  163. PINCTRL_PIN(67, "SIO_SPI_MISO"),
  164. PINCTRL_PIN(68, "SIO_SPI_MOSI"),
  165. PINCTRL_PIN(69, "SIO_SPI_CLK"),
  166. PINCTRL_PIN(70, "SIO_UART1_RXD"),
  167. PINCTRL_PIN(71, "SIO_UART1_TXD"),
  168. PINCTRL_PIN(72, "SIO_UART1_RTS"),
  169. PINCTRL_PIN(73, "SIO_UART1_CTS"),
  170. PINCTRL_PIN(74, "SIO_UART2_RXD"),
  171. PINCTRL_PIN(75, "SIO_UART2_TXD"),
  172. PINCTRL_PIN(76, "SIO_UART2_RTS"),
  173. PINCTRL_PIN(77, "SIO_UART2_CTS"),
  174. PINCTRL_PIN(78, "SIO_I2C0_DATA"),
  175. PINCTRL_PIN(79, "SIO_I2C0_CLK"),
  176. PINCTRL_PIN(80, "SIO_I2C1_DATA"),
  177. PINCTRL_PIN(81, "SIO_I2C1_CLK"),
  178. PINCTRL_PIN(82, "SIO_I2C2_DATA"),
  179. PINCTRL_PIN(83, "SIO_I2C2_CLK"),
  180. PINCTRL_PIN(84, "SIO_I2C3_DATA"),
  181. PINCTRL_PIN(85, "SIO_I2C3_CLK"),
  182. PINCTRL_PIN(86, "SIO_I2C4_DATA"),
  183. PINCTRL_PIN(87, "SIO_I2C4_CLK"),
  184. PINCTRL_PIN(88, "SIO_I2C5_DATA"),
  185. PINCTRL_PIN(89, "SIO_I2C5_CLK"),
  186. PINCTRL_PIN(90, "SIO_I2C6_DATA"),
  187. PINCTRL_PIN(91, "SIO_I2C6_CLK"),
  188. PINCTRL_PIN(92, "GPIO_S0_SC92"),
  189. PINCTRL_PIN(93, "GPIO_S0_SC93"),
  190. PINCTRL_PIN(94, "SIO_PWM0"),
  191. PINCTRL_PIN(95, "SIO_PWM1"),
  192. PINCTRL_PIN(96, "PMC_PLT_CLK0"),
  193. PINCTRL_PIN(97, "PMC_PLT_CLK1"),
  194. PINCTRL_PIN(98, "PMC_PLT_CLK2"),
  195. PINCTRL_PIN(99, "PMC_PLT_CLK3"),
  196. PINCTRL_PIN(100, "PMC_PLT_CLK4"),
  197. PINCTRL_PIN(101, "PMC_PLT_CLK5"),
  198. };
  199. static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
  200. 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
  201. 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
  202. 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
  203. 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
  204. 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
  205. 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
  206. 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
  207. 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
  208. 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
  209. 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
  210. 97, 100,
  211. };
  212. /* SCORE groups */
  213. static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
  214. static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
  215. static const unsigned int byt_score_pwm0_pins[] = { 94 };
  216. static const unsigned int byt_score_pwm1_pins[] = { 95 };
  217. static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
  218. static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
  219. static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
  220. static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
  221. static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
  222. static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
  223. static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
  224. static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
  225. static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
  226. static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
  227. static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
  228. static const unsigned int byt_score_sdcard_pins[] = {
  229. 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
  230. };
  231. static const unsigned int byt_score_sdcard_mux_values[] = {
  232. 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  233. };
  234. static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
  235. static const unsigned int byt_score_emmc_pins[] = {
  236. 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
  237. };
  238. static const unsigned int byt_score_ilb_lpc_pins[] = {
  239. 42, 43, 44, 45, 46, 47, 48, 49, 50,
  240. };
  241. static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
  242. static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
  243. static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
  244. static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
  245. static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
  246. static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
  247. static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
  248. static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
  249. static const struct intel_pingroup byt_score_groups[] = {
  250. PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
  251. PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
  252. PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
  253. PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
  254. PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
  255. PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
  256. PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
  257. PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
  258. PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
  259. PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
  260. PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
  261. PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
  262. PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
  263. PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
  264. PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
  265. PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
  266. PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
  267. PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
  268. PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
  269. PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
  270. PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
  271. PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
  272. PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
  273. PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
  274. PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
  275. PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
  276. PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
  277. };
  278. static const char * const byt_score_uart_groups[] = {
  279. "uart1_grp", "uart2_grp",
  280. };
  281. static const char * const byt_score_pwm_groups[] = {
  282. "pwm0_grp", "pwm1_grp",
  283. };
  284. static const char * const byt_score_ssp_groups[] = {
  285. "ssp0_grp", "ssp1_grp", "ssp2_grp",
  286. };
  287. static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
  288. static const char * const byt_score_i2c_groups[] = {
  289. "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
  290. "i2c6_grp",
  291. };
  292. static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
  293. static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
  294. static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
  295. static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
  296. static const char * const byt_score_sata_groups[] = { "sata_grp" };
  297. static const char * const byt_score_plt_clk_groups[] = {
  298. "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
  299. "plt_clk4_grp", "plt_clk5_grp",
  300. };
  301. static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
  302. static const char * const byt_score_gpio_groups[] = {
  303. "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
  304. "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
  305. "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
  306. "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
  307. "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
  308. "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
  309. };
  310. static const struct intel_function byt_score_functions[] = {
  311. FUNCTION("uart", byt_score_uart_groups),
  312. FUNCTION("pwm", byt_score_pwm_groups),
  313. FUNCTION("ssp", byt_score_ssp_groups),
  314. FUNCTION("spi", byt_score_spi_groups),
  315. FUNCTION("i2c", byt_score_i2c_groups),
  316. FUNCTION("sdcard", byt_score_sdcard_groups),
  317. FUNCTION("sdio", byt_score_sdio_groups),
  318. FUNCTION("emmc", byt_score_emmc_groups),
  319. FUNCTION("lpc", byt_score_lpc_groups),
  320. FUNCTION("sata", byt_score_sata_groups),
  321. FUNCTION("plt_clk", byt_score_plt_clk_groups),
  322. FUNCTION("smbus", byt_score_smbus_groups),
  323. FUNCTION("gpio", byt_score_gpio_groups),
  324. };
  325. static const struct intel_community byt_score_communities[] = {
  326. COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
  327. };
  328. static const struct intel_pinctrl_soc_data byt_score_soc_data = {
  329. .uid = BYT_SCORE_ACPI_UID,
  330. .pins = byt_score_pins,
  331. .npins = ARRAY_SIZE(byt_score_pins),
  332. .groups = byt_score_groups,
  333. .ngroups = ARRAY_SIZE(byt_score_groups),
  334. .functions = byt_score_functions,
  335. .nfunctions = ARRAY_SIZE(byt_score_functions),
  336. .communities = byt_score_communities,
  337. .ncommunities = ARRAY_SIZE(byt_score_communities),
  338. };
  339. /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
  340. static const struct pinctrl_pin_desc byt_sus_pins[] = {
  341. PINCTRL_PIN(0, "GPIO_S50"),
  342. PINCTRL_PIN(1, "GPIO_S51"),
  343. PINCTRL_PIN(2, "GPIO_S52"),
  344. PINCTRL_PIN(3, "GPIO_S53"),
  345. PINCTRL_PIN(4, "GPIO_S54"),
  346. PINCTRL_PIN(5, "GPIO_S55"),
  347. PINCTRL_PIN(6, "GPIO_S56"),
  348. PINCTRL_PIN(7, "GPIO_S57"),
  349. PINCTRL_PIN(8, "GPIO_S58"),
  350. PINCTRL_PIN(9, "GPIO_S59"),
  351. PINCTRL_PIN(10, "GPIO_S510"),
  352. PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
  353. PINCTRL_PIN(12, "PMC_SUSCLK0"),
  354. PINCTRL_PIN(13, "GPIO_S513"),
  355. PINCTRL_PIN(14, "USB_ULPI_RST"),
  356. PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
  357. PINCTRL_PIN(16, "PMC_PWRBTN"),
  358. PINCTRL_PIN(17, "GPIO_S517"),
  359. PINCTRL_PIN(18, "PMC_SUS_STAT"),
  360. PINCTRL_PIN(19, "USB_OC0"),
  361. PINCTRL_PIN(20, "USB_OC1"),
  362. PINCTRL_PIN(21, "PCU_SPI_CS1"),
  363. PINCTRL_PIN(22, "GPIO_S522"),
  364. PINCTRL_PIN(23, "GPIO_S523"),
  365. PINCTRL_PIN(24, "GPIO_S524"),
  366. PINCTRL_PIN(25, "GPIO_S525"),
  367. PINCTRL_PIN(26, "GPIO_S526"),
  368. PINCTRL_PIN(27, "GPIO_S527"),
  369. PINCTRL_PIN(28, "GPIO_S528"),
  370. PINCTRL_PIN(29, "GPIO_S529"),
  371. PINCTRL_PIN(30, "GPIO_S530"),
  372. PINCTRL_PIN(31, "USB_ULPI_CLK"),
  373. PINCTRL_PIN(32, "USB_ULPI_DATA0"),
  374. PINCTRL_PIN(33, "USB_ULPI_DATA1"),
  375. PINCTRL_PIN(34, "USB_ULPI_DATA2"),
  376. PINCTRL_PIN(35, "USB_ULPI_DATA3"),
  377. PINCTRL_PIN(36, "USB_ULPI_DATA4"),
  378. PINCTRL_PIN(37, "USB_ULPI_DATA5"),
  379. PINCTRL_PIN(38, "USB_ULPI_DATA6"),
  380. PINCTRL_PIN(39, "USB_ULPI_DATA7"),
  381. PINCTRL_PIN(40, "USB_ULPI_DIR"),
  382. PINCTRL_PIN(41, "USB_ULPI_NXT"),
  383. PINCTRL_PIN(42, "USB_ULPI_STP"),
  384. PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
  385. };
  386. static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
  387. 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
  388. 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
  389. 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
  390. 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
  391. 52, 53, 59, 40,
  392. };
  393. static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
  394. static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
  395. static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
  396. static const unsigned int byt_sus_usb_ulpi_pins[] = {
  397. 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
  398. };
  399. static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
  400. 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  401. };
  402. static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
  403. 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  404. };
  405. static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
  406. static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
  407. static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
  408. static const struct intel_pingroup byt_sus_groups[] = {
  409. PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
  410. PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
  411. PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
  412. PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
  413. PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
  414. PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
  415. };
  416. static const char * const byt_sus_usb_groups[] = {
  417. "usb_oc_grp", "usb_ulpi_grp",
  418. };
  419. static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
  420. static const char * const byt_sus_gpio_groups[] = {
  421. "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
  422. };
  423. static const struct intel_function byt_sus_functions[] = {
  424. FUNCTION("usb", byt_sus_usb_groups),
  425. FUNCTION("spi", byt_sus_spi_groups),
  426. FUNCTION("gpio", byt_sus_gpio_groups),
  427. };
  428. static const struct intel_community byt_sus_communities[] = {
  429. COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
  430. };
  431. static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
  432. .uid = BYT_SUS_ACPI_UID,
  433. .pins = byt_sus_pins,
  434. .npins = ARRAY_SIZE(byt_sus_pins),
  435. .groups = byt_sus_groups,
  436. .ngroups = ARRAY_SIZE(byt_sus_groups),
  437. .functions = byt_sus_functions,
  438. .nfunctions = ARRAY_SIZE(byt_sus_functions),
  439. .communities = byt_sus_communities,
  440. .ncommunities = ARRAY_SIZE(byt_sus_communities),
  441. };
  442. static const struct pinctrl_pin_desc byt_ncore_pins[] = {
  443. PINCTRL_PIN(0, "HV_DDI0_HPD"),
  444. PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
  445. PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
  446. PINCTRL_PIN(3, "PANEL0_VDDEN"),
  447. PINCTRL_PIN(4, "PANEL0_BKLTEN"),
  448. PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
  449. PINCTRL_PIN(6, "HV_DDI1_HPD"),
  450. PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
  451. PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
  452. PINCTRL_PIN(9, "PANEL1_VDDEN"),
  453. PINCTRL_PIN(10, "PANEL1_BKLTEN"),
  454. PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
  455. PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
  456. PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
  457. PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
  458. PINCTRL_PIN(15, "GP_CAMERASB00"),
  459. PINCTRL_PIN(16, "GP_CAMERASB01"),
  460. PINCTRL_PIN(17, "GP_CAMERASB02"),
  461. PINCTRL_PIN(18, "GP_CAMERASB03"),
  462. PINCTRL_PIN(19, "GP_CAMERASB04"),
  463. PINCTRL_PIN(20, "GP_CAMERASB05"),
  464. PINCTRL_PIN(21, "GP_CAMERASB06"),
  465. PINCTRL_PIN(22, "GP_CAMERASB07"),
  466. PINCTRL_PIN(23, "GP_CAMERASB08"),
  467. PINCTRL_PIN(24, "GP_CAMERASB09"),
  468. PINCTRL_PIN(25, "GP_CAMERASB10"),
  469. PINCTRL_PIN(26, "GP_CAMERASB11"),
  470. PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
  471. };
  472. static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
  473. 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
  474. 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
  475. 3, 6, 10, 13, 2, 5, 9, 7,
  476. };
  477. static const struct intel_community byt_ncore_communities[] = {
  478. COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
  479. };
  480. static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
  481. .uid = BYT_NCORE_ACPI_UID,
  482. .pins = byt_ncore_pins,
  483. .npins = ARRAY_SIZE(byt_ncore_pins),
  484. .communities = byt_ncore_communities,
  485. .ncommunities = ARRAY_SIZE(byt_ncore_communities),
  486. };
  487. static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
  488. &byt_score_soc_data,
  489. &byt_sus_soc_data,
  490. &byt_ncore_soc_data,
  491. NULL
  492. };
  493. static DEFINE_RAW_SPINLOCK(byt_lock);
  494. static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
  495. unsigned int pin)
  496. {
  497. struct intel_community *comm;
  498. int i;
  499. for (i = 0; i < vg->ncommunities; i++) {
  500. comm = vg->communities + i;
  501. if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
  502. return comm;
  503. }
  504. return NULL;
  505. }
  506. static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
  507. int reg)
  508. {
  509. struct intel_community *comm = byt_get_community(vg, offset);
  510. u32 reg_offset;
  511. if (!comm)
  512. return NULL;
  513. offset -= comm->pin_base;
  514. switch (reg) {
  515. case BYT_INT_STAT_REG:
  516. reg_offset = (offset / 32) * 4;
  517. break;
  518. case BYT_DEBOUNCE_REG:
  519. reg_offset = 0;
  520. break;
  521. default:
  522. reg_offset = comm->pad_map[offset] * 16;
  523. break;
  524. }
  525. return comm->pad_regs + reg_offset + reg;
  526. }
  527. static int byt_get_groups_count(struct pinctrl_dev *pctldev)
  528. {
  529. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
  530. return vg->soc->ngroups;
  531. }
  532. static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
  533. unsigned int selector)
  534. {
  535. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
  536. return vg->soc->groups[selector].name;
  537. }
  538. static int byt_get_group_pins(struct pinctrl_dev *pctldev,
  539. unsigned int selector,
  540. const unsigned int **pins,
  541. unsigned int *num_pins)
  542. {
  543. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
  544. *pins = vg->soc->groups[selector].pins;
  545. *num_pins = vg->soc->groups[selector].npins;
  546. return 0;
  547. }
  548. static const struct pinctrl_ops byt_pinctrl_ops = {
  549. .get_groups_count = byt_get_groups_count,
  550. .get_group_name = byt_get_group_name,
  551. .get_group_pins = byt_get_group_pins,
  552. };
  553. static int byt_get_functions_count(struct pinctrl_dev *pctldev)
  554. {
  555. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
  556. return vg->soc->nfunctions;
  557. }
  558. static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
  559. unsigned int selector)
  560. {
  561. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
  562. return vg->soc->functions[selector].name;
  563. }
  564. static int byt_get_function_groups(struct pinctrl_dev *pctldev,
  565. unsigned int selector,
  566. const char * const **groups,
  567. unsigned int *num_groups)
  568. {
  569. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
  570. *groups = vg->soc->functions[selector].groups;
  571. *num_groups = vg->soc->functions[selector].ngroups;
  572. return 0;
  573. }
  574. static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
  575. const struct intel_pingroup group,
  576. unsigned int func)
  577. {
  578. unsigned long flags;
  579. int i;
  580. raw_spin_lock_irqsave(&byt_lock, flags);
  581. for (i = 0; i < group.npins; i++) {
  582. void __iomem *padcfg0;
  583. u32 value;
  584. padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
  585. if (!padcfg0) {
  586. dev_warn(vg->dev,
  587. "Group %s, pin %i not muxed (no padcfg0)\n",
  588. group.name, i);
  589. continue;
  590. }
  591. value = readl(padcfg0);
  592. value &= ~BYT_PIN_MUX;
  593. value |= func;
  594. writel(value, padcfg0);
  595. }
  596. raw_spin_unlock_irqrestore(&byt_lock, flags);
  597. }
  598. static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
  599. const struct intel_pingroup group,
  600. const unsigned int *func)
  601. {
  602. unsigned long flags;
  603. int i;
  604. raw_spin_lock_irqsave(&byt_lock, flags);
  605. for (i = 0; i < group.npins; i++) {
  606. void __iomem *padcfg0;
  607. u32 value;
  608. padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
  609. if (!padcfg0) {
  610. dev_warn(vg->dev,
  611. "Group %s, pin %i not muxed (no padcfg0)\n",
  612. group.name, i);
  613. continue;
  614. }
  615. value = readl(padcfg0);
  616. value &= ~BYT_PIN_MUX;
  617. value |= func[i];
  618. writel(value, padcfg0);
  619. }
  620. raw_spin_unlock_irqrestore(&byt_lock, flags);
  621. }
  622. static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
  623. unsigned int group_selector)
  624. {
  625. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
  626. const struct intel_function func = vg->soc->functions[func_selector];
  627. const struct intel_pingroup group = vg->soc->groups[group_selector];
  628. if (group.modes)
  629. byt_set_group_mixed_mux(vg, group, group.modes);
  630. else if (!strcmp(func.name, "gpio"))
  631. byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
  632. else
  633. byt_set_group_simple_mux(vg, group, group.mode);
  634. return 0;
  635. }
  636. static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
  637. {
  638. /* SCORE pin 92-93 */
  639. if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
  640. offset >= 92 && offset <= 93)
  641. return BYT_ALTER_GPIO_MUX;
  642. /* SUS pin 11-21 */
  643. if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
  644. offset >= 11 && offset <= 21)
  645. return BYT_ALTER_GPIO_MUX;
  646. return BYT_DEFAULT_GPIO_MUX;
  647. }
  648. static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
  649. {
  650. void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
  651. unsigned long flags;
  652. u32 value;
  653. raw_spin_lock_irqsave(&byt_lock, flags);
  654. value = readl(reg);
  655. /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
  656. if (value & BYT_DIRECT_IRQ_EN)
  657. /* nothing to do */ ;
  658. else
  659. value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
  660. writel(value, reg);
  661. raw_spin_unlock_irqrestore(&byt_lock, flags);
  662. }
  663. static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
  664. struct pinctrl_gpio_range *range,
  665. unsigned int offset)
  666. {
  667. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
  668. void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
  669. u32 value, gpio_mux;
  670. unsigned long flags;
  671. raw_spin_lock_irqsave(&byt_lock, flags);
  672. /*
  673. * In most cases, func pin mux 000 means GPIO function.
  674. * But, some pins may have func pin mux 001 represents
  675. * GPIO function.
  676. *
  677. * Because there are devices out there where some pins were not
  678. * configured correctly we allow changing the mux value from
  679. * request (but print out warning about that).
  680. */
  681. value = readl(reg) & BYT_PIN_MUX;
  682. gpio_mux = byt_get_gpio_mux(vg, offset);
  683. if (gpio_mux != value) {
  684. value = readl(reg) & ~BYT_PIN_MUX;
  685. value |= gpio_mux;
  686. writel(value, reg);
  687. dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
  688. }
  689. raw_spin_unlock_irqrestore(&byt_lock, flags);
  690. pm_runtime_get(vg->dev);
  691. return 0;
  692. }
  693. static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
  694. struct pinctrl_gpio_range *range,
  695. unsigned int offset)
  696. {
  697. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
  698. byt_gpio_clear_triggering(vg, offset);
  699. pm_runtime_put(vg->dev);
  700. }
  701. static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
  702. unsigned int offset)
  703. {
  704. void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
  705. /*
  706. * Before making any direction modifications, do a check if gpio is set
  707. * for direct IRQ. On Bay Trail, setting GPIO to output does not make
  708. * sense, so let's at least inform the caller before they shoot
  709. * themselves in the foot.
  710. */
  711. if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
  712. dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
  713. }
  714. static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
  715. struct pinctrl_gpio_range *range,
  716. unsigned int offset,
  717. bool input)
  718. {
  719. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
  720. void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  721. unsigned long flags;
  722. u32 value;
  723. raw_spin_lock_irqsave(&byt_lock, flags);
  724. value = readl(val_reg);
  725. value &= ~BYT_DIR_MASK;
  726. if (input)
  727. value |= BYT_OUTPUT_EN;
  728. else
  729. byt_gpio_direct_irq_check(vg, offset);
  730. writel(value, val_reg);
  731. raw_spin_unlock_irqrestore(&byt_lock, flags);
  732. return 0;
  733. }
  734. static const struct pinmux_ops byt_pinmux_ops = {
  735. .get_functions_count = byt_get_functions_count,
  736. .get_function_name = byt_get_function_name,
  737. .get_function_groups = byt_get_function_groups,
  738. .set_mux = byt_set_mux,
  739. .gpio_request_enable = byt_gpio_request_enable,
  740. .gpio_disable_free = byt_gpio_disable_free,
  741. .gpio_set_direction = byt_gpio_set_direction,
  742. };
  743. static void byt_get_pull_strength(u32 reg, u16 *strength)
  744. {
  745. switch (reg & BYT_PULL_STR_MASK) {
  746. case BYT_PULL_STR_2K:
  747. *strength = 2000;
  748. break;
  749. case BYT_PULL_STR_10K:
  750. *strength = 10000;
  751. break;
  752. case BYT_PULL_STR_20K:
  753. *strength = 20000;
  754. break;
  755. case BYT_PULL_STR_40K:
  756. *strength = 40000;
  757. break;
  758. }
  759. }
  760. static int byt_set_pull_strength(u32 *reg, u16 strength)
  761. {
  762. *reg &= ~BYT_PULL_STR_MASK;
  763. switch (strength) {
  764. case 2000:
  765. *reg |= BYT_PULL_STR_2K;
  766. break;
  767. case 10000:
  768. *reg |= BYT_PULL_STR_10K;
  769. break;
  770. case 20000:
  771. *reg |= BYT_PULL_STR_20K;
  772. break;
  773. case 40000:
  774. *reg |= BYT_PULL_STR_40K;
  775. break;
  776. default:
  777. return -EINVAL;
  778. }
  779. return 0;
  780. }
  781. static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
  782. unsigned long *config)
  783. {
  784. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
  785. enum pin_config_param param = pinconf_to_config_param(*config);
  786. void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
  787. void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  788. void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
  789. unsigned long flags;
  790. u32 conf, pull, val, debounce;
  791. u16 arg = 0;
  792. raw_spin_lock_irqsave(&byt_lock, flags);
  793. conf = readl(conf_reg);
  794. pull = conf & BYT_PULL_ASSIGN_MASK;
  795. val = readl(val_reg);
  796. raw_spin_unlock_irqrestore(&byt_lock, flags);
  797. switch (param) {
  798. case PIN_CONFIG_BIAS_DISABLE:
  799. if (pull)
  800. return -EINVAL;
  801. break;
  802. case PIN_CONFIG_BIAS_PULL_DOWN:
  803. /* Pull assignment is only applicable in input mode */
  804. if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
  805. return -EINVAL;
  806. byt_get_pull_strength(conf, &arg);
  807. break;
  808. case PIN_CONFIG_BIAS_PULL_UP:
  809. /* Pull assignment is only applicable in input mode */
  810. if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
  811. return -EINVAL;
  812. byt_get_pull_strength(conf, &arg);
  813. break;
  814. case PIN_CONFIG_INPUT_DEBOUNCE:
  815. if (!(conf & BYT_DEBOUNCE_EN))
  816. return -EINVAL;
  817. raw_spin_lock_irqsave(&byt_lock, flags);
  818. debounce = readl(db_reg);
  819. raw_spin_unlock_irqrestore(&byt_lock, flags);
  820. switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
  821. case BYT_DEBOUNCE_PULSE_375US:
  822. arg = 375;
  823. break;
  824. case BYT_DEBOUNCE_PULSE_750US:
  825. arg = 750;
  826. break;
  827. case BYT_DEBOUNCE_PULSE_1500US:
  828. arg = 1500;
  829. break;
  830. case BYT_DEBOUNCE_PULSE_3MS:
  831. arg = 3000;
  832. break;
  833. case BYT_DEBOUNCE_PULSE_6MS:
  834. arg = 6000;
  835. break;
  836. case BYT_DEBOUNCE_PULSE_12MS:
  837. arg = 12000;
  838. break;
  839. case BYT_DEBOUNCE_PULSE_24MS:
  840. arg = 24000;
  841. break;
  842. default:
  843. return -EINVAL;
  844. }
  845. break;
  846. default:
  847. return -ENOTSUPP;
  848. }
  849. *config = pinconf_to_config_packed(param, arg);
  850. return 0;
  851. }
  852. static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
  853. unsigned int offset,
  854. unsigned long *configs,
  855. unsigned int num_configs)
  856. {
  857. struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
  858. unsigned int param, arg;
  859. void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
  860. void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  861. void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
  862. unsigned long flags;
  863. u32 conf, val, debounce;
  864. int i, ret = 0;
  865. raw_spin_lock_irqsave(&byt_lock, flags);
  866. conf = readl(conf_reg);
  867. val = readl(val_reg);
  868. for (i = 0; i < num_configs; i++) {
  869. param = pinconf_to_config_param(configs[i]);
  870. arg = pinconf_to_config_argument(configs[i]);
  871. switch (param) {
  872. case PIN_CONFIG_BIAS_DISABLE:
  873. conf &= ~BYT_PULL_ASSIGN_MASK;
  874. break;
  875. case PIN_CONFIG_BIAS_PULL_DOWN:
  876. /* Set default strength value in case none is given */
  877. if (arg == 1)
  878. arg = 2000;
  879. /*
  880. * Pull assignment is only applicable in input mode. If
  881. * chip is not in input mode, set it and warn about it.
  882. */
  883. if (val & BYT_INPUT_EN) {
  884. val &= ~BYT_INPUT_EN;
  885. writel(val, val_reg);
  886. dev_warn(vg->dev,
  887. "pin %u forcibly set to input mode\n",
  888. offset);
  889. }
  890. conf &= ~BYT_PULL_ASSIGN_MASK;
  891. conf |= BYT_PULL_ASSIGN_DOWN;
  892. ret = byt_set_pull_strength(&conf, arg);
  893. break;
  894. case PIN_CONFIG_BIAS_PULL_UP:
  895. /* Set default strength value in case none is given */
  896. if (arg == 1)
  897. arg = 2000;
  898. /*
  899. * Pull assignment is only applicable in input mode. If
  900. * chip is not in input mode, set it and warn about it.
  901. */
  902. if (val & BYT_INPUT_EN) {
  903. val &= ~BYT_INPUT_EN;
  904. writel(val, val_reg);
  905. dev_warn(vg->dev,
  906. "pin %u forcibly set to input mode\n",
  907. offset);
  908. }
  909. conf &= ~BYT_PULL_ASSIGN_MASK;
  910. conf |= BYT_PULL_ASSIGN_UP;
  911. ret = byt_set_pull_strength(&conf, arg);
  912. break;
  913. case PIN_CONFIG_INPUT_DEBOUNCE:
  914. debounce = readl(db_reg);
  915. if (arg)
  916. conf |= BYT_DEBOUNCE_EN;
  917. else
  918. conf &= ~BYT_DEBOUNCE_EN;
  919. switch (arg) {
  920. case 375:
  921. debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
  922. debounce |= BYT_DEBOUNCE_PULSE_375US;
  923. break;
  924. case 750:
  925. debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
  926. debounce |= BYT_DEBOUNCE_PULSE_750US;
  927. break;
  928. case 1500:
  929. debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
  930. debounce |= BYT_DEBOUNCE_PULSE_1500US;
  931. break;
  932. case 3000:
  933. debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
  934. debounce |= BYT_DEBOUNCE_PULSE_3MS;
  935. break;
  936. case 6000:
  937. debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
  938. debounce |= BYT_DEBOUNCE_PULSE_6MS;
  939. break;
  940. case 12000:
  941. debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
  942. debounce |= BYT_DEBOUNCE_PULSE_12MS;
  943. break;
  944. case 24000:
  945. debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
  946. debounce |= BYT_DEBOUNCE_PULSE_24MS;
  947. break;
  948. default:
  949. if (arg)
  950. ret = -EINVAL;
  951. break;
  952. }
  953. if (!ret)
  954. writel(debounce, db_reg);
  955. break;
  956. default:
  957. ret = -ENOTSUPP;
  958. }
  959. if (ret)
  960. break;
  961. }
  962. if (!ret)
  963. writel(conf, conf_reg);
  964. raw_spin_unlock_irqrestore(&byt_lock, flags);
  965. return ret;
  966. }
  967. static const struct pinconf_ops byt_pinconf_ops = {
  968. .is_generic = true,
  969. .pin_config_get = byt_pin_config_get,
  970. .pin_config_set = byt_pin_config_set,
  971. };
  972. static const struct pinctrl_desc byt_pinctrl_desc = {
  973. .pctlops = &byt_pinctrl_ops,
  974. .pmxops = &byt_pinmux_ops,
  975. .confops = &byt_pinconf_ops,
  976. .owner = THIS_MODULE,
  977. };
  978. static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
  979. {
  980. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  981. void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  982. unsigned long flags;
  983. u32 val;
  984. raw_spin_lock_irqsave(&byt_lock, flags);
  985. val = readl(reg);
  986. raw_spin_unlock_irqrestore(&byt_lock, flags);
  987. return !!(val & BYT_LEVEL);
  988. }
  989. static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
  990. {
  991. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  992. void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  993. unsigned long flags;
  994. u32 old_val;
  995. if (!reg)
  996. return;
  997. raw_spin_lock_irqsave(&byt_lock, flags);
  998. old_val = readl(reg);
  999. if (value)
  1000. writel(old_val | BYT_LEVEL, reg);
  1001. else
  1002. writel(old_val & ~BYT_LEVEL, reg);
  1003. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1004. }
  1005. static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
  1006. {
  1007. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  1008. void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  1009. unsigned long flags;
  1010. u32 value;
  1011. if (!reg)
  1012. return -EINVAL;
  1013. raw_spin_lock_irqsave(&byt_lock, flags);
  1014. value = readl(reg);
  1015. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1016. if (!(value & BYT_OUTPUT_EN))
  1017. return GPIO_LINE_DIRECTION_OUT;
  1018. if (!(value & BYT_INPUT_EN))
  1019. return GPIO_LINE_DIRECTION_IN;
  1020. return -EINVAL;
  1021. }
  1022. static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
  1023. {
  1024. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  1025. void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  1026. unsigned long flags;
  1027. u32 reg;
  1028. raw_spin_lock_irqsave(&byt_lock, flags);
  1029. reg = readl(val_reg);
  1030. reg &= ~BYT_DIR_MASK;
  1031. reg |= BYT_OUTPUT_EN;
  1032. writel(reg, val_reg);
  1033. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1034. return 0;
  1035. }
  1036. /*
  1037. * Note despite the temptation this MUST NOT be converted into a call to
  1038. * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
  1039. * MUST be done as a single BYT_VAL_REG register write.
  1040. * See the commit message of the commit adding this comment for details.
  1041. */
  1042. static int byt_gpio_direction_output(struct gpio_chip *chip,
  1043. unsigned int offset, int value)
  1044. {
  1045. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  1046. void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
  1047. unsigned long flags;
  1048. u32 reg;
  1049. raw_spin_lock_irqsave(&byt_lock, flags);
  1050. byt_gpio_direct_irq_check(vg, offset);
  1051. reg = readl(val_reg);
  1052. reg &= ~BYT_DIR_MASK;
  1053. if (value)
  1054. reg |= BYT_LEVEL;
  1055. else
  1056. reg &= ~BYT_LEVEL;
  1057. writel(reg, val_reg);
  1058. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1059. return 0;
  1060. }
  1061. static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  1062. {
  1063. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  1064. int i;
  1065. u32 conf0, val;
  1066. for (i = 0; i < vg->soc->npins; i++) {
  1067. const struct intel_community *comm;
  1068. const char *pull_str = NULL;
  1069. const char *pull = NULL;
  1070. void __iomem *reg;
  1071. unsigned long flags;
  1072. const char *label;
  1073. unsigned int pin;
  1074. raw_spin_lock_irqsave(&byt_lock, flags);
  1075. pin = vg->soc->pins[i].number;
  1076. reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
  1077. if (!reg) {
  1078. seq_printf(s,
  1079. "Could not retrieve pin %i conf0 reg\n",
  1080. pin);
  1081. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1082. continue;
  1083. }
  1084. conf0 = readl(reg);
  1085. reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
  1086. if (!reg) {
  1087. seq_printf(s,
  1088. "Could not retrieve pin %i val reg\n", pin);
  1089. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1090. continue;
  1091. }
  1092. val = readl(reg);
  1093. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1094. comm = byt_get_community(vg, pin);
  1095. if (!comm) {
  1096. seq_printf(s,
  1097. "Could not get community for pin %i\n", pin);
  1098. continue;
  1099. }
  1100. label = gpiochip_is_requested(chip, i);
  1101. if (!label)
  1102. label = "Unrequested";
  1103. switch (conf0 & BYT_PULL_ASSIGN_MASK) {
  1104. case BYT_PULL_ASSIGN_UP:
  1105. pull = "up";
  1106. break;
  1107. case BYT_PULL_ASSIGN_DOWN:
  1108. pull = "down";
  1109. break;
  1110. }
  1111. switch (conf0 & BYT_PULL_STR_MASK) {
  1112. case BYT_PULL_STR_2K:
  1113. pull_str = "2k";
  1114. break;
  1115. case BYT_PULL_STR_10K:
  1116. pull_str = "10k";
  1117. break;
  1118. case BYT_PULL_STR_20K:
  1119. pull_str = "20k";
  1120. break;
  1121. case BYT_PULL_STR_40K:
  1122. pull_str = "40k";
  1123. break;
  1124. }
  1125. seq_printf(s,
  1126. " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
  1127. pin,
  1128. label,
  1129. val & BYT_INPUT_EN ? " " : "in",
  1130. val & BYT_OUTPUT_EN ? " " : "out",
  1131. val & BYT_LEVEL ? "hi" : "lo",
  1132. comm->pad_map[i], comm->pad_map[i] * 16,
  1133. conf0 & 0x7,
  1134. conf0 & BYT_TRIG_NEG ? " fall" : " ",
  1135. conf0 & BYT_TRIG_POS ? " rise" : " ",
  1136. conf0 & BYT_TRIG_LVL ? " level" : " ");
  1137. if (pull && pull_str)
  1138. seq_printf(s, " %-4s %-3s", pull, pull_str);
  1139. else
  1140. seq_puts(s, " ");
  1141. if (conf0 & BYT_IODEN)
  1142. seq_puts(s, " open-drain");
  1143. seq_puts(s, "\n");
  1144. }
  1145. }
  1146. static const struct gpio_chip byt_gpio_chip = {
  1147. .owner = THIS_MODULE,
  1148. .request = gpiochip_generic_request,
  1149. .free = gpiochip_generic_free,
  1150. .get_direction = byt_gpio_get_direction,
  1151. .direction_input = byt_gpio_direction_input,
  1152. .direction_output = byt_gpio_direction_output,
  1153. .get = byt_gpio_get,
  1154. .set = byt_gpio_set,
  1155. .set_config = gpiochip_generic_config,
  1156. .dbg_show = byt_gpio_dbg_show,
  1157. };
  1158. static void byt_irq_ack(struct irq_data *d)
  1159. {
  1160. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1161. struct intel_pinctrl *vg = gpiochip_get_data(gc);
  1162. unsigned int offset = irqd_to_hwirq(d);
  1163. void __iomem *reg;
  1164. reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
  1165. if (!reg)
  1166. return;
  1167. raw_spin_lock(&byt_lock);
  1168. writel(BIT(offset % 32), reg);
  1169. raw_spin_unlock(&byt_lock);
  1170. }
  1171. static void byt_irq_mask(struct irq_data *d)
  1172. {
  1173. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1174. struct intel_pinctrl *vg = gpiochip_get_data(gc);
  1175. byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
  1176. }
  1177. static void byt_irq_unmask(struct irq_data *d)
  1178. {
  1179. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  1180. struct intel_pinctrl *vg = gpiochip_get_data(gc);
  1181. unsigned int offset = irqd_to_hwirq(d);
  1182. unsigned long flags;
  1183. void __iomem *reg;
  1184. u32 value;
  1185. reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
  1186. if (!reg)
  1187. return;
  1188. raw_spin_lock_irqsave(&byt_lock, flags);
  1189. value = readl(reg);
  1190. switch (irqd_get_trigger_type(d)) {
  1191. case IRQ_TYPE_LEVEL_HIGH:
  1192. value |= BYT_TRIG_LVL;
  1193. fallthrough;
  1194. case IRQ_TYPE_EDGE_RISING:
  1195. value |= BYT_TRIG_POS;
  1196. break;
  1197. case IRQ_TYPE_LEVEL_LOW:
  1198. value |= BYT_TRIG_LVL;
  1199. fallthrough;
  1200. case IRQ_TYPE_EDGE_FALLING:
  1201. value |= BYT_TRIG_NEG;
  1202. break;
  1203. case IRQ_TYPE_EDGE_BOTH:
  1204. value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
  1205. break;
  1206. }
  1207. writel(value, reg);
  1208. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1209. }
  1210. static int byt_irq_type(struct irq_data *d, unsigned int type)
  1211. {
  1212. struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
  1213. u32 offset = irqd_to_hwirq(d);
  1214. u32 value;
  1215. unsigned long flags;
  1216. void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
  1217. if (!reg || offset >= vg->chip.ngpio)
  1218. return -EINVAL;
  1219. raw_spin_lock_irqsave(&byt_lock, flags);
  1220. value = readl(reg);
  1221. WARN(value & BYT_DIRECT_IRQ_EN,
  1222. "Bad pad config for io mode, force direct_irq_en bit clearing");
  1223. /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
  1224. * are used to indicate high and low level triggering
  1225. */
  1226. value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
  1227. BYT_TRIG_LVL);
  1228. /* Enable glitch filtering */
  1229. value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
  1230. BYT_GLITCH_F_FAST_CLK;
  1231. writel(value, reg);
  1232. if (type & IRQ_TYPE_EDGE_BOTH)
  1233. irq_set_handler_locked(d, handle_edge_irq);
  1234. else if (type & IRQ_TYPE_LEVEL_MASK)
  1235. irq_set_handler_locked(d, handle_level_irq);
  1236. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1237. return 0;
  1238. }
  1239. static void byt_gpio_irq_handler(struct irq_desc *desc)
  1240. {
  1241. struct irq_data *data = irq_desc_get_irq_data(desc);
  1242. struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
  1243. struct irq_chip *chip = irq_data_get_irq_chip(data);
  1244. u32 base, pin;
  1245. void __iomem *reg;
  1246. unsigned long pending;
  1247. unsigned int virq;
  1248. /* check from GPIO controller which pin triggered the interrupt */
  1249. for (base = 0; base < vg->chip.ngpio; base += 32) {
  1250. reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
  1251. if (!reg) {
  1252. dev_warn(vg->dev,
  1253. "Pin %i: could not retrieve interrupt status register\n",
  1254. base);
  1255. continue;
  1256. }
  1257. raw_spin_lock(&byt_lock);
  1258. pending = readl(reg);
  1259. raw_spin_unlock(&byt_lock);
  1260. for_each_set_bit(pin, &pending, 32) {
  1261. virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
  1262. generic_handle_irq(virq);
  1263. }
  1264. }
  1265. chip->irq_eoi(data);
  1266. }
  1267. static void byt_init_irq_valid_mask(struct gpio_chip *chip,
  1268. unsigned long *valid_mask,
  1269. unsigned int ngpios)
  1270. {
  1271. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  1272. void __iomem *reg;
  1273. u32 value;
  1274. int i;
  1275. /*
  1276. * Clear interrupt triggers for all pins that are GPIOs and
  1277. * do not use direct IRQ mode. This will prevent spurious
  1278. * interrupts from misconfigured pins.
  1279. */
  1280. for (i = 0; i < vg->soc->npins; i++) {
  1281. unsigned int pin = vg->soc->pins[i].number;
  1282. reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
  1283. if (!reg) {
  1284. dev_warn(vg->dev,
  1285. "Pin %i: could not retrieve conf0 register\n",
  1286. i);
  1287. continue;
  1288. }
  1289. value = readl(reg);
  1290. if (value & BYT_DIRECT_IRQ_EN) {
  1291. clear_bit(i, valid_mask);
  1292. dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
  1293. } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
  1294. byt_gpio_clear_triggering(vg, i);
  1295. dev_dbg(vg->dev, "disabling GPIO %d\n", i);
  1296. }
  1297. }
  1298. }
  1299. static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
  1300. {
  1301. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  1302. void __iomem *reg;
  1303. u32 base, value;
  1304. /* clear interrupt status trigger registers */
  1305. for (base = 0; base < vg->soc->npins; base += 32) {
  1306. reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
  1307. if (!reg) {
  1308. dev_warn(vg->dev,
  1309. "Pin %i: could not retrieve irq status reg\n",
  1310. base);
  1311. continue;
  1312. }
  1313. writel(0xffffffff, reg);
  1314. /* make sure trigger bits are cleared, if not then a pin
  1315. might be misconfigured in bios */
  1316. value = readl(reg);
  1317. if (value)
  1318. dev_err(vg->dev,
  1319. "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
  1320. base / 32, value);
  1321. }
  1322. return 0;
  1323. }
  1324. static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
  1325. {
  1326. struct intel_pinctrl *vg = gpiochip_get_data(chip);
  1327. struct device *dev = vg->dev;
  1328. int ret;
  1329. ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
  1330. if (ret)
  1331. dev_err(dev, "failed to add GPIO pin range\n");
  1332. return ret;
  1333. }
  1334. static int byt_gpio_probe(struct intel_pinctrl *vg)
  1335. {
  1336. struct platform_device *pdev = to_platform_device(vg->dev);
  1337. struct gpio_chip *gc;
  1338. int irq, ret;
  1339. /* Set up gpio chip */
  1340. vg->chip = byt_gpio_chip;
  1341. gc = &vg->chip;
  1342. gc->label = dev_name(vg->dev);
  1343. gc->base = -1;
  1344. gc->can_sleep = false;
  1345. gc->add_pin_ranges = byt_gpio_add_pin_ranges;
  1346. gc->parent = vg->dev;
  1347. gc->ngpio = vg->soc->npins;
  1348. #ifdef CONFIG_PM_SLEEP
  1349. vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
  1350. GFP_KERNEL);
  1351. if (!vg->context.pads)
  1352. return -ENOMEM;
  1353. #endif
  1354. /* set up interrupts */
  1355. irq = platform_get_irq_optional(pdev, 0);
  1356. if (irq > 0) {
  1357. struct gpio_irq_chip *girq;
  1358. vg->irqchip.name = "BYT-GPIO",
  1359. vg->irqchip.irq_ack = byt_irq_ack,
  1360. vg->irqchip.irq_mask = byt_irq_mask,
  1361. vg->irqchip.irq_unmask = byt_irq_unmask,
  1362. vg->irqchip.irq_set_type = byt_irq_type,
  1363. vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
  1364. girq = &gc->irq;
  1365. girq->chip = &vg->irqchip;
  1366. girq->init_hw = byt_gpio_irq_init_hw;
  1367. girq->init_valid_mask = byt_init_irq_valid_mask;
  1368. girq->parent_handler = byt_gpio_irq_handler;
  1369. girq->num_parents = 1;
  1370. girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
  1371. sizeof(*girq->parents), GFP_KERNEL);
  1372. if (!girq->parents)
  1373. return -ENOMEM;
  1374. girq->parents[0] = irq;
  1375. girq->default_type = IRQ_TYPE_NONE;
  1376. girq->handler = handle_bad_irq;
  1377. }
  1378. ret = devm_gpiochip_add_data(vg->dev, gc, vg);
  1379. if (ret) {
  1380. dev_err(vg->dev, "failed adding byt-gpio chip\n");
  1381. return ret;
  1382. }
  1383. return ret;
  1384. }
  1385. static int byt_set_soc_data(struct intel_pinctrl *vg,
  1386. const struct intel_pinctrl_soc_data *soc)
  1387. {
  1388. struct platform_device *pdev = to_platform_device(vg->dev);
  1389. int i;
  1390. vg->soc = soc;
  1391. vg->ncommunities = vg->soc->ncommunities;
  1392. vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
  1393. sizeof(*vg->communities), GFP_KERNEL);
  1394. if (!vg->communities)
  1395. return -ENOMEM;
  1396. for (i = 0; i < vg->soc->ncommunities; i++) {
  1397. struct intel_community *comm = vg->communities + i;
  1398. *comm = vg->soc->communities[i];
  1399. comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
  1400. if (IS_ERR(comm->pad_regs))
  1401. return PTR_ERR(comm->pad_regs);
  1402. }
  1403. return 0;
  1404. }
  1405. static const struct acpi_device_id byt_gpio_acpi_match[] = {
  1406. { "INT33B2", (kernel_ulong_t)byt_soc_data },
  1407. { "INT33FC", (kernel_ulong_t)byt_soc_data },
  1408. { }
  1409. };
  1410. static int byt_pinctrl_probe(struct platform_device *pdev)
  1411. {
  1412. const struct intel_pinctrl_soc_data *soc_data;
  1413. struct device *dev = &pdev->dev;
  1414. struct intel_pinctrl *vg;
  1415. int ret;
  1416. soc_data = intel_pinctrl_get_soc_data(pdev);
  1417. if (IS_ERR(soc_data))
  1418. return PTR_ERR(soc_data);
  1419. vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
  1420. if (!vg)
  1421. return -ENOMEM;
  1422. vg->dev = dev;
  1423. ret = byt_set_soc_data(vg, soc_data);
  1424. if (ret) {
  1425. dev_err(dev, "failed to set soc data\n");
  1426. return ret;
  1427. }
  1428. vg->pctldesc = byt_pinctrl_desc;
  1429. vg->pctldesc.name = dev_name(dev);
  1430. vg->pctldesc.pins = vg->soc->pins;
  1431. vg->pctldesc.npins = vg->soc->npins;
  1432. vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
  1433. if (IS_ERR(vg->pctldev)) {
  1434. dev_err(dev, "failed to register pinctrl driver\n");
  1435. return PTR_ERR(vg->pctldev);
  1436. }
  1437. ret = byt_gpio_probe(vg);
  1438. if (ret)
  1439. return ret;
  1440. platform_set_drvdata(pdev, vg);
  1441. pm_runtime_enable(dev);
  1442. return 0;
  1443. }
  1444. #ifdef CONFIG_PM_SLEEP
  1445. static int byt_gpio_suspend(struct device *dev)
  1446. {
  1447. struct intel_pinctrl *vg = dev_get_drvdata(dev);
  1448. unsigned long flags;
  1449. int i;
  1450. raw_spin_lock_irqsave(&byt_lock, flags);
  1451. for (i = 0; i < vg->soc->npins; i++) {
  1452. void __iomem *reg;
  1453. u32 value;
  1454. unsigned int pin = vg->soc->pins[i].number;
  1455. reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
  1456. if (!reg) {
  1457. dev_warn(vg->dev,
  1458. "Pin %i: could not retrieve conf0 register\n",
  1459. i);
  1460. continue;
  1461. }
  1462. value = readl(reg) & BYT_CONF0_RESTORE_MASK;
  1463. vg->context.pads[i].conf0 = value;
  1464. reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
  1465. value = readl(reg) & BYT_VAL_RESTORE_MASK;
  1466. vg->context.pads[i].val = value;
  1467. }
  1468. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1469. return 0;
  1470. }
  1471. static int byt_gpio_resume(struct device *dev)
  1472. {
  1473. struct intel_pinctrl *vg = dev_get_drvdata(dev);
  1474. unsigned long flags;
  1475. int i;
  1476. raw_spin_lock_irqsave(&byt_lock, flags);
  1477. for (i = 0; i < vg->soc->npins; i++) {
  1478. void __iomem *reg;
  1479. u32 value;
  1480. unsigned int pin = vg->soc->pins[i].number;
  1481. reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
  1482. if (!reg) {
  1483. dev_warn(vg->dev,
  1484. "Pin %i: could not retrieve conf0 register\n",
  1485. i);
  1486. continue;
  1487. }
  1488. value = readl(reg);
  1489. if ((value & BYT_CONF0_RESTORE_MASK) !=
  1490. vg->context.pads[i].conf0) {
  1491. value &= ~BYT_CONF0_RESTORE_MASK;
  1492. value |= vg->context.pads[i].conf0;
  1493. writel(value, reg);
  1494. dev_info(dev, "restored pin %d conf0 %#08x", i, value);
  1495. }
  1496. reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
  1497. value = readl(reg);
  1498. if ((value & BYT_VAL_RESTORE_MASK) !=
  1499. vg->context.pads[i].val) {
  1500. u32 v;
  1501. v = value & ~BYT_VAL_RESTORE_MASK;
  1502. v |= vg->context.pads[i].val;
  1503. if (v != value) {
  1504. writel(v, reg);
  1505. dev_dbg(dev, "restored pin %d val %#08x\n",
  1506. i, v);
  1507. }
  1508. }
  1509. }
  1510. raw_spin_unlock_irqrestore(&byt_lock, flags);
  1511. return 0;
  1512. }
  1513. #endif
  1514. #ifdef CONFIG_PM
  1515. static int byt_gpio_runtime_suspend(struct device *dev)
  1516. {
  1517. return 0;
  1518. }
  1519. static int byt_gpio_runtime_resume(struct device *dev)
  1520. {
  1521. return 0;
  1522. }
  1523. #endif
  1524. static const struct dev_pm_ops byt_gpio_pm_ops = {
  1525. SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
  1526. SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
  1527. NULL)
  1528. };
  1529. static struct platform_driver byt_gpio_driver = {
  1530. .probe = byt_pinctrl_probe,
  1531. .driver = {
  1532. .name = "byt_gpio",
  1533. .pm = &byt_gpio_pm_ops,
  1534. .acpi_match_table = byt_gpio_acpi_match,
  1535. .suppress_bind_attrs = true,
  1536. },
  1537. };
  1538. static int __init byt_gpio_init(void)
  1539. {
  1540. return platform_driver_register(&byt_gpio_driver);
  1541. }
  1542. subsys_initcall(byt_gpio_init);