pinctrl-imx8mm.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2017-2018 NXP
  4. */
  5. #include <linux/err.h>
  6. #include <linux/init.h>
  7. #include <linux/module.h>
  8. #include <linux/of_device.h>
  9. #include <linux/pinctrl/pinctrl.h>
  10. #include <linux/platform_device.h>
  11. #include "pinctrl-imx.h"
  12. enum imx8mm_pads {
  13. MX8MM_PAD_RESERVE0 = 0,
  14. MX8MM_PAD_RESERVE1 = 1,
  15. MX8MM_PAD_RESERVE2 = 2,
  16. MX8MM_PAD_RESERVE3 = 3,
  17. MX8MM_PAD_RESERVE4 = 4,
  18. MX8MM_PAD_RESERVE5 = 5,
  19. MX8MM_PAD_RESERVE6 = 6,
  20. MX8MM_PAD_RESERVE7 = 7,
  21. MX8MM_PAD_RESERVE8 = 8,
  22. MX8MM_PAD_RESERVE9 = 9,
  23. MX8MM_IOMUXC_GPIO1_IO00 = 10,
  24. MX8MM_IOMUXC_GPIO1_IO01 = 11,
  25. MX8MM_IOMUXC_GPIO1_IO02 = 12,
  26. MX8MM_IOMUXC_GPIO1_IO03 = 13,
  27. MX8MM_IOMUXC_GPIO1_IO04 = 14,
  28. MX8MM_IOMUXC_GPIO1_IO05 = 15,
  29. MX8MM_IOMUXC_GPIO1_IO06 = 16,
  30. MX8MM_IOMUXC_GPIO1_IO07 = 17,
  31. MX8MM_IOMUXC_GPIO1_IO08 = 18,
  32. MX8MM_IOMUXC_GPIO1_IO09 = 19,
  33. MX8MM_IOMUXC_GPIO1_IO10 = 20,
  34. MX8MM_IOMUXC_GPIO1_IO11 = 21,
  35. MX8MM_IOMUXC_GPIO1_IO12 = 22,
  36. MX8MM_IOMUXC_GPIO1_IO13 = 23,
  37. MX8MM_IOMUXC_GPIO1_IO14 = 24,
  38. MX8MM_IOMUXC_GPIO1_IO15 = 25,
  39. MX8MM_IOMUXC_ENET_MDC = 26,
  40. MX8MM_IOMUXC_ENET_MDIO = 27,
  41. MX8MM_IOMUXC_ENET_TD3 = 28,
  42. MX8MM_IOMUXC_ENET_TD2 = 29,
  43. MX8MM_IOMUXC_ENET_TD1 = 30,
  44. MX8MM_IOMUXC_ENET_TD0 = 31,
  45. MX8MM_IOMUXC_ENET_TX_CTL = 32,
  46. MX8MM_IOMUXC_ENET_TXC = 33,
  47. MX8MM_IOMUXC_ENET_RX_CTL = 34,
  48. MX8MM_IOMUXC_ENET_RXC = 35,
  49. MX8MM_IOMUXC_ENET_RD0 = 36,
  50. MX8MM_IOMUXC_ENET_RD1 = 37,
  51. MX8MM_IOMUXC_ENET_RD2 = 38,
  52. MX8MM_IOMUXC_ENET_RD3 = 39,
  53. MX8MM_IOMUXC_SD1_CLK = 40,
  54. MX8MM_IOMUXC_SD1_CMD = 41,
  55. MX8MM_IOMUXC_SD1_DATA0 = 42,
  56. MX8MM_IOMUXC_SD1_DATA1 = 43,
  57. MX8MM_IOMUXC_SD1_DATA2 = 44,
  58. MX8MM_IOMUXC_SD1_DATA3 = 45,
  59. MX8MM_IOMUXC_SD1_DATA4 = 46,
  60. MX8MM_IOMUXC_SD1_DATA5 = 47,
  61. MX8MM_IOMUXC_SD1_DATA6 = 48,
  62. MX8MM_IOMUXC_SD1_DATA7 = 49,
  63. MX8MM_IOMUXC_SD1_RESET_B = 50,
  64. MX8MM_IOMUXC_SD1_STROBE = 51,
  65. MX8MM_IOMUXC_SD2_CD_B = 52,
  66. MX8MM_IOMUXC_SD2_CLK = 53,
  67. MX8MM_IOMUXC_SD2_CMD = 54,
  68. MX8MM_IOMUXC_SD2_DATA0 = 55,
  69. MX8MM_IOMUXC_SD2_DATA1 = 56,
  70. MX8MM_IOMUXC_SD2_DATA2 = 57,
  71. MX8MM_IOMUXC_SD2_DATA3 = 58,
  72. MX8MM_IOMUXC_SD2_RESET_B = 59,
  73. MX8MM_IOMUXC_SD2_WP = 60,
  74. MX8MM_IOMUXC_NAND_ALE = 61,
  75. MX8MM_IOMUXC_NAND_CE0 = 62,
  76. MX8MM_IOMUXC_NAND_CE1 = 63,
  77. MX8MM_IOMUXC_NAND_CE2 = 64,
  78. MX8MM_IOMUXC_NAND_CE3 = 65,
  79. MX8MM_IOMUXC_NAND_CLE = 66,
  80. MX8MM_IOMUXC_NAND_DATA00 = 67,
  81. MX8MM_IOMUXC_NAND_DATA01 = 68,
  82. MX8MM_IOMUXC_NAND_DATA02 = 69,
  83. MX8MM_IOMUXC_NAND_DATA03 = 70,
  84. MX8MM_IOMUXC_NAND_DATA04 = 71,
  85. MX8MM_IOMUXC_NAND_DATA05 = 72,
  86. MX8MM_IOMUXC_NAND_DATA06 = 73,
  87. MX8MM_IOMUXC_NAND_DATA07 = 74,
  88. MX8MM_IOMUXC_NAND_DQS = 75,
  89. MX8MM_IOMUXC_NAND_RE_B = 76,
  90. MX8MM_IOMUXC_NAND_READY_B = 77,
  91. MX8MM_IOMUXC_NAND_WE_B = 78,
  92. MX8MM_IOMUXC_NAND_WP_B = 79,
  93. MX8MM_IOMUXC_SAI5_RXFS = 80,
  94. MX8MM_IOMUXC_SAI5_RXC = 81,
  95. MX8MM_IOMUXC_SAI5_RXD0 = 82,
  96. MX8MM_IOMUXC_SAI5_RXD1 = 83,
  97. MX8MM_IOMUXC_SAI5_RXD2 = 84,
  98. MX8MM_IOMUXC_SAI5_RXD3 = 85,
  99. MX8MM_IOMUXC_SAI5_MCLK = 86,
  100. MX8MM_IOMUXC_SAI1_RXFS = 87,
  101. MX8MM_IOMUXC_SAI1_RXC = 88,
  102. MX8MM_IOMUXC_SAI1_RXD0 = 89,
  103. MX8MM_IOMUXC_SAI1_RXD1 = 90,
  104. MX8MM_IOMUXC_SAI1_RXD2 = 91,
  105. MX8MM_IOMUXC_SAI1_RXD3 = 92,
  106. MX8MM_IOMUXC_SAI1_RXD4 = 93,
  107. MX8MM_IOMUXC_SAI1_RXD5 = 94,
  108. MX8MM_IOMUXC_SAI1_RXD6 = 95,
  109. MX8MM_IOMUXC_SAI1_RXD7 = 96,
  110. MX8MM_IOMUXC_SAI1_TXFS = 97,
  111. MX8MM_IOMUXC_SAI1_TXC = 98,
  112. MX8MM_IOMUXC_SAI1_TXD0 = 99,
  113. MX8MM_IOMUXC_SAI1_TXD1 = 100,
  114. MX8MM_IOMUXC_SAI1_TXD2 = 101,
  115. MX8MM_IOMUXC_SAI1_TXD3 = 102,
  116. MX8MM_IOMUXC_SAI1_TXD4 = 103,
  117. MX8MM_IOMUXC_SAI1_TXD5 = 104,
  118. MX8MM_IOMUXC_SAI1_TXD6 = 105,
  119. MX8MM_IOMUXC_SAI1_TXD7 = 106,
  120. MX8MM_IOMUXC_SAI1_MCLK = 107,
  121. MX8MM_IOMUXC_SAI2_RXFS = 108,
  122. MX8MM_IOMUXC_SAI2_RXC = 109,
  123. MX8MM_IOMUXC_SAI2_RXD0 = 110,
  124. MX8MM_IOMUXC_SAI2_TXFS = 111,
  125. MX8MM_IOMUXC_SAI2_TXC = 112,
  126. MX8MM_IOMUXC_SAI2_TXD0 = 113,
  127. MX8MM_IOMUXC_SAI2_MCLK = 114,
  128. MX8MM_IOMUXC_SAI3_RXFS = 115,
  129. MX8MM_IOMUXC_SAI3_RXC = 116,
  130. MX8MM_IOMUXC_SAI3_RXD = 117,
  131. MX8MM_IOMUXC_SAI3_TXFS = 118,
  132. MX8MM_IOMUXC_SAI3_TXC = 119,
  133. MX8MM_IOMUXC_SAI3_TXD = 120,
  134. MX8MM_IOMUXC_SAI3_MCLK = 121,
  135. MX8MM_IOMUXC_SPDIF_TX = 122,
  136. MX8MM_IOMUXC_SPDIF_RX = 123,
  137. MX8MM_IOMUXC_SPDIF_EXT_CLK = 124,
  138. MX8MM_IOMUXC_ECSPI1_SCLK = 125,
  139. MX8MM_IOMUXC_ECSPI1_MOSI = 126,
  140. MX8MM_IOMUXC_ECSPI1_MISO = 127,
  141. MX8MM_IOMUXC_ECSPI1_SS0 = 128,
  142. MX8MM_IOMUXC_ECSPI2_SCLK = 129,
  143. MX8MM_IOMUXC_ECSPI2_MOSI = 130,
  144. MX8MM_IOMUXC_ECSPI2_MISO = 131,
  145. MX8MM_IOMUXC_ECSPI2_SS0 = 132,
  146. MX8MM_IOMUXC_I2C1_SCL = 133,
  147. MX8MM_IOMUXC_I2C1_SDA = 134,
  148. MX8MM_IOMUXC_I2C2_SCL = 135,
  149. MX8MM_IOMUXC_I2C2_SDA = 136,
  150. MX8MM_IOMUXC_I2C3_SCL = 137,
  151. MX8MM_IOMUXC_I2C3_SDA = 138,
  152. MX8MM_IOMUXC_I2C4_SCL = 139,
  153. MX8MM_IOMUXC_I2C4_SDA = 140,
  154. MX8MM_IOMUXC_UART1_RXD = 141,
  155. MX8MM_IOMUXC_UART1_TXD = 142,
  156. MX8MM_IOMUXC_UART2_RXD = 143,
  157. MX8MM_IOMUXC_UART2_TXD = 144,
  158. MX8MM_IOMUXC_UART3_RXD = 145,
  159. MX8MM_IOMUXC_UART3_TXD = 146,
  160. MX8MM_IOMUXC_UART4_RXD = 147,
  161. MX8MM_IOMUXC_UART4_TXD = 148,
  162. };
  163. /* Pad names for the pinmux subsystem */
  164. static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] = {
  165. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0),
  166. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1),
  167. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2),
  168. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3),
  169. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4),
  170. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5),
  171. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6),
  172. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7),
  173. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8),
  174. IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9),
  175. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00),
  176. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01),
  177. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02),
  178. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03),
  179. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04),
  180. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05),
  181. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06),
  182. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07),
  183. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08),
  184. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09),
  185. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10),
  186. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11),
  187. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12),
  188. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13),
  189. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14),
  190. IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15),
  191. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC),
  192. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO),
  193. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3),
  194. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2),
  195. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1),
  196. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0),
  197. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL),
  198. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC),
  199. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL),
  200. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC),
  201. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0),
  202. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1),
  203. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2),
  204. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3),
  205. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK),
  206. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD),
  207. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0),
  208. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1),
  209. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2),
  210. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3),
  211. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4),
  212. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5),
  213. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6),
  214. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7),
  215. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B),
  216. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE),
  217. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B),
  218. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK),
  219. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD),
  220. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0),
  221. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1),
  222. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2),
  223. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3),
  224. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B),
  225. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP),
  226. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE),
  227. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0),
  228. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1),
  229. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2),
  230. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3),
  231. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE),
  232. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00),
  233. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01),
  234. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02),
  235. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03),
  236. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04),
  237. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05),
  238. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06),
  239. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07),
  240. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS),
  241. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B),
  242. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B),
  243. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B),
  244. IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B),
  245. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS),
  246. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC),
  247. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0),
  248. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1),
  249. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2),
  250. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3),
  251. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK),
  252. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS),
  253. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC),
  254. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0),
  255. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1),
  256. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2),
  257. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3),
  258. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4),
  259. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5),
  260. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6),
  261. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7),
  262. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS),
  263. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC),
  264. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0),
  265. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1),
  266. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2),
  267. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3),
  268. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4),
  269. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5),
  270. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6),
  271. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7),
  272. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK),
  273. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS),
  274. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC),
  275. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0),
  276. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS),
  277. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC),
  278. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0),
  279. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK),
  280. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS),
  281. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC),
  282. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD),
  283. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS),
  284. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC),
  285. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD),
  286. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK),
  287. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX),
  288. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX),
  289. IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK),
  290. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK),
  291. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI),
  292. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO),
  293. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0),
  294. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK),
  295. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI),
  296. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO),
  297. IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0),
  298. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL),
  299. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA),
  300. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL),
  301. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA),
  302. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL),
  303. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA),
  304. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL),
  305. IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA),
  306. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD),
  307. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD),
  308. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD),
  309. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD),
  310. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD),
  311. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD),
  312. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD),
  313. IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD),
  314. };
  315. static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = {
  316. .pins = imx8mm_pinctrl_pads,
  317. .npins = ARRAY_SIZE(imx8mm_pinctrl_pads),
  318. .gpr_compatible = "fsl,imx8mm-iomuxc-gpr",
  319. };
  320. static const struct of_device_id imx8mm_pinctrl_of_match[] = {
  321. { .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
  322. { /* sentinel */ }
  323. };
  324. MODULE_DEVICE_TABLE(of, imx8mm_pinctrl_of_match);
  325. static int imx8mm_pinctrl_probe(struct platform_device *pdev)
  326. {
  327. return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info);
  328. }
  329. static struct platform_driver imx8mm_pinctrl_driver = {
  330. .driver = {
  331. .name = "imx8mm-pinctrl",
  332. .of_match_table = of_match_ptr(imx8mm_pinctrl_of_match),
  333. .suppress_bind_attrs = true,
  334. },
  335. .probe = imx8mm_pinctrl_probe,
  336. };
  337. static int __init imx8mm_pinctrl_init(void)
  338. {
  339. return platform_driver_register(&imx8mm_pinctrl_driver);
  340. }
  341. arch_initcall(imx8mm_pinctrl_init);
  342. MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
  343. MODULE_DESCRIPTION("NXP i.MX8MM pinctrl driver");
  344. MODULE_LICENSE("GPL v2");