pinctrl-imx6ul.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale imx6ul pinctrl driver
  4. //
  5. // Author: Anson Huang <Anson.Huang@freescale.com>
  6. // Copyright (C) 2015 Freescale Semiconductor, Inc.
  7. #include <linux/err.h>
  8. #include <linux/init.h>
  9. #include <linux/io.h>
  10. #include <linux/of.h>
  11. #include <linux/of_device.h>
  12. #include <linux/pinctrl/pinctrl.h>
  13. #include "pinctrl-imx.h"
  14. enum imx6ul_pads {
  15. MX6UL_PAD_RESERVE0 = 0,
  16. MX6UL_PAD_RESERVE1 = 1,
  17. MX6UL_PAD_RESERVE2 = 2,
  18. MX6UL_PAD_RESERVE3 = 3,
  19. MX6UL_PAD_RESERVE4 = 4,
  20. MX6UL_PAD_RESERVE5 = 5,
  21. MX6UL_PAD_RESERVE6 = 6,
  22. MX6UL_PAD_RESERVE7 = 7,
  23. MX6UL_PAD_RESERVE8 = 8,
  24. MX6UL_PAD_RESERVE9 = 9,
  25. MX6UL_PAD_RESERVE10 = 10,
  26. MX6UL_PAD_SNVS_TAMPER4 = 11,
  27. MX6UL_PAD_RESERVE12 = 12,
  28. MX6UL_PAD_RESERVE13 = 13,
  29. MX6UL_PAD_RESERVE14 = 14,
  30. MX6UL_PAD_RESERVE15 = 15,
  31. MX6UL_PAD_RESERVE16 = 16,
  32. MX6UL_PAD_JTAG_MOD = 17,
  33. MX6UL_PAD_JTAG_TMS = 18,
  34. MX6UL_PAD_JTAG_TDO = 19,
  35. MX6UL_PAD_JTAG_TDI = 20,
  36. MX6UL_PAD_JTAG_TCK = 21,
  37. MX6UL_PAD_JTAG_TRST_B = 22,
  38. MX6UL_PAD_GPIO1_IO00 = 23,
  39. MX6UL_PAD_GPIO1_IO01 = 24,
  40. MX6UL_PAD_GPIO1_IO02 = 25,
  41. MX6UL_PAD_GPIO1_IO03 = 26,
  42. MX6UL_PAD_GPIO1_IO04 = 27,
  43. MX6UL_PAD_GPIO1_IO05 = 28,
  44. MX6UL_PAD_GPIO1_IO06 = 29,
  45. MX6UL_PAD_GPIO1_IO07 = 30,
  46. MX6UL_PAD_GPIO1_IO08 = 31,
  47. MX6UL_PAD_GPIO1_IO09 = 32,
  48. MX6UL_PAD_UART1_TX_DATA = 33,
  49. MX6UL_PAD_UART1_RX_DATA = 34,
  50. MX6UL_PAD_UART1_CTS_B = 35,
  51. MX6UL_PAD_UART1_RTS_B = 36,
  52. MX6UL_PAD_UART2_TX_DATA = 37,
  53. MX6UL_PAD_UART2_RX_DATA = 38,
  54. MX6UL_PAD_UART2_CTS_B = 39,
  55. MX6UL_PAD_UART2_RTS_B = 40,
  56. MX6UL_PAD_UART3_TX_DATA = 41,
  57. MX6UL_PAD_UART3_RX_DATA = 42,
  58. MX6UL_PAD_UART3_CTS_B = 43,
  59. MX6UL_PAD_UART3_RTS_B = 44,
  60. MX6UL_PAD_UART4_TX_DATA = 45,
  61. MX6UL_PAD_UART4_RX_DATA = 46,
  62. MX6UL_PAD_UART5_TX_DATA = 47,
  63. MX6UL_PAD_UART5_RX_DATA = 48,
  64. MX6UL_PAD_ENET1_RX_DATA0 = 49,
  65. MX6UL_PAD_ENET1_RX_DATA1 = 50,
  66. MX6UL_PAD_ENET1_RX_EN = 51,
  67. MX6UL_PAD_ENET1_TX_DATA0 = 52,
  68. MX6UL_PAD_ENET1_TX_DATA1 = 53,
  69. MX6UL_PAD_ENET1_TX_EN = 54,
  70. MX6UL_PAD_ENET1_TX_CLK = 55,
  71. MX6UL_PAD_ENET1_RX_ER = 56,
  72. MX6UL_PAD_ENET2_RX_DATA0 = 57,
  73. MX6UL_PAD_ENET2_RX_DATA1 = 58,
  74. MX6UL_PAD_ENET2_RX_EN = 59,
  75. MX6UL_PAD_ENET2_TX_DATA0 = 60,
  76. MX6UL_PAD_ENET2_TX_DATA1 = 61,
  77. MX6UL_PAD_ENET2_TX_EN = 62,
  78. MX6UL_PAD_ENET2_TX_CLK = 63,
  79. MX6UL_PAD_ENET2_RX_ER = 64,
  80. MX6UL_PAD_LCD_CLK = 65,
  81. MX6UL_PAD_LCD_ENABLE = 66,
  82. MX6UL_PAD_LCD_HSYNC = 67,
  83. MX6UL_PAD_LCD_VSYNC = 68,
  84. MX6UL_PAD_LCD_RESET = 69,
  85. MX6UL_PAD_LCD_DATA00 = 70,
  86. MX6UL_PAD_LCD_DATA01 = 71,
  87. MX6UL_PAD_LCD_DATA02 = 72,
  88. MX6UL_PAD_LCD_DATA03 = 73,
  89. MX6UL_PAD_LCD_DATA04 = 74,
  90. MX6UL_PAD_LCD_DATA05 = 75,
  91. MX6UL_PAD_LCD_DATA06 = 76,
  92. MX6UL_PAD_LCD_DATA07 = 77,
  93. MX6UL_PAD_LCD_DATA08 = 78,
  94. MX6UL_PAD_LCD_DATA09 = 79,
  95. MX6UL_PAD_LCD_DATA10 = 80,
  96. MX6UL_PAD_LCD_DATA11 = 81,
  97. MX6UL_PAD_LCD_DATA12 = 82,
  98. MX6UL_PAD_LCD_DATA13 = 83,
  99. MX6UL_PAD_LCD_DATA14 = 84,
  100. MX6UL_PAD_LCD_DATA15 = 85,
  101. MX6UL_PAD_LCD_DATA16 = 86,
  102. MX6UL_PAD_LCD_DATA17 = 87,
  103. MX6UL_PAD_LCD_DATA18 = 88,
  104. MX6UL_PAD_LCD_DATA19 = 89,
  105. MX6UL_PAD_LCD_DATA20 = 90,
  106. MX6UL_PAD_LCD_DATA21 = 91,
  107. MX6UL_PAD_LCD_DATA22 = 92,
  108. MX6UL_PAD_LCD_DATA23 = 93,
  109. MX6UL_PAD_NAND_RE_B = 94,
  110. MX6UL_PAD_NAND_WE_B = 95,
  111. MX6UL_PAD_NAND_DATA00 = 96,
  112. MX6UL_PAD_NAND_DATA01 = 97,
  113. MX6UL_PAD_NAND_DATA02 = 98,
  114. MX6UL_PAD_NAND_DATA03 = 99,
  115. MX6UL_PAD_NAND_DATA04 = 100,
  116. MX6UL_PAD_NAND_DATA05 = 101,
  117. MX6UL_PAD_NAND_DATA06 = 102,
  118. MX6UL_PAD_NAND_DATA07 = 103,
  119. MX6UL_PAD_NAND_ALE = 104,
  120. MX6UL_PAD_NAND_WP_B = 105,
  121. MX6UL_PAD_NAND_READY_B = 106,
  122. MX6UL_PAD_NAND_CE0_B = 107,
  123. MX6UL_PAD_NAND_CE1_B = 108,
  124. MX6UL_PAD_NAND_CLE = 109,
  125. MX6UL_PAD_NAND_DQS = 110,
  126. MX6UL_PAD_SD1_CMD = 111,
  127. MX6UL_PAD_SD1_CLK = 112,
  128. MX6UL_PAD_SD1_DATA0 = 113,
  129. MX6UL_PAD_SD1_DATA1 = 114,
  130. MX6UL_PAD_SD1_DATA2 = 115,
  131. MX6UL_PAD_SD1_DATA3 = 116,
  132. MX6UL_PAD_CSI_MCLK = 117,
  133. MX6UL_PAD_CSI_PIXCLK = 118,
  134. MX6UL_PAD_CSI_VSYNC = 119,
  135. MX6UL_PAD_CSI_HSYNC = 120,
  136. MX6UL_PAD_CSI_DATA00 = 121,
  137. MX6UL_PAD_CSI_DATA01 = 122,
  138. MX6UL_PAD_CSI_DATA02 = 123,
  139. MX6UL_PAD_CSI_DATA03 = 124,
  140. MX6UL_PAD_CSI_DATA04 = 125,
  141. MX6UL_PAD_CSI_DATA05 = 126,
  142. MX6UL_PAD_CSI_DATA06 = 127,
  143. MX6UL_PAD_CSI_DATA07 = 128,
  144. };
  145. enum imx6ull_lpsr_pads {
  146. MX6ULL_PAD_BOOT_MODE0 = 0,
  147. MX6ULL_PAD_BOOT_MODE1 = 1,
  148. MX6ULL_PAD_SNVS_TAMPER0 = 2,
  149. MX6ULL_PAD_SNVS_TAMPER1 = 3,
  150. MX6ULL_PAD_SNVS_TAMPER2 = 4,
  151. MX6ULL_PAD_SNVS_TAMPER3 = 5,
  152. MX6ULL_PAD_SNVS_TAMPER4 = 6,
  153. MX6ULL_PAD_SNVS_TAMPER5 = 7,
  154. MX6ULL_PAD_SNVS_TAMPER6 = 8,
  155. MX6ULL_PAD_SNVS_TAMPER7 = 9,
  156. MX6ULL_PAD_SNVS_TAMPER8 = 10,
  157. MX6ULL_PAD_SNVS_TAMPER9 = 11,
  158. };
  159. /* Pad names for the pinmux subsystem */
  160. static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
  161. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
  162. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1),
  163. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2),
  164. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3),
  165. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4),
  166. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5),
  167. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6),
  168. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7),
  169. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8),
  170. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9),
  171. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10),
  172. IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4),
  173. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12),
  174. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13),
  175. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14),
  176. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15),
  177. IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16),
  178. IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD),
  179. IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS),
  180. IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO),
  181. IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI),
  182. IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK),
  183. IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B),
  184. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00),
  185. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01),
  186. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02),
  187. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03),
  188. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04),
  189. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05),
  190. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06),
  191. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07),
  192. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08),
  193. IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09),
  194. IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA),
  195. IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA),
  196. IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B),
  197. IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B),
  198. IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA),
  199. IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA),
  200. IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B),
  201. IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B),
  202. IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA),
  203. IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA),
  204. IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B),
  205. IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B),
  206. IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA),
  207. IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA),
  208. IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA),
  209. IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA),
  210. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0),
  211. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1),
  212. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN),
  213. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0),
  214. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1),
  215. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN),
  216. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK),
  217. IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER),
  218. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0),
  219. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1),
  220. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN),
  221. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0),
  222. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1),
  223. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN),
  224. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK),
  225. IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER),
  226. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK),
  227. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE),
  228. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC),
  229. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC),
  230. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET),
  231. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00),
  232. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01),
  233. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02),
  234. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03),
  235. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04),
  236. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05),
  237. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06),
  238. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07),
  239. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08),
  240. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09),
  241. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10),
  242. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11),
  243. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12),
  244. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13),
  245. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14),
  246. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15),
  247. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16),
  248. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17),
  249. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18),
  250. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19),
  251. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20),
  252. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21),
  253. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22),
  254. IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23),
  255. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B),
  256. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B),
  257. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00),
  258. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01),
  259. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02),
  260. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03),
  261. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04),
  262. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05),
  263. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06),
  264. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07),
  265. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE),
  266. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B),
  267. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B),
  268. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B),
  269. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B),
  270. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE),
  271. IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS),
  272. IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD),
  273. IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK),
  274. IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0),
  275. IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1),
  276. IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2),
  277. IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3),
  278. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK),
  279. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK),
  280. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC),
  281. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC),
  282. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00),
  283. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01),
  284. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02),
  285. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03),
  286. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04),
  287. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05),
  288. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06),
  289. IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
  290. };
  291. /* pad for i.MX6ULL lpsr pinmux */
  292. static const struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = {
  293. IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0),
  294. IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1),
  295. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0),
  296. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1),
  297. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2),
  298. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3),
  299. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4),
  300. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5),
  301. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6),
  302. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7),
  303. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8),
  304. IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9),
  305. };
  306. static const struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
  307. .pins = imx6ul_pinctrl_pads,
  308. .npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
  309. .gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
  310. };
  311. static const struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = {
  312. .pins = imx6ull_snvs_pinctrl_pads,
  313. .npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads),
  314. .flags = ZERO_OFFSET_VALID,
  315. };
  316. static const struct of_device_id imx6ul_pinctrl_of_match[] = {
  317. { .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, },
  318. { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
  319. { /* sentinel */ }
  320. };
  321. static int imx6ul_pinctrl_probe(struct platform_device *pdev)
  322. {
  323. const struct imx_pinctrl_soc_info *pinctrl_info;
  324. pinctrl_info = of_device_get_match_data(&pdev->dev);
  325. if (!pinctrl_info)
  326. return -ENODEV;
  327. return imx_pinctrl_probe(pdev, pinctrl_info);
  328. }
  329. static struct platform_driver imx6ul_pinctrl_driver = {
  330. .driver = {
  331. .name = "imx6ul-pinctrl",
  332. .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match),
  333. },
  334. .probe = imx6ul_pinctrl_probe,
  335. };
  336. static int __init imx6ul_pinctrl_init(void)
  337. {
  338. return platform_driver_register(&imx6ul_pinctrl_driver);
  339. }
  340. arch_initcall(imx6ul_pinctrl_init);