pinctrl-imx6sll.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. // Copyright 2017-2018 NXP.
  5. #include <linux/err.h>
  6. #include <linux/init.h>
  7. #include <linux/io.h>
  8. #include <linux/module.h>
  9. #include <linux/of.h>
  10. #include <linux/of_device.h>
  11. #include <linux/pinctrl/pinctrl.h>
  12. #include "pinctrl-imx.h"
  13. enum imx6sll_pads {
  14. MX6SLL_PAD_RESERVE0 = 0,
  15. MX6SLL_PAD_RESERVE1 = 1,
  16. MX6SLL_PAD_RESERVE2 = 2,
  17. MX6SLL_PAD_RESERVE3 = 3,
  18. MX6SLL_PAD_RESERVE4 = 4,
  19. MX6SLL_PAD_WDOG_B = 5,
  20. MX6SLL_PAD_REF_CLK_24M = 6,
  21. MX6SLL_PAD_REF_CLK_32K = 7,
  22. MX6SLL_PAD_PWM1 = 8,
  23. MX6SLL_PAD_KEY_COL0 = 9,
  24. MX6SLL_PAD_KEY_ROW0 = 10,
  25. MX6SLL_PAD_KEY_COL1 = 11,
  26. MX6SLL_PAD_KEY_ROW1 = 12,
  27. MX6SLL_PAD_KEY_COL2 = 13,
  28. MX6SLL_PAD_KEY_ROW2 = 14,
  29. MX6SLL_PAD_KEY_COL3 = 15,
  30. MX6SLL_PAD_KEY_ROW3 = 16,
  31. MX6SLL_PAD_KEY_COL4 = 17,
  32. MX6SLL_PAD_KEY_ROW4 = 18,
  33. MX6SLL_PAD_KEY_COL5 = 19,
  34. MX6SLL_PAD_KEY_ROW5 = 20,
  35. MX6SLL_PAD_KEY_COL6 = 21,
  36. MX6SLL_PAD_KEY_ROW6 = 22,
  37. MX6SLL_PAD_KEY_COL7 = 23,
  38. MX6SLL_PAD_KEY_ROW7 = 24,
  39. MX6SLL_PAD_EPDC_DATA00 = 25,
  40. MX6SLL_PAD_EPDC_DATA01 = 26,
  41. MX6SLL_PAD_EPDC_DATA02 = 27,
  42. MX6SLL_PAD_EPDC_DATA03 = 28,
  43. MX6SLL_PAD_EPDC_DATA04 = 29,
  44. MX6SLL_PAD_EPDC_DATA05 = 30,
  45. MX6SLL_PAD_EPDC_DATA06 = 31,
  46. MX6SLL_PAD_EPDC_DATA07 = 32,
  47. MX6SLL_PAD_EPDC_DATA08 = 33,
  48. MX6SLL_PAD_EPDC_DATA09 = 34,
  49. MX6SLL_PAD_EPDC_DATA10 = 35,
  50. MX6SLL_PAD_EPDC_DATA11 = 36,
  51. MX6SLL_PAD_EPDC_DATA12 = 37,
  52. MX6SLL_PAD_EPDC_DATA13 = 38,
  53. MX6SLL_PAD_EPDC_DATA14 = 39,
  54. MX6SLL_PAD_EPDC_DATA15 = 40,
  55. MX6SLL_PAD_EPDC_SDCLK = 41,
  56. MX6SLL_PAD_EPDC_SDLE = 42,
  57. MX6SLL_PAD_EPDC_SDOE = 43,
  58. MX6SLL_PAD_EPDC_SDSHR = 44,
  59. MX6SLL_PAD_EPDC_SDCE0 = 45,
  60. MX6SLL_PAD_EPDC_SDCE1 = 46,
  61. MX6SLL_PAD_EPDC_SDCE2 = 47,
  62. MX6SLL_PAD_EPDC_SDCE3 = 48,
  63. MX6SLL_PAD_EPDC_GDCLK = 49,
  64. MX6SLL_PAD_EPDC_GDOE = 50,
  65. MX6SLL_PAD_EPDC_GDRL = 51,
  66. MX6SLL_PAD_EPDC_GDSP = 52,
  67. MX6SLL_PAD_EPDC_VCOM0 = 53,
  68. MX6SLL_PAD_EPDC_VCOM1 = 54,
  69. MX6SLL_PAD_EPDC_BDR0 = 55,
  70. MX6SLL_PAD_EPDC_BDR1 = 56,
  71. MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
  72. MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
  73. MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
  74. MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
  75. MX6SLL_PAD_EPDC_PWR_COM = 61,
  76. MX6SLL_PAD_EPDC_PWR_INT = 62,
  77. MX6SLL_PAD_EPDC_PWR_STAT = 63,
  78. MX6SLL_PAD_EPDC_PWR_WAKE = 64,
  79. MX6SLL_PAD_LCD_CLK = 65,
  80. MX6SLL_PAD_LCD_ENABLE = 66,
  81. MX6SLL_PAD_LCD_HSYNC = 67,
  82. MX6SLL_PAD_LCD_VSYNC = 68,
  83. MX6SLL_PAD_LCD_RESET = 69,
  84. MX6SLL_PAD_LCD_DATA00 = 70,
  85. MX6SLL_PAD_LCD_DATA01 = 71,
  86. MX6SLL_PAD_LCD_DATA02 = 72,
  87. MX6SLL_PAD_LCD_DATA03 = 73,
  88. MX6SLL_PAD_LCD_DATA04 = 74,
  89. MX6SLL_PAD_LCD_DATA05 = 75,
  90. MX6SLL_PAD_LCD_DATA06 = 76,
  91. MX6SLL_PAD_LCD_DATA07 = 77,
  92. MX6SLL_PAD_LCD_DATA08 = 78,
  93. MX6SLL_PAD_LCD_DATA09 = 79,
  94. MX6SLL_PAD_LCD_DATA10 = 80,
  95. MX6SLL_PAD_LCD_DATA11 = 81,
  96. MX6SLL_PAD_LCD_DATA12 = 82,
  97. MX6SLL_PAD_LCD_DATA13 = 83,
  98. MX6SLL_PAD_LCD_DATA14 = 84,
  99. MX6SLL_PAD_LCD_DATA15 = 85,
  100. MX6SLL_PAD_LCD_DATA16 = 86,
  101. MX6SLL_PAD_LCD_DATA17 = 87,
  102. MX6SLL_PAD_LCD_DATA18 = 88,
  103. MX6SLL_PAD_LCD_DATA19 = 89,
  104. MX6SLL_PAD_LCD_DATA20 = 90,
  105. MX6SLL_PAD_LCD_DATA21 = 91,
  106. MX6SLL_PAD_LCD_DATA22 = 92,
  107. MX6SLL_PAD_LCD_DATA23 = 93,
  108. MX6SLL_PAD_AUD_RXFS = 94,
  109. MX6SLL_PAD_AUD_RXC = 95,
  110. MX6SLL_PAD_AUD_RXD = 96,
  111. MX6SLL_PAD_AUD_TXC = 97,
  112. MX6SLL_PAD_AUD_TXFS = 98,
  113. MX6SLL_PAD_AUD_TXD = 99,
  114. MX6SLL_PAD_AUD_MCLK = 100,
  115. MX6SLL_PAD_UART1_RXD = 101,
  116. MX6SLL_PAD_UART1_TXD = 102,
  117. MX6SLL_PAD_I2C1_SCL = 103,
  118. MX6SLL_PAD_I2C1_SDA = 104,
  119. MX6SLL_PAD_I2C2_SCL = 105,
  120. MX6SLL_PAD_I2C2_SDA = 106,
  121. MX6SLL_PAD_ECSPI1_SCLK = 107,
  122. MX6SLL_PAD_ECSPI1_MOSI = 108,
  123. MX6SLL_PAD_ECSPI1_MISO = 109,
  124. MX6SLL_PAD_ECSPI1_SS0 = 110,
  125. MX6SLL_PAD_ECSPI2_SCLK = 111,
  126. MX6SLL_PAD_ECSPI2_MOSI = 112,
  127. MX6SLL_PAD_ECSPI2_MISO = 113,
  128. MX6SLL_PAD_ECSPI2_SS0 = 114,
  129. MX6SLL_PAD_SD1_CLK = 115,
  130. MX6SLL_PAD_SD1_CMD = 116,
  131. MX6SLL_PAD_SD1_DATA0 = 117,
  132. MX6SLL_PAD_SD1_DATA1 = 118,
  133. MX6SLL_PAD_SD1_DATA2 = 119,
  134. MX6SLL_PAD_SD1_DATA3 = 120,
  135. MX6SLL_PAD_SD1_DATA4 = 121,
  136. MX6SLL_PAD_SD1_DATA5 = 122,
  137. MX6SLL_PAD_SD1_DATA6 = 123,
  138. MX6SLL_PAD_SD1_DATA7 = 124,
  139. MX6SLL_PAD_SD2_RESET = 125,
  140. MX6SLL_PAD_SD2_CLK = 126,
  141. MX6SLL_PAD_SD2_CMD = 127,
  142. MX6SLL_PAD_SD2_DATA0 = 128,
  143. MX6SLL_PAD_SD2_DATA1 = 129,
  144. MX6SLL_PAD_SD2_DATA2 = 130,
  145. MX6SLL_PAD_SD2_DATA3 = 131,
  146. MX6SLL_PAD_SD2_DATA4 = 132,
  147. MX6SLL_PAD_SD2_DATA5 = 133,
  148. MX6SLL_PAD_SD2_DATA6 = 134,
  149. MX6SLL_PAD_SD2_DATA7 = 135,
  150. MX6SLL_PAD_SD3_CLK = 136,
  151. MX6SLL_PAD_SD3_CMD = 137,
  152. MX6SLL_PAD_SD3_DATA0 = 138,
  153. MX6SLL_PAD_SD3_DATA1 = 139,
  154. MX6SLL_PAD_SD3_DATA2 = 140,
  155. MX6SLL_PAD_SD3_DATA3 = 141,
  156. MX6SLL_PAD_GPIO4_IO20 = 142,
  157. MX6SLL_PAD_GPIO4_IO21 = 143,
  158. MX6SLL_PAD_GPIO4_IO19 = 144,
  159. MX6SLL_PAD_GPIO4_IO25 = 145,
  160. MX6SLL_PAD_GPIO4_IO18 = 146,
  161. MX6SLL_PAD_GPIO4_IO24 = 147,
  162. MX6SLL_PAD_GPIO4_IO23 = 148,
  163. MX6SLL_PAD_GPIO4_IO17 = 149,
  164. MX6SLL_PAD_GPIO4_IO22 = 150,
  165. MX6SLL_PAD_GPIO4_IO16 = 151,
  166. MX6SLL_PAD_GPIO4_IO26 = 152,
  167. };
  168. /* Pad names for the pinmux subsystem */
  169. static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
  170. IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
  171. IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
  172. IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
  173. IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
  174. IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
  175. IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
  176. IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
  177. IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
  178. IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
  179. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
  180. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
  181. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
  182. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
  183. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
  184. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
  185. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
  186. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
  187. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
  188. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
  189. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
  190. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
  191. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
  192. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
  193. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
  194. IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
  195. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
  196. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
  197. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
  198. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
  199. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
  200. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
  201. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
  202. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
  203. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
  204. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
  205. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
  206. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
  207. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
  208. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
  209. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
  210. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
  211. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
  212. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
  213. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
  214. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
  215. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
  216. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
  217. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
  218. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
  219. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
  220. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
  221. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
  222. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
  223. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
  224. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
  225. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
  226. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
  227. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
  228. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
  229. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
  230. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
  231. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
  232. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
  233. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
  234. IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
  235. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
  236. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
  237. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
  238. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
  239. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
  240. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
  241. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
  242. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
  243. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
  244. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
  245. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
  246. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
  247. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
  248. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
  249. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
  250. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
  251. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
  252. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
  253. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
  254. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
  255. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
  256. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
  257. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
  258. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
  259. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
  260. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
  261. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
  262. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
  263. IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
  264. IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
  265. IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
  266. IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
  267. IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
  268. IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
  269. IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
  270. IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
  271. IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
  272. IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
  273. IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
  274. IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
  275. IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
  276. IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
  277. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
  278. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
  279. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
  280. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
  281. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
  282. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
  283. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
  284. IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
  285. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
  286. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
  287. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
  288. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
  289. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
  290. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
  291. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
  292. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
  293. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
  294. IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
  295. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
  296. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
  297. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
  298. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
  299. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
  300. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
  301. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
  302. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
  303. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
  304. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
  305. IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
  306. IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
  307. IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
  308. IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
  309. IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
  310. IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
  311. IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
  312. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
  313. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
  314. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
  315. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
  316. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
  317. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
  318. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
  319. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
  320. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
  321. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
  322. IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
  323. };
  324. static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
  325. .pins = imx6sll_pinctrl_pads,
  326. .npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
  327. .gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
  328. };
  329. static const struct of_device_id imx6sll_pinctrl_of_match[] = {
  330. { .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
  331. { /* sentinel */ }
  332. };
  333. static int imx6sll_pinctrl_probe(struct platform_device *pdev)
  334. {
  335. return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
  336. }
  337. static struct platform_driver imx6sll_pinctrl_driver = {
  338. .driver = {
  339. .name = "imx6sll-pinctrl",
  340. .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
  341. .suppress_bind_attrs = true,
  342. },
  343. .probe = imx6sll_pinctrl_probe,
  344. };
  345. static int __init imx6sll_pinctrl_init(void)
  346. {
  347. return platform_driver_register(&imx6sll_pinctrl_driver);
  348. }
  349. arch_initcall(imx6sll_pinctrl_init);