pinctrl-imx28.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Freescale i.MX28 pinctrl driver
  4. //
  5. // Author: Shawn Guo <shawn.guo@linaro.org>
  6. // Copyright 2012 Freescale Semiconductor, Inc.
  7. #include <linux/init.h>
  8. #include <linux/of_device.h>
  9. #include <linux/pinctrl/pinctrl.h>
  10. #include "pinctrl-mxs.h"
  11. enum imx28_pin_enum {
  12. GPMI_D00 = PINID(0, 0),
  13. GPMI_D01 = PINID(0, 1),
  14. GPMI_D02 = PINID(0, 2),
  15. GPMI_D03 = PINID(0, 3),
  16. GPMI_D04 = PINID(0, 4),
  17. GPMI_D05 = PINID(0, 5),
  18. GPMI_D06 = PINID(0, 6),
  19. GPMI_D07 = PINID(0, 7),
  20. GPMI_CE0N = PINID(0, 16),
  21. GPMI_CE1N = PINID(0, 17),
  22. GPMI_CE2N = PINID(0, 18),
  23. GPMI_CE3N = PINID(0, 19),
  24. GPMI_RDY0 = PINID(0, 20),
  25. GPMI_RDY1 = PINID(0, 21),
  26. GPMI_RDY2 = PINID(0, 22),
  27. GPMI_RDY3 = PINID(0, 23),
  28. GPMI_RDN = PINID(0, 24),
  29. GPMI_WRN = PINID(0, 25),
  30. GPMI_ALE = PINID(0, 26),
  31. GPMI_CLE = PINID(0, 27),
  32. GPMI_RESETN = PINID(0, 28),
  33. LCD_D00 = PINID(1, 0),
  34. LCD_D01 = PINID(1, 1),
  35. LCD_D02 = PINID(1, 2),
  36. LCD_D03 = PINID(1, 3),
  37. LCD_D04 = PINID(1, 4),
  38. LCD_D05 = PINID(1, 5),
  39. LCD_D06 = PINID(1, 6),
  40. LCD_D07 = PINID(1, 7),
  41. LCD_D08 = PINID(1, 8),
  42. LCD_D09 = PINID(1, 9),
  43. LCD_D10 = PINID(1, 10),
  44. LCD_D11 = PINID(1, 11),
  45. LCD_D12 = PINID(1, 12),
  46. LCD_D13 = PINID(1, 13),
  47. LCD_D14 = PINID(1, 14),
  48. LCD_D15 = PINID(1, 15),
  49. LCD_D16 = PINID(1, 16),
  50. LCD_D17 = PINID(1, 17),
  51. LCD_D18 = PINID(1, 18),
  52. LCD_D19 = PINID(1, 19),
  53. LCD_D20 = PINID(1, 20),
  54. LCD_D21 = PINID(1, 21),
  55. LCD_D22 = PINID(1, 22),
  56. LCD_D23 = PINID(1, 23),
  57. LCD_RD_E = PINID(1, 24),
  58. LCD_WR_RWN = PINID(1, 25),
  59. LCD_RS = PINID(1, 26),
  60. LCD_CS = PINID(1, 27),
  61. LCD_VSYNC = PINID(1, 28),
  62. LCD_HSYNC = PINID(1, 29),
  63. LCD_DOTCLK = PINID(1, 30),
  64. LCD_ENABLE = PINID(1, 31),
  65. SSP0_DATA0 = PINID(2, 0),
  66. SSP0_DATA1 = PINID(2, 1),
  67. SSP0_DATA2 = PINID(2, 2),
  68. SSP0_DATA3 = PINID(2, 3),
  69. SSP0_DATA4 = PINID(2, 4),
  70. SSP0_DATA5 = PINID(2, 5),
  71. SSP0_DATA6 = PINID(2, 6),
  72. SSP0_DATA7 = PINID(2, 7),
  73. SSP0_CMD = PINID(2, 8),
  74. SSP0_DETECT = PINID(2, 9),
  75. SSP0_SCK = PINID(2, 10),
  76. SSP1_SCK = PINID(2, 12),
  77. SSP1_CMD = PINID(2, 13),
  78. SSP1_DATA0 = PINID(2, 14),
  79. SSP1_DATA3 = PINID(2, 15),
  80. SSP2_SCK = PINID(2, 16),
  81. SSP2_MOSI = PINID(2, 17),
  82. SSP2_MISO = PINID(2, 18),
  83. SSP2_SS0 = PINID(2, 19),
  84. SSP2_SS1 = PINID(2, 20),
  85. SSP2_SS2 = PINID(2, 21),
  86. SSP3_SCK = PINID(2, 24),
  87. SSP3_MOSI = PINID(2, 25),
  88. SSP3_MISO = PINID(2, 26),
  89. SSP3_SS0 = PINID(2, 27),
  90. AUART0_RX = PINID(3, 0),
  91. AUART0_TX = PINID(3, 1),
  92. AUART0_CTS = PINID(3, 2),
  93. AUART0_RTS = PINID(3, 3),
  94. AUART1_RX = PINID(3, 4),
  95. AUART1_TX = PINID(3, 5),
  96. AUART1_CTS = PINID(3, 6),
  97. AUART1_RTS = PINID(3, 7),
  98. AUART2_RX = PINID(3, 8),
  99. AUART2_TX = PINID(3, 9),
  100. AUART2_CTS = PINID(3, 10),
  101. AUART2_RTS = PINID(3, 11),
  102. AUART3_RX = PINID(3, 12),
  103. AUART3_TX = PINID(3, 13),
  104. AUART3_CTS = PINID(3, 14),
  105. AUART3_RTS = PINID(3, 15),
  106. PWM0 = PINID(3, 16),
  107. PWM1 = PINID(3, 17),
  108. PWM2 = PINID(3, 18),
  109. SAIF0_MCLK = PINID(3, 20),
  110. SAIF0_LRCLK = PINID(3, 21),
  111. SAIF0_BITCLK = PINID(3, 22),
  112. SAIF0_SDATA0 = PINID(3, 23),
  113. I2C0_SCL = PINID(3, 24),
  114. I2C0_SDA = PINID(3, 25),
  115. SAIF1_SDATA0 = PINID(3, 26),
  116. SPDIF = PINID(3, 27),
  117. PWM3 = PINID(3, 28),
  118. PWM4 = PINID(3, 29),
  119. LCD_RESET = PINID(3, 30),
  120. ENET0_MDC = PINID(4, 0),
  121. ENET0_MDIO = PINID(4, 1),
  122. ENET0_RX_EN = PINID(4, 2),
  123. ENET0_RXD0 = PINID(4, 3),
  124. ENET0_RXD1 = PINID(4, 4),
  125. ENET0_TX_CLK = PINID(4, 5),
  126. ENET0_TX_EN = PINID(4, 6),
  127. ENET0_TXD0 = PINID(4, 7),
  128. ENET0_TXD1 = PINID(4, 8),
  129. ENET0_RXD2 = PINID(4, 9),
  130. ENET0_RXD3 = PINID(4, 10),
  131. ENET0_TXD2 = PINID(4, 11),
  132. ENET0_TXD3 = PINID(4, 12),
  133. ENET0_RX_CLK = PINID(4, 13),
  134. ENET0_COL = PINID(4, 14),
  135. ENET0_CRS = PINID(4, 15),
  136. ENET_CLK = PINID(4, 16),
  137. JTAG_RTCK = PINID(4, 20),
  138. EMI_D00 = PINID(5, 0),
  139. EMI_D01 = PINID(5, 1),
  140. EMI_D02 = PINID(5, 2),
  141. EMI_D03 = PINID(5, 3),
  142. EMI_D04 = PINID(5, 4),
  143. EMI_D05 = PINID(5, 5),
  144. EMI_D06 = PINID(5, 6),
  145. EMI_D07 = PINID(5, 7),
  146. EMI_D08 = PINID(5, 8),
  147. EMI_D09 = PINID(5, 9),
  148. EMI_D10 = PINID(5, 10),
  149. EMI_D11 = PINID(5, 11),
  150. EMI_D12 = PINID(5, 12),
  151. EMI_D13 = PINID(5, 13),
  152. EMI_D14 = PINID(5, 14),
  153. EMI_D15 = PINID(5, 15),
  154. EMI_ODT0 = PINID(5, 16),
  155. EMI_DQM0 = PINID(5, 17),
  156. EMI_ODT1 = PINID(5, 18),
  157. EMI_DQM1 = PINID(5, 19),
  158. EMI_DDR_OPEN_FB = PINID(5, 20),
  159. EMI_CLK = PINID(5, 21),
  160. EMI_DQS0 = PINID(5, 22),
  161. EMI_DQS1 = PINID(5, 23),
  162. EMI_DDR_OPEN = PINID(5, 26),
  163. EMI_A00 = PINID(6, 0),
  164. EMI_A01 = PINID(6, 1),
  165. EMI_A02 = PINID(6, 2),
  166. EMI_A03 = PINID(6, 3),
  167. EMI_A04 = PINID(6, 4),
  168. EMI_A05 = PINID(6, 5),
  169. EMI_A06 = PINID(6, 6),
  170. EMI_A07 = PINID(6, 7),
  171. EMI_A08 = PINID(6, 8),
  172. EMI_A09 = PINID(6, 9),
  173. EMI_A10 = PINID(6, 10),
  174. EMI_A11 = PINID(6, 11),
  175. EMI_A12 = PINID(6, 12),
  176. EMI_A13 = PINID(6, 13),
  177. EMI_A14 = PINID(6, 14),
  178. EMI_BA0 = PINID(6, 16),
  179. EMI_BA1 = PINID(6, 17),
  180. EMI_BA2 = PINID(6, 18),
  181. EMI_CASN = PINID(6, 19),
  182. EMI_RASN = PINID(6, 20),
  183. EMI_WEN = PINID(6, 21),
  184. EMI_CE0N = PINID(6, 22),
  185. EMI_CE1N = PINID(6, 23),
  186. EMI_CKE = PINID(6, 24),
  187. };
  188. static const struct pinctrl_pin_desc imx28_pins[] = {
  189. MXS_PINCTRL_PIN(GPMI_D00),
  190. MXS_PINCTRL_PIN(GPMI_D01),
  191. MXS_PINCTRL_PIN(GPMI_D02),
  192. MXS_PINCTRL_PIN(GPMI_D03),
  193. MXS_PINCTRL_PIN(GPMI_D04),
  194. MXS_PINCTRL_PIN(GPMI_D05),
  195. MXS_PINCTRL_PIN(GPMI_D06),
  196. MXS_PINCTRL_PIN(GPMI_D07),
  197. MXS_PINCTRL_PIN(GPMI_CE0N),
  198. MXS_PINCTRL_PIN(GPMI_CE1N),
  199. MXS_PINCTRL_PIN(GPMI_CE2N),
  200. MXS_PINCTRL_PIN(GPMI_CE3N),
  201. MXS_PINCTRL_PIN(GPMI_RDY0),
  202. MXS_PINCTRL_PIN(GPMI_RDY1),
  203. MXS_PINCTRL_PIN(GPMI_RDY2),
  204. MXS_PINCTRL_PIN(GPMI_RDY3),
  205. MXS_PINCTRL_PIN(GPMI_RDN),
  206. MXS_PINCTRL_PIN(GPMI_WRN),
  207. MXS_PINCTRL_PIN(GPMI_ALE),
  208. MXS_PINCTRL_PIN(GPMI_CLE),
  209. MXS_PINCTRL_PIN(GPMI_RESETN),
  210. MXS_PINCTRL_PIN(LCD_D00),
  211. MXS_PINCTRL_PIN(LCD_D01),
  212. MXS_PINCTRL_PIN(LCD_D02),
  213. MXS_PINCTRL_PIN(LCD_D03),
  214. MXS_PINCTRL_PIN(LCD_D04),
  215. MXS_PINCTRL_PIN(LCD_D05),
  216. MXS_PINCTRL_PIN(LCD_D06),
  217. MXS_PINCTRL_PIN(LCD_D07),
  218. MXS_PINCTRL_PIN(LCD_D08),
  219. MXS_PINCTRL_PIN(LCD_D09),
  220. MXS_PINCTRL_PIN(LCD_D10),
  221. MXS_PINCTRL_PIN(LCD_D11),
  222. MXS_PINCTRL_PIN(LCD_D12),
  223. MXS_PINCTRL_PIN(LCD_D13),
  224. MXS_PINCTRL_PIN(LCD_D14),
  225. MXS_PINCTRL_PIN(LCD_D15),
  226. MXS_PINCTRL_PIN(LCD_D16),
  227. MXS_PINCTRL_PIN(LCD_D17),
  228. MXS_PINCTRL_PIN(LCD_D18),
  229. MXS_PINCTRL_PIN(LCD_D19),
  230. MXS_PINCTRL_PIN(LCD_D20),
  231. MXS_PINCTRL_PIN(LCD_D21),
  232. MXS_PINCTRL_PIN(LCD_D22),
  233. MXS_PINCTRL_PIN(LCD_D23),
  234. MXS_PINCTRL_PIN(LCD_RD_E),
  235. MXS_PINCTRL_PIN(LCD_WR_RWN),
  236. MXS_PINCTRL_PIN(LCD_RS),
  237. MXS_PINCTRL_PIN(LCD_CS),
  238. MXS_PINCTRL_PIN(LCD_VSYNC),
  239. MXS_PINCTRL_PIN(LCD_HSYNC),
  240. MXS_PINCTRL_PIN(LCD_DOTCLK),
  241. MXS_PINCTRL_PIN(LCD_ENABLE),
  242. MXS_PINCTRL_PIN(SSP0_DATA0),
  243. MXS_PINCTRL_PIN(SSP0_DATA1),
  244. MXS_PINCTRL_PIN(SSP0_DATA2),
  245. MXS_PINCTRL_PIN(SSP0_DATA3),
  246. MXS_PINCTRL_PIN(SSP0_DATA4),
  247. MXS_PINCTRL_PIN(SSP0_DATA5),
  248. MXS_PINCTRL_PIN(SSP0_DATA6),
  249. MXS_PINCTRL_PIN(SSP0_DATA7),
  250. MXS_PINCTRL_PIN(SSP0_CMD),
  251. MXS_PINCTRL_PIN(SSP0_DETECT),
  252. MXS_PINCTRL_PIN(SSP0_SCK),
  253. MXS_PINCTRL_PIN(SSP1_SCK),
  254. MXS_PINCTRL_PIN(SSP1_CMD),
  255. MXS_PINCTRL_PIN(SSP1_DATA0),
  256. MXS_PINCTRL_PIN(SSP1_DATA3),
  257. MXS_PINCTRL_PIN(SSP2_SCK),
  258. MXS_PINCTRL_PIN(SSP2_MOSI),
  259. MXS_PINCTRL_PIN(SSP2_MISO),
  260. MXS_PINCTRL_PIN(SSP2_SS0),
  261. MXS_PINCTRL_PIN(SSP2_SS1),
  262. MXS_PINCTRL_PIN(SSP2_SS2),
  263. MXS_PINCTRL_PIN(SSP3_SCK),
  264. MXS_PINCTRL_PIN(SSP3_MOSI),
  265. MXS_PINCTRL_PIN(SSP3_MISO),
  266. MXS_PINCTRL_PIN(SSP3_SS0),
  267. MXS_PINCTRL_PIN(AUART0_RX),
  268. MXS_PINCTRL_PIN(AUART0_TX),
  269. MXS_PINCTRL_PIN(AUART0_CTS),
  270. MXS_PINCTRL_PIN(AUART0_RTS),
  271. MXS_PINCTRL_PIN(AUART1_RX),
  272. MXS_PINCTRL_PIN(AUART1_TX),
  273. MXS_PINCTRL_PIN(AUART1_CTS),
  274. MXS_PINCTRL_PIN(AUART1_RTS),
  275. MXS_PINCTRL_PIN(AUART2_RX),
  276. MXS_PINCTRL_PIN(AUART2_TX),
  277. MXS_PINCTRL_PIN(AUART2_CTS),
  278. MXS_PINCTRL_PIN(AUART2_RTS),
  279. MXS_PINCTRL_PIN(AUART3_RX),
  280. MXS_PINCTRL_PIN(AUART3_TX),
  281. MXS_PINCTRL_PIN(AUART3_CTS),
  282. MXS_PINCTRL_PIN(AUART3_RTS),
  283. MXS_PINCTRL_PIN(PWM0),
  284. MXS_PINCTRL_PIN(PWM1),
  285. MXS_PINCTRL_PIN(PWM2),
  286. MXS_PINCTRL_PIN(SAIF0_MCLK),
  287. MXS_PINCTRL_PIN(SAIF0_LRCLK),
  288. MXS_PINCTRL_PIN(SAIF0_BITCLK),
  289. MXS_PINCTRL_PIN(SAIF0_SDATA0),
  290. MXS_PINCTRL_PIN(I2C0_SCL),
  291. MXS_PINCTRL_PIN(I2C0_SDA),
  292. MXS_PINCTRL_PIN(SAIF1_SDATA0),
  293. MXS_PINCTRL_PIN(SPDIF),
  294. MXS_PINCTRL_PIN(PWM3),
  295. MXS_PINCTRL_PIN(PWM4),
  296. MXS_PINCTRL_PIN(LCD_RESET),
  297. MXS_PINCTRL_PIN(ENET0_MDC),
  298. MXS_PINCTRL_PIN(ENET0_MDIO),
  299. MXS_PINCTRL_PIN(ENET0_RX_EN),
  300. MXS_PINCTRL_PIN(ENET0_RXD0),
  301. MXS_PINCTRL_PIN(ENET0_RXD1),
  302. MXS_PINCTRL_PIN(ENET0_TX_CLK),
  303. MXS_PINCTRL_PIN(ENET0_TX_EN),
  304. MXS_PINCTRL_PIN(ENET0_TXD0),
  305. MXS_PINCTRL_PIN(ENET0_TXD1),
  306. MXS_PINCTRL_PIN(ENET0_RXD2),
  307. MXS_PINCTRL_PIN(ENET0_RXD3),
  308. MXS_PINCTRL_PIN(ENET0_TXD2),
  309. MXS_PINCTRL_PIN(ENET0_TXD3),
  310. MXS_PINCTRL_PIN(ENET0_RX_CLK),
  311. MXS_PINCTRL_PIN(ENET0_COL),
  312. MXS_PINCTRL_PIN(ENET0_CRS),
  313. MXS_PINCTRL_PIN(ENET_CLK),
  314. MXS_PINCTRL_PIN(JTAG_RTCK),
  315. MXS_PINCTRL_PIN(EMI_D00),
  316. MXS_PINCTRL_PIN(EMI_D01),
  317. MXS_PINCTRL_PIN(EMI_D02),
  318. MXS_PINCTRL_PIN(EMI_D03),
  319. MXS_PINCTRL_PIN(EMI_D04),
  320. MXS_PINCTRL_PIN(EMI_D05),
  321. MXS_PINCTRL_PIN(EMI_D06),
  322. MXS_PINCTRL_PIN(EMI_D07),
  323. MXS_PINCTRL_PIN(EMI_D08),
  324. MXS_PINCTRL_PIN(EMI_D09),
  325. MXS_PINCTRL_PIN(EMI_D10),
  326. MXS_PINCTRL_PIN(EMI_D11),
  327. MXS_PINCTRL_PIN(EMI_D12),
  328. MXS_PINCTRL_PIN(EMI_D13),
  329. MXS_PINCTRL_PIN(EMI_D14),
  330. MXS_PINCTRL_PIN(EMI_D15),
  331. MXS_PINCTRL_PIN(EMI_ODT0),
  332. MXS_PINCTRL_PIN(EMI_DQM0),
  333. MXS_PINCTRL_PIN(EMI_ODT1),
  334. MXS_PINCTRL_PIN(EMI_DQM1),
  335. MXS_PINCTRL_PIN(EMI_DDR_OPEN_FB),
  336. MXS_PINCTRL_PIN(EMI_CLK),
  337. MXS_PINCTRL_PIN(EMI_DQS0),
  338. MXS_PINCTRL_PIN(EMI_DQS1),
  339. MXS_PINCTRL_PIN(EMI_DDR_OPEN),
  340. MXS_PINCTRL_PIN(EMI_A00),
  341. MXS_PINCTRL_PIN(EMI_A01),
  342. MXS_PINCTRL_PIN(EMI_A02),
  343. MXS_PINCTRL_PIN(EMI_A03),
  344. MXS_PINCTRL_PIN(EMI_A04),
  345. MXS_PINCTRL_PIN(EMI_A05),
  346. MXS_PINCTRL_PIN(EMI_A06),
  347. MXS_PINCTRL_PIN(EMI_A07),
  348. MXS_PINCTRL_PIN(EMI_A08),
  349. MXS_PINCTRL_PIN(EMI_A09),
  350. MXS_PINCTRL_PIN(EMI_A10),
  351. MXS_PINCTRL_PIN(EMI_A11),
  352. MXS_PINCTRL_PIN(EMI_A12),
  353. MXS_PINCTRL_PIN(EMI_A13),
  354. MXS_PINCTRL_PIN(EMI_A14),
  355. MXS_PINCTRL_PIN(EMI_BA0),
  356. MXS_PINCTRL_PIN(EMI_BA1),
  357. MXS_PINCTRL_PIN(EMI_BA2),
  358. MXS_PINCTRL_PIN(EMI_CASN),
  359. MXS_PINCTRL_PIN(EMI_RASN),
  360. MXS_PINCTRL_PIN(EMI_WEN),
  361. MXS_PINCTRL_PIN(EMI_CE0N),
  362. MXS_PINCTRL_PIN(EMI_CE1N),
  363. MXS_PINCTRL_PIN(EMI_CKE),
  364. };
  365. static const struct mxs_regs imx28_regs = {
  366. .muxsel = 0x100,
  367. .drive = 0x300,
  368. .pull = 0x600,
  369. };
  370. static struct mxs_pinctrl_soc_data imx28_pinctrl_data = {
  371. .regs = &imx28_regs,
  372. .pins = imx28_pins,
  373. .npins = ARRAY_SIZE(imx28_pins),
  374. };
  375. static int imx28_pinctrl_probe(struct platform_device *pdev)
  376. {
  377. return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
  378. }
  379. static const struct of_device_id imx28_pinctrl_of_match[] = {
  380. { .compatible = "fsl,imx28-pinctrl", },
  381. { /* sentinel */ }
  382. };
  383. static struct platform_driver imx28_pinctrl_driver = {
  384. .driver = {
  385. .name = "imx28-pinctrl",
  386. .suppress_bind_attrs = true,
  387. .of_match_table = imx28_pinctrl_of_match,
  388. },
  389. .probe = imx28_pinctrl_probe,
  390. };
  391. static int __init imx28_pinctrl_init(void)
  392. {
  393. return platform_driver_register(&imx28_pinctrl_driver);
  394. }
  395. postcore_initcall(imx28_pinctrl_init);