pinctrl-imx21.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // i.MX21 pinctrl driver based on imx pinmux core
  4. //
  5. // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
  6. #include <linux/init.h>
  7. #include <linux/of.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pinctrl/pinctrl.h>
  10. #include "pinctrl-imx1.h"
  11. #define PAD_ID(port, pin) ((port) * 32 + (pin))
  12. #define PA 0
  13. #define PB 1
  14. #define PC 2
  15. #define PD 3
  16. #define PE 4
  17. #define PF 5
  18. enum imx21_pads {
  19. MX21_PAD_LSCLK = PAD_ID(PA, 5),
  20. MX21_PAD_LD0 = PAD_ID(PA, 6),
  21. MX21_PAD_LD1 = PAD_ID(PA, 7),
  22. MX21_PAD_LD2 = PAD_ID(PA, 8),
  23. MX21_PAD_LD3 = PAD_ID(PA, 9),
  24. MX21_PAD_LD4 = PAD_ID(PA, 10),
  25. MX21_PAD_LD5 = PAD_ID(PA, 11),
  26. MX21_PAD_LD6 = PAD_ID(PA, 12),
  27. MX21_PAD_LD7 = PAD_ID(PA, 13),
  28. MX21_PAD_LD8 = PAD_ID(PA, 14),
  29. MX21_PAD_LD9 = PAD_ID(PA, 15),
  30. MX21_PAD_LD10 = PAD_ID(PA, 16),
  31. MX21_PAD_LD11 = PAD_ID(PA, 17),
  32. MX21_PAD_LD12 = PAD_ID(PA, 18),
  33. MX21_PAD_LD13 = PAD_ID(PA, 19),
  34. MX21_PAD_LD14 = PAD_ID(PA, 20),
  35. MX21_PAD_LD15 = PAD_ID(PA, 21),
  36. MX21_PAD_LD16 = PAD_ID(PA, 22),
  37. MX21_PAD_LD17 = PAD_ID(PA, 23),
  38. MX21_PAD_REV = PAD_ID(PA, 24),
  39. MX21_PAD_CLS = PAD_ID(PA, 25),
  40. MX21_PAD_PS = PAD_ID(PA, 26),
  41. MX21_PAD_SPL_SPR = PAD_ID(PA, 27),
  42. MX21_PAD_HSYNC = PAD_ID(PA, 28),
  43. MX21_PAD_VSYNC = PAD_ID(PA, 29),
  44. MX21_PAD_CONTRAST = PAD_ID(PA, 30),
  45. MX21_PAD_OE_ACD = PAD_ID(PA, 31),
  46. MX21_PAD_SD2_D0 = PAD_ID(PB, 4),
  47. MX21_PAD_SD2_D1 = PAD_ID(PB, 5),
  48. MX21_PAD_SD2_D2 = PAD_ID(PB, 6),
  49. MX21_PAD_SD2_D3 = PAD_ID(PB, 7),
  50. MX21_PAD_SD2_CMD = PAD_ID(PB, 8),
  51. MX21_PAD_SD2_CLK = PAD_ID(PB, 9),
  52. MX21_PAD_CSI_D0 = PAD_ID(PB, 10),
  53. MX21_PAD_CSI_D1 = PAD_ID(PB, 11),
  54. MX21_PAD_CSI_D2 = PAD_ID(PB, 12),
  55. MX21_PAD_CSI_D3 = PAD_ID(PB, 13),
  56. MX21_PAD_CSI_D4 = PAD_ID(PB, 14),
  57. MX21_PAD_CSI_MCLK = PAD_ID(PB, 15),
  58. MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
  59. MX21_PAD_CSI_D5 = PAD_ID(PB, 17),
  60. MX21_PAD_CSI_D6 = PAD_ID(PB, 18),
  61. MX21_PAD_CSI_D7 = PAD_ID(PB, 19),
  62. MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20),
  63. MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21),
  64. MX21_PAD_USB_BYP = PAD_ID(PB, 22),
  65. MX21_PAD_USB_PWR = PAD_ID(PB, 23),
  66. MX21_PAD_USB_OC = PAD_ID(PB, 24),
  67. MX21_PAD_USBH_ON = PAD_ID(PB, 25),
  68. MX21_PAD_USBH1_FS = PAD_ID(PB, 26),
  69. MX21_PAD_USBH1_OE = PAD_ID(PB, 27),
  70. MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28),
  71. MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29),
  72. MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30),
  73. MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31),
  74. MX21_PAD_USBG_SDA = PAD_ID(PC, 5),
  75. MX21_PAD_USBG_SCL = PAD_ID(PC, 6),
  76. MX21_PAD_USBG_ON = PAD_ID(PC, 7),
  77. MX21_PAD_USBG_FS = PAD_ID(PC, 8),
  78. MX21_PAD_USBG_OE = PAD_ID(PC, 9),
  79. MX21_PAD_USBG_TXDM = PAD_ID(PC, 10),
  80. MX21_PAD_USBG_TXDP = PAD_ID(PC, 11),
  81. MX21_PAD_USBG_RXDM = PAD_ID(PC, 12),
  82. MX21_PAD_USBG_RXDP = PAD_ID(PC, 13),
  83. MX21_PAD_TOUT = PAD_ID(PC, 14),
  84. MX21_PAD_TIN = PAD_ID(PC, 15),
  85. MX21_PAD_SAP_FS = PAD_ID(PC, 16),
  86. MX21_PAD_SAP_RXD = PAD_ID(PC, 17),
  87. MX21_PAD_SAP_TXD = PAD_ID(PC, 18),
  88. MX21_PAD_SAP_CLK = PAD_ID(PC, 19),
  89. MX21_PAD_SSI1_FS = PAD_ID(PC, 20),
  90. MX21_PAD_SSI1_RXD = PAD_ID(PC, 21),
  91. MX21_PAD_SSI1_TXD = PAD_ID(PC, 22),
  92. MX21_PAD_SSI1_CLK = PAD_ID(PC, 23),
  93. MX21_PAD_SSI2_FS = PAD_ID(PC, 24),
  94. MX21_PAD_SSI2_RXD = PAD_ID(PC, 25),
  95. MX21_PAD_SSI2_TXD = PAD_ID(PC, 26),
  96. MX21_PAD_SSI2_CLK = PAD_ID(PC, 27),
  97. MX21_PAD_SSI3_FS = PAD_ID(PC, 28),
  98. MX21_PAD_SSI3_RXD = PAD_ID(PC, 29),
  99. MX21_PAD_SSI3_TXD = PAD_ID(PC, 30),
  100. MX21_PAD_SSI3_CLK = PAD_ID(PC, 31),
  101. MX21_PAD_I2C_DATA = PAD_ID(PD, 17),
  102. MX21_PAD_I2C_CLK = PAD_ID(PD, 18),
  103. MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
  104. MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
  105. MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
  106. MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
  107. MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23),
  108. MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
  109. MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25),
  110. MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
  111. MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
  112. MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
  113. MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
  114. MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30),
  115. MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
  116. MX21_PAD_TEST_WB2 = PAD_ID(PE, 0),
  117. MX21_PAD_TEST_WB1 = PAD_ID(PE, 1),
  118. MX21_PAD_TEST_WB0 = PAD_ID(PE, 2),
  119. MX21_PAD_UART2_CTS = PAD_ID(PE, 3),
  120. MX21_PAD_UART2_RTS = PAD_ID(PE, 4),
  121. MX21_PAD_PWMO = PAD_ID(PE, 5),
  122. MX21_PAD_UART2_TXD = PAD_ID(PE, 6),
  123. MX21_PAD_UART2_RXD = PAD_ID(PE, 7),
  124. MX21_PAD_UART3_TXD = PAD_ID(PE, 8),
  125. MX21_PAD_UART3_RXD = PAD_ID(PE, 9),
  126. MX21_PAD_UART3_CTS = PAD_ID(PE, 10),
  127. MX21_PAD_UART3_RTS = PAD_ID(PE, 11),
  128. MX21_PAD_UART1_TXD = PAD_ID(PE, 12),
  129. MX21_PAD_UART1_RXD = PAD_ID(PE, 13),
  130. MX21_PAD_UART1_CTS = PAD_ID(PE, 14),
  131. MX21_PAD_UART1_RTS = PAD_ID(PE, 15),
  132. MX21_PAD_RTCK = PAD_ID(PE, 16),
  133. MX21_PAD_RESET_OUT = PAD_ID(PE, 17),
  134. MX21_PAD_SD1_D0 = PAD_ID(PE, 18),
  135. MX21_PAD_SD1_D1 = PAD_ID(PE, 19),
  136. MX21_PAD_SD1_D2 = PAD_ID(PE, 20),
  137. MX21_PAD_SD1_D3 = PAD_ID(PE, 21),
  138. MX21_PAD_SD1_CMD = PAD_ID(PE, 22),
  139. MX21_PAD_SD1_CLK = PAD_ID(PE, 23),
  140. MX21_PAD_NFRB = PAD_ID(PF, 0),
  141. MX21_PAD_NFCE = PAD_ID(PF, 1),
  142. MX21_PAD_NFWP = PAD_ID(PF, 2),
  143. MX21_PAD_NFCLE = PAD_ID(PF, 3),
  144. MX21_PAD_NFALE = PAD_ID(PF, 4),
  145. MX21_PAD_NFRE = PAD_ID(PF, 5),
  146. MX21_PAD_NFWE = PAD_ID(PF, 6),
  147. MX21_PAD_NFIO0 = PAD_ID(PF, 7),
  148. MX21_PAD_NFIO1 = PAD_ID(PF, 8),
  149. MX21_PAD_NFIO2 = PAD_ID(PF, 9),
  150. MX21_PAD_NFIO3 = PAD_ID(PF, 10),
  151. MX21_PAD_NFIO4 = PAD_ID(PF, 11),
  152. MX21_PAD_NFIO5 = PAD_ID(PF, 12),
  153. MX21_PAD_NFIO6 = PAD_ID(PF, 13),
  154. MX21_PAD_NFIO7 = PAD_ID(PF, 14),
  155. MX21_PAD_CLKO = PAD_ID(PF, 15),
  156. MX21_PAD_RESERVED = PAD_ID(PF, 16),
  157. MX21_PAD_CS4 = PAD_ID(PF, 21),
  158. MX21_PAD_CS5 = PAD_ID(PF, 22),
  159. };
  160. /* Pad names for the pinmux subsystem */
  161. static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
  162. IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
  163. IMX_PINCTRL_PIN(MX21_PAD_LD0),
  164. IMX_PINCTRL_PIN(MX21_PAD_LD1),
  165. IMX_PINCTRL_PIN(MX21_PAD_LD2),
  166. IMX_PINCTRL_PIN(MX21_PAD_LD3),
  167. IMX_PINCTRL_PIN(MX21_PAD_LD4),
  168. IMX_PINCTRL_PIN(MX21_PAD_LD5),
  169. IMX_PINCTRL_PIN(MX21_PAD_LD6),
  170. IMX_PINCTRL_PIN(MX21_PAD_LD7),
  171. IMX_PINCTRL_PIN(MX21_PAD_LD8),
  172. IMX_PINCTRL_PIN(MX21_PAD_LD9),
  173. IMX_PINCTRL_PIN(MX21_PAD_LD10),
  174. IMX_PINCTRL_PIN(MX21_PAD_LD11),
  175. IMX_PINCTRL_PIN(MX21_PAD_LD12),
  176. IMX_PINCTRL_PIN(MX21_PAD_LD13),
  177. IMX_PINCTRL_PIN(MX21_PAD_LD14),
  178. IMX_PINCTRL_PIN(MX21_PAD_LD15),
  179. IMX_PINCTRL_PIN(MX21_PAD_LD16),
  180. IMX_PINCTRL_PIN(MX21_PAD_LD17),
  181. IMX_PINCTRL_PIN(MX21_PAD_REV),
  182. IMX_PINCTRL_PIN(MX21_PAD_CLS),
  183. IMX_PINCTRL_PIN(MX21_PAD_PS),
  184. IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
  185. IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
  186. IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
  187. IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
  188. IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
  189. IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
  190. IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
  191. IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
  192. IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
  193. IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
  194. IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
  195. IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
  196. IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
  197. IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
  198. IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
  199. IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
  200. IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
  201. IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
  202. IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
  203. IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
  204. IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
  205. IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
  206. IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
  207. IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
  208. IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
  209. IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
  210. IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
  211. IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
  212. IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
  213. IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
  214. IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
  215. IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
  216. IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
  217. IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
  218. IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
  219. IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
  220. IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
  221. IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
  222. IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
  223. IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
  224. IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
  225. IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
  226. IMX_PINCTRL_PIN(MX21_PAD_TOUT),
  227. IMX_PINCTRL_PIN(MX21_PAD_TIN),
  228. IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
  229. IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
  230. IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
  231. IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
  232. IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
  233. IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
  234. IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
  235. IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
  236. IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
  237. IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
  238. IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
  239. IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
  240. IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
  241. IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
  242. IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
  243. IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
  244. IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
  245. IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
  246. IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
  247. IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
  248. IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
  249. IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
  250. IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
  251. IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
  252. IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
  253. IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
  254. IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
  255. IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
  256. IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
  257. IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
  258. IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
  259. IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
  260. IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
  261. IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
  262. IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
  263. IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
  264. IMX_PINCTRL_PIN(MX21_PAD_PWMO),
  265. IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
  266. IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
  267. IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
  268. IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
  269. IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
  270. IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
  271. IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
  272. IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
  273. IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
  274. IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
  275. IMX_PINCTRL_PIN(MX21_PAD_RTCK),
  276. IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
  277. IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
  278. IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
  279. IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
  280. IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
  281. IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
  282. IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
  283. IMX_PINCTRL_PIN(MX21_PAD_NFRB),
  284. IMX_PINCTRL_PIN(MX21_PAD_NFCE),
  285. IMX_PINCTRL_PIN(MX21_PAD_NFWP),
  286. IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
  287. IMX_PINCTRL_PIN(MX21_PAD_NFALE),
  288. IMX_PINCTRL_PIN(MX21_PAD_NFRE),
  289. IMX_PINCTRL_PIN(MX21_PAD_NFWE),
  290. IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
  291. IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
  292. IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
  293. IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
  294. IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
  295. IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
  296. IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
  297. IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
  298. IMX_PINCTRL_PIN(MX21_PAD_CLKO),
  299. IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
  300. IMX_PINCTRL_PIN(MX21_PAD_CS4),
  301. IMX_PINCTRL_PIN(MX21_PAD_CS5),
  302. };
  303. static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
  304. .pins = imx21_pinctrl_pads,
  305. .npins = ARRAY_SIZE(imx21_pinctrl_pads),
  306. };
  307. static int __init imx21_pinctrl_probe(struct platform_device *pdev)
  308. {
  309. return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
  310. }
  311. static const struct of_device_id imx21_pinctrl_of_match[] = {
  312. { .compatible = "fsl,imx21-iomuxc", },
  313. { }
  314. };
  315. static struct platform_driver imx21_pinctrl_driver = {
  316. .driver = {
  317. .name = "imx21-pinctrl",
  318. .of_match_table = imx21_pinctrl_of_match,
  319. },
  320. };
  321. builtin_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);