pinctrl-imx1.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // i.MX1 pinctrl driver based on imx pinmux core
  4. //
  5. // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
  6. #include <linux/init.h>
  7. #include <linux/of.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pinctrl/pinctrl.h>
  10. #include "pinctrl-imx1.h"
  11. #define PAD_ID(port, pin) ((port) * 32 + (pin))
  12. #define PA 0
  13. #define PB 1
  14. #define PC 2
  15. #define PD 3
  16. enum imx1_pads {
  17. MX1_PAD_A24 = PAD_ID(PA, 0),
  18. MX1_PAD_TIN = PAD_ID(PA, 1),
  19. MX1_PAD_PWMO = PAD_ID(PA, 2),
  20. MX1_PAD_CSI_MCLK = PAD_ID(PA, 3),
  21. MX1_PAD_CSI_D0 = PAD_ID(PA, 4),
  22. MX1_PAD_CSI_D1 = PAD_ID(PA, 5),
  23. MX1_PAD_CSI_D2 = PAD_ID(PA, 6),
  24. MX1_PAD_CSI_D3 = PAD_ID(PA, 7),
  25. MX1_PAD_CSI_D4 = PAD_ID(PA, 8),
  26. MX1_PAD_CSI_D5 = PAD_ID(PA, 9),
  27. MX1_PAD_CSI_D6 = PAD_ID(PA, 10),
  28. MX1_PAD_CSI_D7 = PAD_ID(PA, 11),
  29. MX1_PAD_CSI_VSYNC = PAD_ID(PA, 12),
  30. MX1_PAD_CSI_HSYNC = PAD_ID(PA, 13),
  31. MX1_PAD_CSI_PIXCLK = PAD_ID(PA, 14),
  32. MX1_PAD_I2C_SDA = PAD_ID(PA, 15),
  33. MX1_PAD_I2C_SCL = PAD_ID(PA, 16),
  34. MX1_PAD_DTACK = PAD_ID(PA, 17),
  35. MX1_PAD_BCLK = PAD_ID(PA, 18),
  36. MX1_PAD_LBA = PAD_ID(PA, 19),
  37. MX1_PAD_ECB = PAD_ID(PA, 20),
  38. MX1_PAD_A0 = PAD_ID(PA, 21),
  39. MX1_PAD_CS4 = PAD_ID(PA, 22),
  40. MX1_PAD_CS5 = PAD_ID(PA, 23),
  41. MX1_PAD_A16 = PAD_ID(PA, 24),
  42. MX1_PAD_A17 = PAD_ID(PA, 25),
  43. MX1_PAD_A18 = PAD_ID(PA, 26),
  44. MX1_PAD_A19 = PAD_ID(PA, 27),
  45. MX1_PAD_A20 = PAD_ID(PA, 28),
  46. MX1_PAD_A21 = PAD_ID(PA, 29),
  47. MX1_PAD_A22 = PAD_ID(PA, 30),
  48. MX1_PAD_A23 = PAD_ID(PA, 31),
  49. MX1_PAD_SD_DAT0 = PAD_ID(PB, 8),
  50. MX1_PAD_SD_DAT1 = PAD_ID(PB, 9),
  51. MX1_PAD_SD_DAT2 = PAD_ID(PB, 10),
  52. MX1_PAD_SD_DAT3 = PAD_ID(PB, 11),
  53. MX1_PAD_SD_SCLK = PAD_ID(PB, 12),
  54. MX1_PAD_SD_CMD = PAD_ID(PB, 13),
  55. MX1_PAD_SIM_SVEN = PAD_ID(PB, 14),
  56. MX1_PAD_SIM_PD = PAD_ID(PB, 15),
  57. MX1_PAD_SIM_TX = PAD_ID(PB, 16),
  58. MX1_PAD_SIM_RX = PAD_ID(PB, 17),
  59. MX1_PAD_SIM_RST = PAD_ID(PB, 18),
  60. MX1_PAD_SIM_CLK = PAD_ID(PB, 19),
  61. MX1_PAD_USBD_AFE = PAD_ID(PB, 20),
  62. MX1_PAD_USBD_OE = PAD_ID(PB, 21),
  63. MX1_PAD_USBD_RCV = PAD_ID(PB, 22),
  64. MX1_PAD_USBD_SUSPND = PAD_ID(PB, 23),
  65. MX1_PAD_USBD_VP = PAD_ID(PB, 24),
  66. MX1_PAD_USBD_VM = PAD_ID(PB, 25),
  67. MX1_PAD_USBD_VPO = PAD_ID(PB, 26),
  68. MX1_PAD_USBD_VMO = PAD_ID(PB, 27),
  69. MX1_PAD_UART2_CTS = PAD_ID(PB, 28),
  70. MX1_PAD_UART2_RTS = PAD_ID(PB, 29),
  71. MX1_PAD_UART2_TXD = PAD_ID(PB, 30),
  72. MX1_PAD_UART2_RXD = PAD_ID(PB, 31),
  73. MX1_PAD_SSI_RXFS = PAD_ID(PC, 3),
  74. MX1_PAD_SSI_RXCLK = PAD_ID(PC, 4),
  75. MX1_PAD_SSI_RXDAT = PAD_ID(PC, 5),
  76. MX1_PAD_SSI_TXDAT = PAD_ID(PC, 6),
  77. MX1_PAD_SSI_TXFS = PAD_ID(PC, 7),
  78. MX1_PAD_SSI_TXCLK = PAD_ID(PC, 8),
  79. MX1_PAD_UART1_CTS = PAD_ID(PC, 9),
  80. MX1_PAD_UART1_RTS = PAD_ID(PC, 10),
  81. MX1_PAD_UART1_TXD = PAD_ID(PC, 11),
  82. MX1_PAD_UART1_RXD = PAD_ID(PC, 12),
  83. MX1_PAD_SPI1_RDY = PAD_ID(PC, 13),
  84. MX1_PAD_SPI1_SCLK = PAD_ID(PC, 14),
  85. MX1_PAD_SPI1_SS = PAD_ID(PC, 15),
  86. MX1_PAD_SPI1_MISO = PAD_ID(PC, 16),
  87. MX1_PAD_SPI1_MOSI = PAD_ID(PC, 17),
  88. MX1_PAD_BT13 = PAD_ID(PC, 19),
  89. MX1_PAD_BT12 = PAD_ID(PC, 20),
  90. MX1_PAD_BT11 = PAD_ID(PC, 21),
  91. MX1_PAD_BT10 = PAD_ID(PC, 22),
  92. MX1_PAD_BT9 = PAD_ID(PC, 23),
  93. MX1_PAD_BT8 = PAD_ID(PC, 24),
  94. MX1_PAD_BT7 = PAD_ID(PC, 25),
  95. MX1_PAD_BT6 = PAD_ID(PC, 26),
  96. MX1_PAD_BT5 = PAD_ID(PC, 27),
  97. MX1_PAD_BT4 = PAD_ID(PC, 28),
  98. MX1_PAD_BT3 = PAD_ID(PC, 29),
  99. MX1_PAD_BT2 = PAD_ID(PC, 30),
  100. MX1_PAD_BT1 = PAD_ID(PC, 31),
  101. MX1_PAD_LSCLK = PAD_ID(PD, 6),
  102. MX1_PAD_REV = PAD_ID(PD, 7),
  103. MX1_PAD_CLS = PAD_ID(PD, 8),
  104. MX1_PAD_PS = PAD_ID(PD, 9),
  105. MX1_PAD_SPL_SPR = PAD_ID(PD, 10),
  106. MX1_PAD_CONTRAST = PAD_ID(PD, 11),
  107. MX1_PAD_ACD_OE = PAD_ID(PD, 12),
  108. MX1_PAD_LP_HSYNC = PAD_ID(PD, 13),
  109. MX1_PAD_FLM_VSYNC = PAD_ID(PD, 14),
  110. MX1_PAD_LD0 = PAD_ID(PD, 15),
  111. MX1_PAD_LD1 = PAD_ID(PD, 16),
  112. MX1_PAD_LD2 = PAD_ID(PD, 17),
  113. MX1_PAD_LD3 = PAD_ID(PD, 18),
  114. MX1_PAD_LD4 = PAD_ID(PD, 19),
  115. MX1_PAD_LD5 = PAD_ID(PD, 20),
  116. MX1_PAD_LD6 = PAD_ID(PD, 21),
  117. MX1_PAD_LD7 = PAD_ID(PD, 22),
  118. MX1_PAD_LD8 = PAD_ID(PD, 23),
  119. MX1_PAD_LD9 = PAD_ID(PD, 24),
  120. MX1_PAD_LD10 = PAD_ID(PD, 25),
  121. MX1_PAD_LD11 = PAD_ID(PD, 26),
  122. MX1_PAD_LD12 = PAD_ID(PD, 27),
  123. MX1_PAD_LD13 = PAD_ID(PD, 28),
  124. MX1_PAD_LD14 = PAD_ID(PD, 29),
  125. MX1_PAD_LD15 = PAD_ID(PD, 30),
  126. MX1_PAD_TMR2OUT = PAD_ID(PD, 31),
  127. };
  128. /* Pad names for the pinmux subsystem */
  129. static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
  130. IMX_PINCTRL_PIN(MX1_PAD_A24),
  131. IMX_PINCTRL_PIN(MX1_PAD_TIN),
  132. IMX_PINCTRL_PIN(MX1_PAD_PWMO),
  133. IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
  134. IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
  135. IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
  136. IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
  137. IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
  138. IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
  139. IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
  140. IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
  141. IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
  142. IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
  143. IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
  144. IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
  145. IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
  146. IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
  147. IMX_PINCTRL_PIN(MX1_PAD_DTACK),
  148. IMX_PINCTRL_PIN(MX1_PAD_BCLK),
  149. IMX_PINCTRL_PIN(MX1_PAD_LBA),
  150. IMX_PINCTRL_PIN(MX1_PAD_ECB),
  151. IMX_PINCTRL_PIN(MX1_PAD_A0),
  152. IMX_PINCTRL_PIN(MX1_PAD_CS4),
  153. IMX_PINCTRL_PIN(MX1_PAD_CS5),
  154. IMX_PINCTRL_PIN(MX1_PAD_A16),
  155. IMX_PINCTRL_PIN(MX1_PAD_A17),
  156. IMX_PINCTRL_PIN(MX1_PAD_A18),
  157. IMX_PINCTRL_PIN(MX1_PAD_A19),
  158. IMX_PINCTRL_PIN(MX1_PAD_A20),
  159. IMX_PINCTRL_PIN(MX1_PAD_A21),
  160. IMX_PINCTRL_PIN(MX1_PAD_A22),
  161. IMX_PINCTRL_PIN(MX1_PAD_A23),
  162. IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
  163. IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
  164. IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
  165. IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
  166. IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
  167. IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
  168. IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
  169. IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
  170. IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
  171. IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
  172. IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
  173. IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
  174. IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
  175. IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
  176. IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
  177. IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
  178. IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
  179. IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
  180. IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
  181. IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
  182. IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
  183. IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
  184. IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
  185. IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
  186. IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
  187. IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
  188. IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
  189. IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
  190. IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
  191. IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
  192. IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
  193. IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
  194. IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
  195. IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
  196. IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
  197. IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
  198. IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
  199. IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
  200. IMX_PINCTRL_PIN(MX1_PAD_BT13),
  201. IMX_PINCTRL_PIN(MX1_PAD_BT12),
  202. IMX_PINCTRL_PIN(MX1_PAD_BT11),
  203. IMX_PINCTRL_PIN(MX1_PAD_BT10),
  204. IMX_PINCTRL_PIN(MX1_PAD_BT9),
  205. IMX_PINCTRL_PIN(MX1_PAD_BT8),
  206. IMX_PINCTRL_PIN(MX1_PAD_BT7),
  207. IMX_PINCTRL_PIN(MX1_PAD_BT6),
  208. IMX_PINCTRL_PIN(MX1_PAD_BT5),
  209. IMX_PINCTRL_PIN(MX1_PAD_BT4),
  210. IMX_PINCTRL_PIN(MX1_PAD_BT3),
  211. IMX_PINCTRL_PIN(MX1_PAD_BT2),
  212. IMX_PINCTRL_PIN(MX1_PAD_BT1),
  213. IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
  214. IMX_PINCTRL_PIN(MX1_PAD_REV),
  215. IMX_PINCTRL_PIN(MX1_PAD_CLS),
  216. IMX_PINCTRL_PIN(MX1_PAD_PS),
  217. IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
  218. IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
  219. IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
  220. IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
  221. IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
  222. IMX_PINCTRL_PIN(MX1_PAD_LD0),
  223. IMX_PINCTRL_PIN(MX1_PAD_LD1),
  224. IMX_PINCTRL_PIN(MX1_PAD_LD2),
  225. IMX_PINCTRL_PIN(MX1_PAD_LD3),
  226. IMX_PINCTRL_PIN(MX1_PAD_LD4),
  227. IMX_PINCTRL_PIN(MX1_PAD_LD5),
  228. IMX_PINCTRL_PIN(MX1_PAD_LD6),
  229. IMX_PINCTRL_PIN(MX1_PAD_LD7),
  230. IMX_PINCTRL_PIN(MX1_PAD_LD8),
  231. IMX_PINCTRL_PIN(MX1_PAD_LD9),
  232. IMX_PINCTRL_PIN(MX1_PAD_LD10),
  233. IMX_PINCTRL_PIN(MX1_PAD_LD11),
  234. IMX_PINCTRL_PIN(MX1_PAD_LD12),
  235. IMX_PINCTRL_PIN(MX1_PAD_LD13),
  236. IMX_PINCTRL_PIN(MX1_PAD_LD14),
  237. IMX_PINCTRL_PIN(MX1_PAD_LD15),
  238. IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
  239. };
  240. static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
  241. .pins = imx1_pinctrl_pads,
  242. .npins = ARRAY_SIZE(imx1_pinctrl_pads),
  243. };
  244. static int __init imx1_pinctrl_probe(struct platform_device *pdev)
  245. {
  246. return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
  247. }
  248. static const struct of_device_id imx1_pinctrl_of_match[] = {
  249. { .compatible = "fsl,imx1-iomuxc", },
  250. { }
  251. };
  252. static struct platform_driver imx1_pinctrl_driver = {
  253. .driver = {
  254. .name = "imx1-pinctrl",
  255. .of_match_table = imx1_pinctrl_of_match,
  256. },
  257. };
  258. builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);