pinctrl-imx1-core.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Core driver for the imx pin controller in imx1/21/27
  4. //
  5. // Copyright (C) 2013 Pengutronix
  6. // Author: Markus Pargmann <mpa@pengutronix.de>
  7. //
  8. // Based on pinctrl-imx.c:
  9. // Author: Dong Aisheng <dong.aisheng@linaro.org>
  10. // Copyright (C) 2012 Freescale Semiconductor, Inc.
  11. // Copyright (C) 2012 Linaro Ltd.
  12. #include <linux/bitops.h>
  13. #include <linux/err.h>
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <linux/of.h>
  17. #include <linux/of_device.h>
  18. #include <linux/pinctrl/machine.h>
  19. #include <linux/pinctrl/pinconf.h>
  20. #include <linux/pinctrl/pinctrl.h>
  21. #include <linux/pinctrl/pinmux.h>
  22. #include <linux/slab.h>
  23. #include "../core.h"
  24. #include "pinctrl-imx1.h"
  25. struct imx1_pinctrl {
  26. struct device *dev;
  27. struct pinctrl_dev *pctl;
  28. void __iomem *base;
  29. const struct imx1_pinctrl_soc_info *info;
  30. };
  31. /*
  32. * MX1 register offsets
  33. */
  34. #define MX1_DDIR 0x00
  35. #define MX1_OCR 0x04
  36. #define MX1_ICONFA 0x0c
  37. #define MX1_ICONFB 0x14
  38. #define MX1_GIUS 0x20
  39. #define MX1_GPR 0x38
  40. #define MX1_PUEN 0x40
  41. #define MX1_PORT_STRIDE 0x100
  42. /*
  43. * MUX_ID format defines
  44. */
  45. #define MX1_MUX_FUNCTION(val) (BIT(0) & val)
  46. #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
  47. #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
  48. #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
  49. #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
  50. #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
  51. /*
  52. * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
  53. * control registers are separated into function, output configuration, input
  54. * configuration A, input configuration B, GPIO in use and data direction.
  55. *
  56. * Those controls that are represented by 1 bit have a direct mapping between
  57. * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
  58. * are in the first register and the upper 16 pins in the second (next)
  59. * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
  60. */
  61. /*
  62. * Calculates the register offset from a pin_id
  63. */
  64. static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
  65. {
  66. unsigned int port = pin_id / 32;
  67. return ipctl->base + port * MX1_PORT_STRIDE;
  68. }
  69. /*
  70. * Write to a register with 2 bits per pin. The function will automatically
  71. * use the next register if the pin is managed in the second register.
  72. */
  73. static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
  74. u32 value, u32 reg_offset)
  75. {
  76. void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
  77. int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
  78. int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
  79. u32 old_val;
  80. u32 new_val;
  81. /* Use the next register if the pin's port pin number is >=16 */
  82. if (pin_id % 32 >= 16)
  83. reg += 0x04;
  84. dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
  85. reg, offset, value);
  86. /* Get current state of pins */
  87. old_val = readl(reg);
  88. old_val &= mask;
  89. new_val = value & 0x3; /* Make sure value is really 2 bit */
  90. new_val <<= offset;
  91. new_val |= old_val;/* Set new state for pin_id */
  92. writel(new_val, reg);
  93. }
  94. static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
  95. u32 value, u32 reg_offset)
  96. {
  97. void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
  98. int offset = pin_id % 32;
  99. int mask = ~BIT_MASK(offset);
  100. u32 old_val;
  101. u32 new_val;
  102. /* Get current state of pins */
  103. old_val = readl(reg);
  104. old_val &= mask;
  105. new_val = value & 0x1; /* Make sure value is really 1 bit */
  106. new_val <<= offset;
  107. new_val |= old_val;/* Set new state for pin_id */
  108. writel(new_val, reg);
  109. }
  110. static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
  111. u32 reg_offset)
  112. {
  113. void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
  114. int offset = (pin_id % 16) * 2;
  115. /* Use the next register if the pin's port pin number is >=16 */
  116. if (pin_id % 32 >= 16)
  117. reg += 0x04;
  118. return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
  119. }
  120. static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
  121. u32 reg_offset)
  122. {
  123. void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
  124. int offset = pin_id % 32;
  125. return !!(readl(reg) & BIT(offset));
  126. }
  127. static inline const struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
  128. const struct imx1_pinctrl_soc_info *info,
  129. const char *name)
  130. {
  131. const struct imx1_pin_group *grp = NULL;
  132. int i;
  133. for (i = 0; i < info->ngroups; i++) {
  134. if (!strcmp(info->groups[i].name, name)) {
  135. grp = &info->groups[i];
  136. break;
  137. }
  138. }
  139. return grp;
  140. }
  141. static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
  142. {
  143. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  144. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  145. return info->ngroups;
  146. }
  147. static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
  148. unsigned selector)
  149. {
  150. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  151. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  152. return info->groups[selector].name;
  153. }
  154. static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
  155. const unsigned int **pins,
  156. unsigned *npins)
  157. {
  158. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  159. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  160. if (selector >= info->ngroups)
  161. return -EINVAL;
  162. *pins = info->groups[selector].pin_ids;
  163. *npins = info->groups[selector].npins;
  164. return 0;
  165. }
  166. static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  167. unsigned offset)
  168. {
  169. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  170. seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
  171. imx1_read_bit(ipctl, offset, MX1_GIUS),
  172. imx1_read_bit(ipctl, offset, MX1_GPR),
  173. imx1_read_bit(ipctl, offset, MX1_DDIR),
  174. imx1_read_2bit(ipctl, offset, MX1_OCR),
  175. imx1_read_2bit(ipctl, offset, MX1_ICONFA),
  176. imx1_read_2bit(ipctl, offset, MX1_ICONFB));
  177. }
  178. static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
  179. struct device_node *np,
  180. struct pinctrl_map **map, unsigned *num_maps)
  181. {
  182. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  183. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  184. const struct imx1_pin_group *grp;
  185. struct pinctrl_map *new_map;
  186. struct device_node *parent;
  187. int map_num = 1;
  188. int i, j;
  189. /*
  190. * first find the group of this node and check if we need create
  191. * config maps for pins
  192. */
  193. grp = imx1_pinctrl_find_group_by_name(info, np->name);
  194. if (!grp) {
  195. dev_err(info->dev, "unable to find group for node %pOFn\n",
  196. np);
  197. return -EINVAL;
  198. }
  199. for (i = 0; i < grp->npins; i++)
  200. map_num++;
  201. new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
  202. GFP_KERNEL);
  203. if (!new_map)
  204. return -ENOMEM;
  205. *map = new_map;
  206. *num_maps = map_num;
  207. /* create mux map */
  208. parent = of_get_parent(np);
  209. if (!parent) {
  210. kfree(new_map);
  211. return -EINVAL;
  212. }
  213. new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
  214. new_map[0].data.mux.function = parent->name;
  215. new_map[0].data.mux.group = np->name;
  216. of_node_put(parent);
  217. /* create config map */
  218. new_map++;
  219. for (i = j = 0; i < grp->npins; i++) {
  220. new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
  221. new_map[j].data.configs.group_or_pin =
  222. pin_get_name(pctldev, grp->pins[i].pin_id);
  223. new_map[j].data.configs.configs = &grp->pins[i].config;
  224. new_map[j].data.configs.num_configs = 1;
  225. j++;
  226. }
  227. dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
  228. (*map)->data.mux.function, (*map)->data.mux.group, map_num);
  229. return 0;
  230. }
  231. static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
  232. struct pinctrl_map *map, unsigned num_maps)
  233. {
  234. kfree(map);
  235. }
  236. static const struct pinctrl_ops imx1_pctrl_ops = {
  237. .get_groups_count = imx1_get_groups_count,
  238. .get_group_name = imx1_get_group_name,
  239. .get_group_pins = imx1_get_group_pins,
  240. .pin_dbg_show = imx1_pin_dbg_show,
  241. .dt_node_to_map = imx1_dt_node_to_map,
  242. .dt_free_map = imx1_dt_free_map,
  243. };
  244. static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
  245. unsigned group)
  246. {
  247. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  248. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  249. const struct imx1_pin *pins;
  250. unsigned int npins;
  251. int i;
  252. /*
  253. * Configure the mux mode for each pin in the group for a specific
  254. * function.
  255. */
  256. pins = info->groups[group].pins;
  257. npins = info->groups[group].npins;
  258. WARN_ON(!pins || !npins);
  259. dev_dbg(ipctl->dev, "enable function %s group %s\n",
  260. info->functions[selector].name, info->groups[group].name);
  261. for (i = 0; i < npins; i++) {
  262. unsigned int mux = pins[i].mux_id;
  263. unsigned int pin_id = pins[i].pin_id;
  264. unsigned int afunction = MX1_MUX_FUNCTION(mux);
  265. unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
  266. unsigned int direction = MX1_MUX_DIR(mux);
  267. unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
  268. unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
  269. unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
  270. dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
  271. __func__, pin_id, afunction, gpio_in_use,
  272. direction, gpio_oconf, gpio_iconfa,
  273. gpio_iconfb);
  274. imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
  275. imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
  276. if (gpio_in_use) {
  277. imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
  278. imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
  279. MX1_ICONFA);
  280. imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
  281. MX1_ICONFB);
  282. } else {
  283. imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
  284. }
  285. }
  286. return 0;
  287. }
  288. static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
  289. {
  290. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  291. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  292. return info->nfunctions;
  293. }
  294. static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
  295. unsigned selector)
  296. {
  297. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  298. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  299. return info->functions[selector].name;
  300. }
  301. static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
  302. const char * const **groups,
  303. unsigned * const num_groups)
  304. {
  305. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  306. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  307. *groups = info->functions[selector].groups;
  308. *num_groups = info->functions[selector].num_groups;
  309. return 0;
  310. }
  311. static const struct pinmux_ops imx1_pmx_ops = {
  312. .get_functions_count = imx1_pmx_get_funcs_count,
  313. .get_function_name = imx1_pmx_get_func_name,
  314. .get_function_groups = imx1_pmx_get_groups,
  315. .set_mux = imx1_pmx_set,
  316. };
  317. static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
  318. unsigned pin_id, unsigned long *config)
  319. {
  320. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  321. *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
  322. return 0;
  323. }
  324. static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
  325. unsigned pin_id, unsigned long *configs,
  326. unsigned num_configs)
  327. {
  328. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  329. int i;
  330. for (i = 0; i != num_configs; ++i) {
  331. imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
  332. dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
  333. pin_desc_get(pctldev, pin_id)->name);
  334. }
  335. return 0;
  336. }
  337. static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  338. struct seq_file *s, unsigned pin_id)
  339. {
  340. unsigned long config;
  341. imx1_pinconf_get(pctldev, pin_id, &config);
  342. seq_printf(s, "0x%lx", config);
  343. }
  344. static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
  345. struct seq_file *s, unsigned group)
  346. {
  347. struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  348. const struct imx1_pinctrl_soc_info *info = ipctl->info;
  349. struct imx1_pin_group *grp;
  350. unsigned long config;
  351. const char *name;
  352. int i, ret;
  353. if (group >= info->ngroups)
  354. return;
  355. seq_puts(s, "\n");
  356. grp = &info->groups[group];
  357. for (i = 0; i < grp->npins; i++) {
  358. name = pin_get_name(pctldev, grp->pins[i].pin_id);
  359. ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
  360. if (ret)
  361. return;
  362. seq_printf(s, "%s: 0x%lx", name, config);
  363. }
  364. }
  365. static const struct pinconf_ops imx1_pinconf_ops = {
  366. .pin_config_get = imx1_pinconf_get,
  367. .pin_config_set = imx1_pinconf_set,
  368. .pin_config_dbg_show = imx1_pinconf_dbg_show,
  369. .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
  370. };
  371. static struct pinctrl_desc imx1_pinctrl_desc = {
  372. .pctlops = &imx1_pctrl_ops,
  373. .pmxops = &imx1_pmx_ops,
  374. .confops = &imx1_pinconf_ops,
  375. .owner = THIS_MODULE,
  376. };
  377. static int imx1_pinctrl_parse_groups(struct device_node *np,
  378. struct imx1_pin_group *grp,
  379. struct imx1_pinctrl_soc_info *info,
  380. u32 index)
  381. {
  382. int size;
  383. const __be32 *list;
  384. int i;
  385. dev_dbg(info->dev, "group(%d): %pOFn\n", index, np);
  386. /* Initialise group */
  387. grp->name = np->name;
  388. /*
  389. * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
  390. */
  391. list = of_get_property(np, "fsl,pins", &size);
  392. /* we do not check return since it's safe node passed down */
  393. if (!size || size % 12) {
  394. dev_notice(info->dev, "Not a valid fsl,pins property (%pOFn)\n",
  395. np);
  396. return -EINVAL;
  397. }
  398. grp->npins = size / 12;
  399. grp->pins = devm_kcalloc(info->dev,
  400. grp->npins, sizeof(struct imx1_pin), GFP_KERNEL);
  401. grp->pin_ids = devm_kcalloc(info->dev,
  402. grp->npins, sizeof(unsigned int), GFP_KERNEL);
  403. if (!grp->pins || !grp->pin_ids)
  404. return -ENOMEM;
  405. for (i = 0; i < grp->npins; i++) {
  406. grp->pins[i].pin_id = be32_to_cpu(*list++);
  407. grp->pins[i].mux_id = be32_to_cpu(*list++);
  408. grp->pins[i].config = be32_to_cpu(*list++);
  409. grp->pin_ids[i] = grp->pins[i].pin_id;
  410. }
  411. return 0;
  412. }
  413. static int imx1_pinctrl_parse_functions(struct device_node *np,
  414. struct imx1_pinctrl_soc_info *info,
  415. u32 index)
  416. {
  417. struct device_node *child;
  418. struct imx1_pmx_func *func;
  419. struct imx1_pin_group *grp;
  420. int ret;
  421. static u32 grp_index;
  422. u32 i = 0;
  423. dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np);
  424. func = &info->functions[index];
  425. /* Initialise function */
  426. func->name = np->name;
  427. func->num_groups = of_get_child_count(np);
  428. if (func->num_groups == 0)
  429. return -EINVAL;
  430. func->groups = devm_kcalloc(info->dev,
  431. func->num_groups, sizeof(char *), GFP_KERNEL);
  432. if (!func->groups)
  433. return -ENOMEM;
  434. for_each_child_of_node(np, child) {
  435. func->groups[i] = child->name;
  436. grp = &info->groups[grp_index++];
  437. ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
  438. if (ret == -ENOMEM) {
  439. of_node_put(child);
  440. return ret;
  441. }
  442. }
  443. return 0;
  444. }
  445. static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
  446. struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
  447. {
  448. struct device_node *np = pdev->dev.of_node;
  449. struct device_node *child;
  450. int ret;
  451. u32 nfuncs = 0;
  452. u32 ngroups = 0;
  453. u32 ifunc = 0;
  454. if (!np)
  455. return -ENODEV;
  456. for_each_child_of_node(np, child) {
  457. ++nfuncs;
  458. ngroups += of_get_child_count(child);
  459. }
  460. if (!nfuncs) {
  461. dev_err(&pdev->dev, "No pin functions defined\n");
  462. return -EINVAL;
  463. }
  464. info->nfunctions = nfuncs;
  465. info->functions = devm_kcalloc(&pdev->dev,
  466. nfuncs, sizeof(struct imx1_pmx_func), GFP_KERNEL);
  467. info->ngroups = ngroups;
  468. info->groups = devm_kcalloc(&pdev->dev,
  469. ngroups, sizeof(struct imx1_pin_group), GFP_KERNEL);
  470. if (!info->functions || !info->groups)
  471. return -ENOMEM;
  472. for_each_child_of_node(np, child) {
  473. ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
  474. if (ret == -ENOMEM) {
  475. of_node_put(child);
  476. return -ENOMEM;
  477. }
  478. }
  479. return 0;
  480. }
  481. int imx1_pinctrl_core_probe(struct platform_device *pdev,
  482. struct imx1_pinctrl_soc_info *info)
  483. {
  484. struct imx1_pinctrl *ipctl;
  485. struct resource *res;
  486. struct pinctrl_desc *pctl_desc;
  487. int ret;
  488. if (!info || !info->pins || !info->npins) {
  489. dev_err(&pdev->dev, "wrong pinctrl info\n");
  490. return -EINVAL;
  491. }
  492. info->dev = &pdev->dev;
  493. /* Create state holders etc for this driver */
  494. ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
  495. if (!ipctl)
  496. return -ENOMEM;
  497. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  498. if (!res)
  499. return -ENOENT;
  500. ipctl->base = devm_ioremap(&pdev->dev, res->start,
  501. resource_size(res));
  502. if (!ipctl->base)
  503. return -ENOMEM;
  504. pctl_desc = &imx1_pinctrl_desc;
  505. pctl_desc->name = dev_name(&pdev->dev);
  506. pctl_desc->pins = info->pins;
  507. pctl_desc->npins = info->npins;
  508. ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
  509. if (ret) {
  510. dev_err(&pdev->dev, "fail to probe dt properties\n");
  511. return ret;
  512. }
  513. ipctl->info = info;
  514. ipctl->dev = info->dev;
  515. platform_set_drvdata(pdev, ipctl);
  516. ipctl->pctl = devm_pinctrl_register(&pdev->dev, pctl_desc, ipctl);
  517. if (IS_ERR(ipctl->pctl)) {
  518. dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
  519. return PTR_ERR(ipctl->pctl);
  520. }
  521. ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
  522. if (ret) {
  523. dev_err(&pdev->dev, "Failed to populate subdevices\n");
  524. return ret;
  525. }
  526. dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
  527. return 0;
  528. }