pinctrl-imx.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. //
  3. // Core driver for the imx pin controller
  4. //
  5. // Copyright (C) 2012 Freescale Semiconductor, Inc.
  6. // Copyright (C) 2012 Linaro Ltd.
  7. //
  8. // Author: Dong Aisheng <dong.aisheng@linaro.org>
  9. #include <linux/err.h>
  10. #include <linux/init.h>
  11. #include <linux/io.h>
  12. #include <linux/mfd/syscon.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_address.h>
  17. #include <linux/pinctrl/machine.h>
  18. #include <linux/pinctrl/pinconf.h>
  19. #include <linux/pinctrl/pinctrl.h>
  20. #include <linux/pinctrl/pinmux.h>
  21. #include <linux/slab.h>
  22. #include <linux/regmap.h>
  23. #include "../core.h"
  24. #include "../pinconf.h"
  25. #include "../pinmux.h"
  26. #include "pinctrl-imx.h"
  27. /* The bits in CONFIG cell defined in binding doc*/
  28. #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
  29. #define IMX_PAD_SION 0x40000000 /* set SION */
  30. static inline const struct group_desc *imx_pinctrl_find_group_by_name(
  31. struct pinctrl_dev *pctldev,
  32. const char *name)
  33. {
  34. const struct group_desc *grp = NULL;
  35. int i;
  36. for (i = 0; i < pctldev->num_groups; i++) {
  37. grp = pinctrl_generic_get_group(pctldev, i);
  38. if (grp && !strcmp(grp->name, name))
  39. break;
  40. }
  41. return grp;
  42. }
  43. static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  44. unsigned offset)
  45. {
  46. seq_printf(s, "%s", dev_name(pctldev->dev));
  47. }
  48. static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
  49. struct device_node *np,
  50. struct pinctrl_map **map, unsigned *num_maps)
  51. {
  52. struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  53. const struct imx_pinctrl_soc_info *info = ipctl->info;
  54. const struct group_desc *grp;
  55. struct pinctrl_map *new_map;
  56. struct device_node *parent;
  57. struct imx_pin *pin;
  58. int map_num = 1;
  59. int i, j;
  60. /*
  61. * first find the group of this node and check if we need create
  62. * config maps for pins
  63. */
  64. grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
  65. if (!grp) {
  66. dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
  67. return -EINVAL;
  68. }
  69. if (info->flags & IMX_USE_SCU) {
  70. map_num += grp->num_pins;
  71. } else {
  72. for (i = 0; i < grp->num_pins; i++) {
  73. pin = &((struct imx_pin *)(grp->data))[i];
  74. if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
  75. map_num++;
  76. }
  77. }
  78. new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
  79. GFP_KERNEL);
  80. if (!new_map)
  81. return -ENOMEM;
  82. *map = new_map;
  83. *num_maps = map_num;
  84. /* create mux map */
  85. parent = of_get_parent(np);
  86. if (!parent) {
  87. kfree(new_map);
  88. return -EINVAL;
  89. }
  90. new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
  91. new_map[0].data.mux.function = parent->name;
  92. new_map[0].data.mux.group = np->name;
  93. of_node_put(parent);
  94. /* create config map */
  95. new_map++;
  96. for (i = j = 0; i < grp->num_pins; i++) {
  97. pin = &((struct imx_pin *)(grp->data))[i];
  98. /*
  99. * We only create config maps for SCU pads or MMIO pads that
  100. * are not using the default config(a.k.a IMX_NO_PAD_CTL)
  101. */
  102. if (!(info->flags & IMX_USE_SCU) &&
  103. (pin->conf.mmio.config & IMX_NO_PAD_CTL))
  104. continue;
  105. new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
  106. new_map[j].data.configs.group_or_pin =
  107. pin_get_name(pctldev, pin->pin);
  108. if (info->flags & IMX_USE_SCU) {
  109. /*
  110. * For SCU case, we set mux and conf together
  111. * in one IPC call
  112. */
  113. new_map[j].data.configs.configs =
  114. (unsigned long *)&pin->conf.scu;
  115. new_map[j].data.configs.num_configs = 2;
  116. } else {
  117. new_map[j].data.configs.configs =
  118. &pin->conf.mmio.config;
  119. new_map[j].data.configs.num_configs = 1;
  120. }
  121. j++;
  122. }
  123. dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
  124. (*map)->data.mux.function, (*map)->data.mux.group, map_num);
  125. return 0;
  126. }
  127. static void imx_dt_free_map(struct pinctrl_dev *pctldev,
  128. struct pinctrl_map *map, unsigned num_maps)
  129. {
  130. kfree(map);
  131. }
  132. static const struct pinctrl_ops imx_pctrl_ops = {
  133. .get_groups_count = pinctrl_generic_get_group_count,
  134. .get_group_name = pinctrl_generic_get_group_name,
  135. .get_group_pins = pinctrl_generic_get_group_pins,
  136. .pin_dbg_show = imx_pin_dbg_show,
  137. .dt_node_to_map = imx_dt_node_to_map,
  138. .dt_free_map = imx_dt_free_map,
  139. };
  140. static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
  141. struct imx_pin *pin)
  142. {
  143. const struct imx_pinctrl_soc_info *info = ipctl->info;
  144. struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
  145. const struct imx_pin_reg *pin_reg;
  146. unsigned int pin_id;
  147. pin_id = pin->pin;
  148. pin_reg = &ipctl->pin_regs[pin_id];
  149. if (pin_reg->mux_reg == -1) {
  150. dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
  151. info->pins[pin_id].name);
  152. return 0;
  153. }
  154. if (info->flags & SHARE_MUX_CONF_REG) {
  155. u32 reg;
  156. reg = readl(ipctl->base + pin_reg->mux_reg);
  157. reg &= ~info->mux_mask;
  158. reg |= (pin_mmio->mux_mode << info->mux_shift);
  159. writel(reg, ipctl->base + pin_reg->mux_reg);
  160. dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
  161. pin_reg->mux_reg, reg);
  162. } else {
  163. writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
  164. dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
  165. pin_reg->mux_reg, pin_mmio->mux_mode);
  166. }
  167. /*
  168. * If the select input value begins with 0xff, it's a quirky
  169. * select input and the value should be interpreted as below.
  170. * 31 23 15 7 0
  171. * | 0xff | shift | width | select |
  172. * It's used to work around the problem that the select
  173. * input for some pin is not implemented in the select
  174. * input register but in some general purpose register.
  175. * We encode the select input value, width and shift of
  176. * the bit field into input_val cell of pin function ID
  177. * in device tree, and then decode them here for setting
  178. * up the select input bits in general purpose register.
  179. */
  180. if (pin_mmio->input_val >> 24 == 0xff) {
  181. u32 val = pin_mmio->input_val;
  182. u8 select = val & 0xff;
  183. u8 width = (val >> 8) & 0xff;
  184. u8 shift = (val >> 16) & 0xff;
  185. u32 mask = ((1 << width) - 1) << shift;
  186. /*
  187. * The input_reg[i] here is actually some IOMUXC general
  188. * purpose register, not regular select input register.
  189. */
  190. val = readl(ipctl->base + pin_mmio->input_reg);
  191. val &= ~mask;
  192. val |= select << shift;
  193. writel(val, ipctl->base + pin_mmio->input_reg);
  194. } else if (pin_mmio->input_reg) {
  195. /*
  196. * Regular select input register can never be at offset
  197. * 0, and we only print register value for regular case.
  198. */
  199. if (ipctl->input_sel_base)
  200. writel(pin_mmio->input_val, ipctl->input_sel_base +
  201. pin_mmio->input_reg);
  202. else
  203. writel(pin_mmio->input_val, ipctl->base +
  204. pin_mmio->input_reg);
  205. dev_dbg(ipctl->dev,
  206. "==>select_input: offset 0x%x val 0x%x\n",
  207. pin_mmio->input_reg, pin_mmio->input_val);
  208. }
  209. return 0;
  210. }
  211. static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
  212. unsigned group)
  213. {
  214. struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  215. const struct imx_pinctrl_soc_info *info = ipctl->info;
  216. struct function_desc *func;
  217. struct group_desc *grp;
  218. struct imx_pin *pin;
  219. unsigned int npins;
  220. int i, err;
  221. /*
  222. * Configure the mux mode for each pin in the group for a specific
  223. * function.
  224. */
  225. grp = pinctrl_generic_get_group(pctldev, group);
  226. if (!grp)
  227. return -EINVAL;
  228. func = pinmux_generic_get_function(pctldev, selector);
  229. if (!func)
  230. return -EINVAL;
  231. npins = grp->num_pins;
  232. dev_dbg(ipctl->dev, "enable function %s group %s\n",
  233. func->name, grp->name);
  234. for (i = 0; i < npins; i++) {
  235. /*
  236. * For IMX_USE_SCU case, we postpone the mux setting
  237. * until config is set as we can set them together
  238. * in one IPC call
  239. */
  240. pin = &((struct imx_pin *)(grp->data))[i];
  241. if (!(info->flags & IMX_USE_SCU)) {
  242. err = imx_pmx_set_one_pin_mmio(ipctl, pin);
  243. if (err)
  244. return err;
  245. }
  246. }
  247. return 0;
  248. }
  249. struct pinmux_ops imx_pmx_ops = {
  250. .get_functions_count = pinmux_generic_get_function_count,
  251. .get_function_name = pinmux_generic_get_function_name,
  252. .get_function_groups = pinmux_generic_get_function_groups,
  253. .set_mux = imx_pmx_set,
  254. };
  255. /* decode generic config into raw register values */
  256. static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
  257. unsigned long *configs,
  258. unsigned int num_configs)
  259. {
  260. const struct imx_pinctrl_soc_info *info = ipctl->info;
  261. const struct imx_cfg_params_decode *decode;
  262. enum pin_config_param param;
  263. u32 raw_config = 0;
  264. u32 param_val;
  265. int i, j;
  266. WARN_ON(num_configs > info->num_decodes);
  267. for (i = 0; i < num_configs; i++) {
  268. param = pinconf_to_config_param(configs[i]);
  269. param_val = pinconf_to_config_argument(configs[i]);
  270. decode = info->decodes;
  271. for (j = 0; j < info->num_decodes; j++) {
  272. if (param == decode->param) {
  273. if (decode->invert)
  274. param_val = !param_val;
  275. raw_config |= (param_val << decode->shift)
  276. & decode->mask;
  277. break;
  278. }
  279. decode++;
  280. }
  281. }
  282. if (info->fixup)
  283. info->fixup(configs, num_configs, &raw_config);
  284. return raw_config;
  285. }
  286. static u32 imx_pinconf_parse_generic_config(struct device_node *np,
  287. struct imx_pinctrl *ipctl)
  288. {
  289. const struct imx_pinctrl_soc_info *info = ipctl->info;
  290. struct pinctrl_dev *pctl = ipctl->pctl;
  291. unsigned int num_configs;
  292. unsigned long *configs;
  293. int ret;
  294. if (!info->generic_pinconf)
  295. return 0;
  296. ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
  297. &num_configs);
  298. if (ret)
  299. return 0;
  300. return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
  301. }
  302. static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
  303. unsigned long *config)
  304. {
  305. struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  306. const struct imx_pinctrl_soc_info *info = ipctl->info;
  307. const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
  308. if (pin_reg->conf_reg == -1) {
  309. dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
  310. info->pins[pin_id].name);
  311. return -EINVAL;
  312. }
  313. *config = readl(ipctl->base + pin_reg->conf_reg);
  314. if (info->flags & SHARE_MUX_CONF_REG)
  315. *config &= ~info->mux_mask;
  316. return 0;
  317. }
  318. static int imx_pinconf_get(struct pinctrl_dev *pctldev,
  319. unsigned pin_id, unsigned long *config)
  320. {
  321. struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  322. const struct imx_pinctrl_soc_info *info = ipctl->info;
  323. if (info->flags & IMX_USE_SCU)
  324. return info->imx_pinconf_get(pctldev, pin_id, config);
  325. else
  326. return imx_pinconf_get_mmio(pctldev, pin_id, config);
  327. }
  328. static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
  329. unsigned pin_id, unsigned long *configs,
  330. unsigned num_configs)
  331. {
  332. struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  333. const struct imx_pinctrl_soc_info *info = ipctl->info;
  334. const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
  335. int i;
  336. if (pin_reg->conf_reg == -1) {
  337. dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
  338. info->pins[pin_id].name);
  339. return -EINVAL;
  340. }
  341. dev_dbg(ipctl->dev, "pinconf set pin %s\n",
  342. info->pins[pin_id].name);
  343. for (i = 0; i < num_configs; i++) {
  344. if (info->flags & SHARE_MUX_CONF_REG) {
  345. u32 reg;
  346. reg = readl(ipctl->base + pin_reg->conf_reg);
  347. reg &= info->mux_mask;
  348. reg |= configs[i];
  349. writel(reg, ipctl->base + pin_reg->conf_reg);
  350. dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
  351. pin_reg->conf_reg, reg);
  352. } else {
  353. writel(configs[i], ipctl->base + pin_reg->conf_reg);
  354. dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
  355. pin_reg->conf_reg, configs[i]);
  356. }
  357. } /* for each config */
  358. return 0;
  359. }
  360. static int imx_pinconf_set(struct pinctrl_dev *pctldev,
  361. unsigned pin_id, unsigned long *configs,
  362. unsigned num_configs)
  363. {
  364. struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  365. const struct imx_pinctrl_soc_info *info = ipctl->info;
  366. if (info->flags & IMX_USE_SCU)
  367. return info->imx_pinconf_set(pctldev, pin_id,
  368. configs, num_configs);
  369. else
  370. return imx_pinconf_set_mmio(pctldev, pin_id,
  371. configs, num_configs);
  372. }
  373. static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
  374. struct seq_file *s, unsigned pin_id)
  375. {
  376. struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  377. const struct imx_pinctrl_soc_info *info = ipctl->info;
  378. const struct imx_pin_reg *pin_reg;
  379. unsigned long config;
  380. int ret;
  381. if (info->flags & IMX_USE_SCU) {
  382. ret = info->imx_pinconf_get(pctldev, pin_id, &config);
  383. if (ret) {
  384. dev_err(ipctl->dev, "failed to get %s pinconf\n",
  385. pin_get_name(pctldev, pin_id));
  386. seq_puts(s, "N/A");
  387. return;
  388. }
  389. } else {
  390. pin_reg = &ipctl->pin_regs[pin_id];
  391. if (pin_reg->conf_reg == -1) {
  392. seq_puts(s, "N/A");
  393. return;
  394. }
  395. config = readl(ipctl->base + pin_reg->conf_reg);
  396. }
  397. seq_printf(s, "0x%lx", config);
  398. }
  399. static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
  400. struct seq_file *s, unsigned group)
  401. {
  402. struct group_desc *grp;
  403. unsigned long config;
  404. const char *name;
  405. int i, ret;
  406. if (group >= pctldev->num_groups)
  407. return;
  408. seq_puts(s, "\n");
  409. grp = pinctrl_generic_get_group(pctldev, group);
  410. if (!grp)
  411. return;
  412. for (i = 0; i < grp->num_pins; i++) {
  413. struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
  414. name = pin_get_name(pctldev, pin->pin);
  415. ret = imx_pinconf_get(pctldev, pin->pin, &config);
  416. if (ret)
  417. return;
  418. seq_printf(s, " %s: 0x%lx\n", name, config);
  419. }
  420. }
  421. static const struct pinconf_ops imx_pinconf_ops = {
  422. .pin_config_get = imx_pinconf_get,
  423. .pin_config_set = imx_pinconf_set,
  424. .pin_config_dbg_show = imx_pinconf_dbg_show,
  425. .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
  426. };
  427. /*
  428. * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
  429. * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
  430. * For generic_pinconf case, there's no extra u32 CONFIG.
  431. *
  432. * PIN_FUNC_ID format:
  433. * Default:
  434. * <mux_reg conf_reg input_reg mux_mode input_val>
  435. * SHARE_MUX_CONF_REG:
  436. * <mux_conf_reg input_reg mux_mode input_val>
  437. * IMX_USE_SCU:
  438. * <pin_id mux_mode>
  439. */
  440. #define FSL_PIN_SIZE 24
  441. #define FSL_PIN_SHARE_SIZE 20
  442. #define FSL_SCU_PIN_SIZE 12
  443. static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
  444. unsigned int *pin_id, struct imx_pin *pin,
  445. const __be32 **list_p,
  446. struct device_node *np)
  447. {
  448. const struct imx_pinctrl_soc_info *info = ipctl->info;
  449. struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
  450. struct imx_pin_reg *pin_reg;
  451. const __be32 *list = *list_p;
  452. u32 mux_reg, conf_reg;
  453. u32 config;
  454. mux_reg = be32_to_cpu(*list++);
  455. if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
  456. mux_reg = -1;
  457. if (info->flags & SHARE_MUX_CONF_REG) {
  458. conf_reg = mux_reg;
  459. } else {
  460. conf_reg = be32_to_cpu(*list++);
  461. if (!conf_reg)
  462. conf_reg = -1;
  463. }
  464. *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
  465. pin_reg = &ipctl->pin_regs[*pin_id];
  466. pin->pin = *pin_id;
  467. pin_reg->mux_reg = mux_reg;
  468. pin_reg->conf_reg = conf_reg;
  469. pin_mmio->input_reg = be32_to_cpu(*list++);
  470. pin_mmio->mux_mode = be32_to_cpu(*list++);
  471. pin_mmio->input_val = be32_to_cpu(*list++);
  472. if (info->generic_pinconf) {
  473. /* generic pin config decoded */
  474. pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
  475. } else {
  476. /* legacy pin config read from devicetree */
  477. config = be32_to_cpu(*list++);
  478. /* SION bit is in mux register */
  479. if (config & IMX_PAD_SION)
  480. pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
  481. pin_mmio->config = config & ~IMX_PAD_SION;
  482. }
  483. *list_p = list;
  484. dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
  485. pin_mmio->mux_mode, pin_mmio->config);
  486. }
  487. static int imx_pinctrl_parse_groups(struct device_node *np,
  488. struct group_desc *grp,
  489. struct imx_pinctrl *ipctl,
  490. u32 index)
  491. {
  492. const struct imx_pinctrl_soc_info *info = ipctl->info;
  493. struct imx_pin *pin;
  494. int size, pin_size;
  495. const __be32 *list;
  496. int i;
  497. dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
  498. if (info->flags & IMX_USE_SCU)
  499. pin_size = FSL_SCU_PIN_SIZE;
  500. else if (info->flags & SHARE_MUX_CONF_REG)
  501. pin_size = FSL_PIN_SHARE_SIZE;
  502. else
  503. pin_size = FSL_PIN_SIZE;
  504. if (info->generic_pinconf)
  505. pin_size -= 4;
  506. /* Initialise group */
  507. grp->name = np->name;
  508. /*
  509. * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
  510. * do sanity check and calculate pins number
  511. *
  512. * First try legacy 'fsl,pins' property, then fall back to the
  513. * generic 'pinmux'.
  514. *
  515. * Note: for generic 'pinmux' case, there's no CONFIG part in
  516. * the binding format.
  517. */
  518. list = of_get_property(np, "fsl,pins", &size);
  519. if (!list) {
  520. list = of_get_property(np, "pinmux", &size);
  521. if (!list) {
  522. dev_err(ipctl->dev,
  523. "no fsl,pins and pins property in node %pOF\n", np);
  524. return -EINVAL;
  525. }
  526. }
  527. /* we do not check return since it's safe node passed down */
  528. if (!size || size % pin_size) {
  529. dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
  530. return -EINVAL;
  531. }
  532. grp->num_pins = size / pin_size;
  533. grp->data = devm_kcalloc(ipctl->dev,
  534. grp->num_pins, sizeof(struct imx_pin),
  535. GFP_KERNEL);
  536. grp->pins = devm_kcalloc(ipctl->dev,
  537. grp->num_pins, sizeof(unsigned int),
  538. GFP_KERNEL);
  539. if (!grp->pins || !grp->data)
  540. return -ENOMEM;
  541. for (i = 0; i < grp->num_pins; i++) {
  542. pin = &((struct imx_pin *)(grp->data))[i];
  543. if (info->flags & IMX_USE_SCU)
  544. info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
  545. pin, &list);
  546. else
  547. imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
  548. pin, &list, np);
  549. }
  550. return 0;
  551. }
  552. static int imx_pinctrl_parse_functions(struct device_node *np,
  553. struct imx_pinctrl *ipctl,
  554. u32 index)
  555. {
  556. struct pinctrl_dev *pctl = ipctl->pctl;
  557. struct device_node *child;
  558. struct function_desc *func;
  559. struct group_desc *grp;
  560. u32 i = 0;
  561. dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
  562. func = pinmux_generic_get_function(pctl, index);
  563. if (!func)
  564. return -EINVAL;
  565. /* Initialise function */
  566. func->name = np->name;
  567. func->num_group_names = of_get_child_count(np);
  568. if (func->num_group_names == 0) {
  569. dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
  570. return -EINVAL;
  571. }
  572. func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
  573. sizeof(char *), GFP_KERNEL);
  574. if (!func->group_names)
  575. return -ENOMEM;
  576. for_each_child_of_node(np, child) {
  577. func->group_names[i] = child->name;
  578. grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
  579. GFP_KERNEL);
  580. if (!grp) {
  581. of_node_put(child);
  582. return -ENOMEM;
  583. }
  584. mutex_lock(&ipctl->mutex);
  585. radix_tree_insert(&pctl->pin_group_tree,
  586. ipctl->group_index++, grp);
  587. mutex_unlock(&ipctl->mutex);
  588. imx_pinctrl_parse_groups(child, grp, ipctl, i++);
  589. }
  590. return 0;
  591. }
  592. /*
  593. * Check if the DT contains pins in the direct child nodes. This indicates the
  594. * newer DT format to store pins. This function returns true if the first found
  595. * fsl,pins property is in a child of np. Otherwise false is returned.
  596. */
  597. static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
  598. {
  599. struct device_node *function_np;
  600. struct device_node *pinctrl_np;
  601. for_each_child_of_node(np, function_np) {
  602. if (of_property_read_bool(function_np, "fsl,pins")) {
  603. of_node_put(function_np);
  604. return true;
  605. }
  606. for_each_child_of_node(function_np, pinctrl_np) {
  607. if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
  608. of_node_put(pinctrl_np);
  609. of_node_put(function_np);
  610. return false;
  611. }
  612. }
  613. }
  614. return true;
  615. }
  616. static int imx_pinctrl_probe_dt(struct platform_device *pdev,
  617. struct imx_pinctrl *ipctl)
  618. {
  619. struct device_node *np = pdev->dev.of_node;
  620. struct device_node *child;
  621. struct pinctrl_dev *pctl = ipctl->pctl;
  622. u32 nfuncs = 0;
  623. u32 i = 0;
  624. bool flat_funcs;
  625. if (!np)
  626. return -ENODEV;
  627. flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
  628. if (flat_funcs) {
  629. nfuncs = 1;
  630. } else {
  631. nfuncs = of_get_child_count(np);
  632. if (nfuncs == 0) {
  633. dev_err(&pdev->dev, "no functions defined\n");
  634. return -EINVAL;
  635. }
  636. }
  637. for (i = 0; i < nfuncs; i++) {
  638. struct function_desc *function;
  639. function = devm_kzalloc(&pdev->dev, sizeof(*function),
  640. GFP_KERNEL);
  641. if (!function)
  642. return -ENOMEM;
  643. mutex_lock(&ipctl->mutex);
  644. radix_tree_insert(&pctl->pin_function_tree, i, function);
  645. mutex_unlock(&ipctl->mutex);
  646. }
  647. pctl->num_functions = nfuncs;
  648. ipctl->group_index = 0;
  649. if (flat_funcs) {
  650. pctl->num_groups = of_get_child_count(np);
  651. } else {
  652. pctl->num_groups = 0;
  653. for_each_child_of_node(np, child)
  654. pctl->num_groups += of_get_child_count(child);
  655. }
  656. if (flat_funcs) {
  657. imx_pinctrl_parse_functions(np, ipctl, 0);
  658. } else {
  659. i = 0;
  660. for_each_child_of_node(np, child)
  661. imx_pinctrl_parse_functions(child, ipctl, i++);
  662. }
  663. return 0;
  664. }
  665. int imx_pinctrl_probe(struct platform_device *pdev,
  666. const struct imx_pinctrl_soc_info *info)
  667. {
  668. struct regmap_config config = { .name = "gpr" };
  669. struct device_node *dev_np = pdev->dev.of_node;
  670. struct pinctrl_desc *imx_pinctrl_desc;
  671. struct device_node *np;
  672. struct imx_pinctrl *ipctl;
  673. struct regmap *gpr;
  674. int ret, i;
  675. if (!info || !info->pins || !info->npins) {
  676. dev_err(&pdev->dev, "wrong pinctrl info\n");
  677. return -EINVAL;
  678. }
  679. if (info->gpr_compatible) {
  680. gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
  681. if (!IS_ERR(gpr))
  682. regmap_attach_dev(&pdev->dev, gpr, &config);
  683. }
  684. /* Create state holders etc for this driver */
  685. ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
  686. if (!ipctl)
  687. return -ENOMEM;
  688. if (!(info->flags & IMX_USE_SCU)) {
  689. ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
  690. sizeof(*ipctl->pin_regs),
  691. GFP_KERNEL);
  692. if (!ipctl->pin_regs)
  693. return -ENOMEM;
  694. for (i = 0; i < info->npins; i++) {
  695. ipctl->pin_regs[i].mux_reg = -1;
  696. ipctl->pin_regs[i].conf_reg = -1;
  697. }
  698. ipctl->base = devm_platform_ioremap_resource(pdev, 0);
  699. if (IS_ERR(ipctl->base))
  700. return PTR_ERR(ipctl->base);
  701. if (of_property_read_bool(dev_np, "fsl,input-sel")) {
  702. np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
  703. if (!np) {
  704. dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
  705. return -EINVAL;
  706. }
  707. ipctl->input_sel_base = of_iomap(np, 0);
  708. of_node_put(np);
  709. if (!ipctl->input_sel_base) {
  710. dev_err(&pdev->dev,
  711. "iomuxc input select base address not found\n");
  712. return -ENOMEM;
  713. }
  714. }
  715. }
  716. imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
  717. GFP_KERNEL);
  718. if (!imx_pinctrl_desc)
  719. return -ENOMEM;
  720. imx_pinctrl_desc->name = dev_name(&pdev->dev);
  721. imx_pinctrl_desc->pins = info->pins;
  722. imx_pinctrl_desc->npins = info->npins;
  723. imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
  724. imx_pinctrl_desc->pmxops = &imx_pmx_ops;
  725. imx_pinctrl_desc->confops = &imx_pinconf_ops;
  726. imx_pinctrl_desc->owner = THIS_MODULE;
  727. /* for generic pinconf */
  728. imx_pinctrl_desc->custom_params = info->custom_params;
  729. imx_pinctrl_desc->num_custom_params = info->num_custom_params;
  730. /* platform specific callback */
  731. imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
  732. mutex_init(&ipctl->mutex);
  733. ipctl->info = info;
  734. ipctl->dev = &pdev->dev;
  735. platform_set_drvdata(pdev, ipctl);
  736. ret = devm_pinctrl_register_and_init(&pdev->dev,
  737. imx_pinctrl_desc, ipctl,
  738. &ipctl->pctl);
  739. if (ret) {
  740. dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
  741. return ret;
  742. }
  743. ret = imx_pinctrl_probe_dt(pdev, ipctl);
  744. if (ret) {
  745. dev_err(&pdev->dev, "fail to probe dt properties\n");
  746. return ret;
  747. }
  748. dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
  749. return pinctrl_enable(ipctl->pctl);
  750. }
  751. EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
  752. static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
  753. {
  754. struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
  755. return pinctrl_force_sleep(ipctl->pctl);
  756. }
  757. static int __maybe_unused imx_pinctrl_resume(struct device *dev)
  758. {
  759. struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
  760. return pinctrl_force_default(ipctl->pctl);
  761. }
  762. const struct dev_pm_ops imx_pinctrl_pm_ops = {
  763. SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
  764. imx_pinctrl_resume)
  765. };
  766. EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
  767. MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
  768. MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
  769. MODULE_LICENSE("GPL v2");