phy-zynqmp.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
  4. *
  5. * Copyright (C) 2018-2020 Xilinx Inc.
  6. *
  7. * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
  8. * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>
  9. * Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10. *
  11. * This driver is tested for USB, SATA and Display Port currently.
  12. * Other controllers PCIe and SGMII should also work but that is
  13. * experimental as of now.
  14. */
  15. #include <linux/clk.h>
  16. #include <linux/delay.h>
  17. #include <linux/io.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/phy/phy.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/slab.h>
  24. #include <dt-bindings/phy/phy.h>
  25. /*
  26. * Lane Registers
  27. */
  28. /* TX De-emphasis parameters */
  29. #define L0_TX_ANA_TM_18 0x0048
  30. #define L0_TX_ANA_TM_118 0x01d8
  31. #define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0)
  32. /* DN Resistor calibration code parameters */
  33. #define L0_TXPMA_ST_3 0x0b0c
  34. #define L0_DN_CALIB_CODE 0x3f
  35. /* PMA control parameters */
  36. #define L0_TXPMD_TM_45 0x0cb4
  37. #define L0_TXPMD_TM_48 0x0cc0
  38. #define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0)
  39. #define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1)
  40. #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
  41. #define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3)
  42. #define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4)
  43. #define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5)
  44. /* PCS control parameters */
  45. #define L0_TM_DIG_6 0x106c
  46. #define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f
  47. #define L0_TX_DIG_61 0x00f4
  48. #define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f
  49. /* PLL Test Mode register parameters */
  50. #define L0_TM_PLL_DIG_37 0x2094
  51. #define L0_TM_COARSE_CODE_LIMIT 0x10
  52. /* PLL SSC step size offsets */
  53. #define L0_PLL_SS_STEPS_0_LSB 0x2368
  54. #define L0_PLL_SS_STEPS_1_MSB 0x236c
  55. #define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370
  56. #define L0_PLL_SS_STEP_SIZE_1 0x2374
  57. #define L0_PLL_SS_STEP_SIZE_2 0x2378
  58. #define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c
  59. #define L0_PLL_STATUS_READ_1 0x23e4
  60. /* SSC step size parameters */
  61. #define STEP_SIZE_0_MASK 0xff
  62. #define STEP_SIZE_1_MASK 0xff
  63. #define STEP_SIZE_2_MASK 0xff
  64. #define STEP_SIZE_3_MASK 0x3
  65. #define STEP_SIZE_SHIFT 8
  66. #define FORCE_STEP_SIZE 0x10
  67. #define FORCE_STEPS 0x20
  68. #define STEPS_0_MASK 0xff
  69. #define STEPS_1_MASK 0x07
  70. /* Reference clock selection parameters */
  71. #define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
  72. #define L0_REF_CLK_SEL_MASK 0x8f
  73. /* Calibration digital logic parameters */
  74. #define L3_TM_CALIB_DIG19 0xec4c
  75. #define L3_CALIB_DONE_STATUS 0xef14
  76. #define L3_TM_CALIB_DIG18 0xec48
  77. #define L3_TM_CALIB_DIG19_NSW 0x07
  78. #define L3_TM_CALIB_DIG18_NSW 0xe0
  79. #define L3_TM_OVERRIDE_NSW_CODE 0x20
  80. #define L3_CALIB_DONE 0x02
  81. #define L3_NSW_SHIFT 5
  82. #define L3_NSW_PIPE_SHIFT 4
  83. #define L3_NSW_CALIB_SHIFT 3
  84. #define PHY_REG_OFFSET 0x4000
  85. /*
  86. * Global Registers
  87. */
  88. /* Refclk selection parameters */
  89. #define PLL_REF_SEL(n) (0x10000 + (n) * 4)
  90. #define PLL_FREQ_MASK 0x1f
  91. #define PLL_STATUS_LOCKED 0x10
  92. /* Inter Connect Matrix parameters */
  93. #define ICM_CFG0 0x10010
  94. #define ICM_CFG1 0x10014
  95. #define ICM_CFG0_L0_MASK 0x07
  96. #define ICM_CFG0_L1_MASK 0x70
  97. #define ICM_CFG1_L2_MASK 0x07
  98. #define ICM_CFG2_L3_MASK 0x70
  99. #define ICM_CFG_SHIFT 4
  100. /* Inter Connect Matrix allowed protocols */
  101. #define ICM_PROTOCOL_PD 0x0
  102. #define ICM_PROTOCOL_PCIE 0x1
  103. #define ICM_PROTOCOL_SATA 0x2
  104. #define ICM_PROTOCOL_USB 0x3
  105. #define ICM_PROTOCOL_DP 0x4
  106. #define ICM_PROTOCOL_SGMII 0x5
  107. /* Test Mode common reset control parameters */
  108. #define TM_CMN_RST 0x10018
  109. #define TM_CMN_RST_EN 0x1
  110. #define TM_CMN_RST_SET 0x2
  111. #define TM_CMN_RST_MASK 0x3
  112. /* Bus width parameters */
  113. #define TX_PROT_BUS_WIDTH 0x10040
  114. #define RX_PROT_BUS_WIDTH 0x10044
  115. #define PROT_BUS_WIDTH_10 0x0
  116. #define PROT_BUS_WIDTH_20 0x1
  117. #define PROT_BUS_WIDTH_40 0x2
  118. #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
  119. #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
  120. /* Number of GT lanes */
  121. #define NUM_LANES 4
  122. /* SIOU SATA control register */
  123. #define SATA_CONTROL_OFFSET 0x0100
  124. /* Total number of controllers */
  125. #define CONTROLLERS_PER_LANE 5
  126. /* Protocol Type parameters */
  127. #define XPSGTR_TYPE_USB0 0 /* USB controller 0 */
  128. #define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
  129. #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
  130. #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
  131. #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
  132. #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
  133. #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
  134. #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
  135. #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
  136. #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
  137. #define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
  138. #define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
  139. #define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */
  140. #define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */
  141. /* Timeout values */
  142. #define TIMEOUT_US 1000
  143. struct xpsgtr_dev;
  144. /**
  145. * struct xpsgtr_ssc - structure to hold SSC settings for a lane
  146. * @refclk_rate: PLL reference clock frequency
  147. * @pll_ref_clk: value to be written to register for corresponding ref clk rate
  148. * @steps: number of steps of SSC (Spread Spectrum Clock)
  149. * @step_size: step size of each step
  150. */
  151. struct xpsgtr_ssc {
  152. u32 refclk_rate;
  153. u8 pll_ref_clk;
  154. u32 steps;
  155. u32 step_size;
  156. };
  157. /**
  158. * struct xpsgtr_phy - representation of a lane
  159. * @phy: pointer to the kernel PHY device
  160. * @type: controller which uses this lane
  161. * @lane: lane number
  162. * @protocol: protocol in which the lane operates
  163. * @skip_phy_init: skip phy_init() if true
  164. * @dev: pointer to the xpsgtr_dev instance
  165. * @refclk: reference clock index
  166. */
  167. struct xpsgtr_phy {
  168. struct phy *phy;
  169. u8 type;
  170. u8 lane;
  171. u8 protocol;
  172. bool skip_phy_init;
  173. struct xpsgtr_dev *dev;
  174. unsigned int refclk;
  175. };
  176. /**
  177. * struct xpsgtr_dev - representation of a ZynMP GT device
  178. * @dev: pointer to device
  179. * @serdes: serdes base address
  180. * @siou: siou base address
  181. * @gtr_mutex: mutex for locking
  182. * @phys: PHY lanes
  183. * @refclk_sscs: spread spectrum settings for the reference clocks
  184. * @tx_term_fix: fix for GT issue
  185. * @saved_icm_cfg0: stored value of ICM CFG0 register
  186. * @saved_icm_cfg1: stored value of ICM CFG1 register
  187. */
  188. struct xpsgtr_dev {
  189. struct device *dev;
  190. void __iomem *serdes;
  191. void __iomem *siou;
  192. struct mutex gtr_mutex; /* mutex for locking */
  193. struct xpsgtr_phy phys[NUM_LANES];
  194. const struct xpsgtr_ssc *refclk_sscs[NUM_LANES];
  195. bool tx_term_fix;
  196. unsigned int saved_icm_cfg0;
  197. unsigned int saved_icm_cfg1;
  198. };
  199. /*
  200. * Configuration Data
  201. */
  202. /* lookup table to hold all settings needed for a ref clock frequency */
  203. static const struct xpsgtr_ssc ssc_lookup[] = {
  204. { 19200000, 0x05, 608, 264020 },
  205. { 20000000, 0x06, 634, 243454 },
  206. { 24000000, 0x07, 760, 168973 },
  207. { 26000000, 0x08, 824, 143860 },
  208. { 27000000, 0x09, 856, 86551 },
  209. { 38400000, 0x0a, 1218, 65896 },
  210. { 40000000, 0x0b, 634, 243454 },
  211. { 52000000, 0x0c, 824, 143860 },
  212. { 100000000, 0x0d, 1058, 87533 },
  213. { 108000000, 0x0e, 856, 86551 },
  214. { 125000000, 0x0f, 992, 119497 },
  215. { 135000000, 0x10, 1070, 55393 },
  216. { 150000000, 0x11, 792, 187091 }
  217. };
  218. /*
  219. * I/O Accessors
  220. */
  221. static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
  222. {
  223. return readl(gtr_dev->serdes + reg);
  224. }
  225. static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
  226. {
  227. writel(value, gtr_dev->serdes + reg);
  228. }
  229. static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
  230. u32 clr, u32 set)
  231. {
  232. u32 value = xpsgtr_read(gtr_dev, reg);
  233. value &= ~clr;
  234. value |= set;
  235. xpsgtr_write(gtr_dev, reg, value);
  236. }
  237. static inline u32 xpsgtr_read_phy(struct xpsgtr_phy *gtr_phy, u32 reg)
  238. {
  239. void __iomem *addr = gtr_phy->dev->serdes
  240. + gtr_phy->lane * PHY_REG_OFFSET + reg;
  241. return readl(addr);
  242. }
  243. static inline void xpsgtr_write_phy(struct xpsgtr_phy *gtr_phy,
  244. u32 reg, u32 value)
  245. {
  246. void __iomem *addr = gtr_phy->dev->serdes
  247. + gtr_phy->lane * PHY_REG_OFFSET + reg;
  248. writel(value, addr);
  249. }
  250. static inline void xpsgtr_clr_set_phy(struct xpsgtr_phy *gtr_phy,
  251. u32 reg, u32 clr, u32 set)
  252. {
  253. void __iomem *addr = gtr_phy->dev->serdes
  254. + gtr_phy->lane * PHY_REG_OFFSET + reg;
  255. writel((readl(addr) & ~clr) | set, addr);
  256. }
  257. /*
  258. * Hardware Configuration
  259. */
  260. /* Wait for the PLL to lock (with a timeout). */
  261. static int xpsgtr_wait_pll_lock(struct phy *phy)
  262. {
  263. struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
  264. struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
  265. unsigned int timeout = TIMEOUT_US;
  266. int ret;
  267. dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
  268. while (1) {
  269. u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
  270. if ((reg & PLL_STATUS_LOCKED) == PLL_STATUS_LOCKED) {
  271. ret = 0;
  272. break;
  273. }
  274. if (--timeout == 0) {
  275. ret = -ETIMEDOUT;
  276. break;
  277. }
  278. udelay(1);
  279. }
  280. if (ret == -ETIMEDOUT)
  281. dev_err(gtr_dev->dev,
  282. "lane %u (type %u, protocol %u): PLL lock timeout\n",
  283. gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
  284. return ret;
  285. }
  286. /* Configure PLL and spread-sprectrum clock. */
  287. static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
  288. {
  289. const struct xpsgtr_ssc *ssc;
  290. u32 step_size;
  291. ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk];
  292. step_size = ssc->step_size;
  293. xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
  294. PLL_FREQ_MASK, ssc->pll_ref_clk);
  295. /* Enable lane clock sharing, if required */
  296. if (gtr_phy->refclk != gtr_phy->lane) {
  297. /* Lane3 Ref Clock Selection Register */
  298. xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
  299. L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
  300. }
  301. /* SSC step size [7:0] */
  302. xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
  303. STEP_SIZE_0_MASK, step_size & STEP_SIZE_0_MASK);
  304. /* SSC step size [15:8] */
  305. step_size >>= STEP_SIZE_SHIFT;
  306. xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_1,
  307. STEP_SIZE_1_MASK, step_size & STEP_SIZE_1_MASK);
  308. /* SSC step size [23:16] */
  309. step_size >>= STEP_SIZE_SHIFT;
  310. xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_2,
  311. STEP_SIZE_2_MASK, step_size & STEP_SIZE_2_MASK);
  312. /* SSC steps [7:0] */
  313. xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_0_LSB,
  314. STEPS_0_MASK, ssc->steps & STEPS_0_MASK);
  315. /* SSC steps [10:8] */
  316. xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEPS_1_MSB,
  317. STEPS_1_MASK,
  318. (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK);
  319. /* SSC step size [24:25] */
  320. step_size >>= STEP_SIZE_SHIFT;
  321. xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_3_MSB,
  322. STEP_SIZE_3_MASK, (step_size & STEP_SIZE_3_MASK) |
  323. FORCE_STEP_SIZE | FORCE_STEPS);
  324. }
  325. /* Configure the lane protocol. */
  326. static void xpsgtr_lane_set_protocol(struct xpsgtr_phy *gtr_phy)
  327. {
  328. struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
  329. u8 protocol = gtr_phy->protocol;
  330. switch (gtr_phy->lane) {
  331. case 0:
  332. xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L0_MASK, protocol);
  333. break;
  334. case 1:
  335. xpsgtr_clr_set(gtr_dev, ICM_CFG0, ICM_CFG0_L1_MASK,
  336. protocol << ICM_CFG_SHIFT);
  337. break;
  338. case 2:
  339. xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L0_MASK, protocol);
  340. break;
  341. case 3:
  342. xpsgtr_clr_set(gtr_dev, ICM_CFG1, ICM_CFG0_L1_MASK,
  343. protocol << ICM_CFG_SHIFT);
  344. break;
  345. default:
  346. /* We already checked 0 <= lane <= 3 */
  347. break;
  348. }
  349. }
  350. /* Bypass (de)scrambler and 8b/10b decoder and encoder. */
  351. static void xpsgtr_bypass_scrambler_8b10b(struct xpsgtr_phy *gtr_phy)
  352. {
  353. xpsgtr_write_phy(gtr_phy, L0_TM_DIG_6, L0_TM_DIS_DESCRAMBLE_DECODER);
  354. xpsgtr_write_phy(gtr_phy, L0_TX_DIG_61, L0_TM_DISABLE_SCRAMBLE_ENCODER);
  355. }
  356. /* DP-specific initialization. */
  357. static void xpsgtr_phy_init_dp(struct xpsgtr_phy *gtr_phy)
  358. {
  359. xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_45,
  360. L0_TXPMD_TM_45_OVER_DP_MAIN |
  361. L0_TXPMD_TM_45_ENABLE_DP_MAIN |
  362. L0_TXPMD_TM_45_OVER_DP_POST1 |
  363. L0_TXPMD_TM_45_OVER_DP_POST2 |
  364. L0_TXPMD_TM_45_ENABLE_DP_POST2);
  365. xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_118,
  366. L0_TX_ANA_TM_118_FORCE_17_0);
  367. }
  368. /* SATA-specific initialization. */
  369. static void xpsgtr_phy_init_sata(struct xpsgtr_phy *gtr_phy)
  370. {
  371. struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
  372. xpsgtr_bypass_scrambler_8b10b(gtr_phy);
  373. writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
  374. }
  375. /* SGMII-specific initialization. */
  376. static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy)
  377. {
  378. struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
  379. u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
  380. u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
  381. /* Set SGMII protocol TX and RX bus width to 10 bits. */
  382. xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val);
  383. xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val);
  384. xpsgtr_bypass_scrambler_8b10b(gtr_phy);
  385. }
  386. /* Configure TX de-emphasis and margining for DP. */
  387. static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre,
  388. unsigned int voltage)
  389. {
  390. static const u8 voltage_swing[4][4] = {
  391. { 0x2a, 0x27, 0x24, 0x20 },
  392. { 0x27, 0x23, 0x20, 0xff },
  393. { 0x24, 0x20, 0xff, 0xff },
  394. { 0xff, 0xff, 0xff, 0xff }
  395. };
  396. static const u8 pre_emphasis[4][4] = {
  397. { 0x02, 0x02, 0x02, 0x02 },
  398. { 0x01, 0x01, 0x01, 0xff },
  399. { 0x00, 0x00, 0xff, 0xff },
  400. { 0xff, 0xff, 0xff, 0xff }
  401. };
  402. xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]);
  403. xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]);
  404. }
  405. /*
  406. * PHY Operations
  407. */
  408. static bool xpsgtr_phy_init_required(struct xpsgtr_phy *gtr_phy)
  409. {
  410. /*
  411. * As USB may save the snapshot of the states during hibernation, doing
  412. * phy_init() will put the USB controller into reset, resulting in the
  413. * losing of the saved snapshot. So try to avoid phy_init() for USB
  414. * except when gtr_phy->skip_phy_init is false (this happens when FPD is
  415. * shutdown during suspend or when gt lane is changed from current one)
  416. */
  417. if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init)
  418. return false;
  419. else
  420. return true;
  421. }
  422. /*
  423. * There is a functional issue in the GT. The TX termination resistance can be
  424. * out of spec due to a issue in the calibration logic. This is the workaround
  425. * to fix it, required for XCZU9EG silicon.
  426. */
  427. static int xpsgtr_phy_tx_term_fix(struct xpsgtr_phy *gtr_phy)
  428. {
  429. struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
  430. u32 timeout = TIMEOUT_US;
  431. u32 nsw;
  432. /* Enabling Test Mode control for CMN Rest */
  433. xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
  434. /* Set Test Mode reset */
  435. xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
  436. xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18, 0x00);
  437. xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, L3_TM_OVERRIDE_NSW_CODE);
  438. /*
  439. * As a part of work around sequence for PMOS calibration fix,
  440. * we need to configure any lane ICM_CFG to valid protocol. This
  441. * will deassert the CMN_Resetn signal.
  442. */
  443. xpsgtr_lane_set_protocol(gtr_phy);
  444. /* Clear Test Mode reset */
  445. xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
  446. dev_dbg(gtr_dev->dev, "calibrating...\n");
  447. do {
  448. u32 reg = xpsgtr_read(gtr_dev, L3_CALIB_DONE_STATUS);
  449. if ((reg & L3_CALIB_DONE) == L3_CALIB_DONE)
  450. break;
  451. if (!--timeout) {
  452. dev_err(gtr_dev->dev, "calibration time out\n");
  453. return -ETIMEDOUT;
  454. }
  455. udelay(1);
  456. } while (timeout > 0);
  457. dev_dbg(gtr_dev->dev, "calibration done\n");
  458. /* Reading NMOS Register Code */
  459. nsw = xpsgtr_read(gtr_dev, L0_TXPMA_ST_3) & L0_DN_CALIB_CODE;
  460. /* Set Test Mode reset */
  461. xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_EN);
  462. /* Writing NMOS register values back [5:3] */
  463. xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG19, nsw >> L3_NSW_CALIB_SHIFT);
  464. /* Writing NMOS register value [2:0] */
  465. xpsgtr_write(gtr_dev, L3_TM_CALIB_DIG18,
  466. ((nsw & L3_TM_CALIB_DIG19_NSW) << L3_NSW_SHIFT) |
  467. (1 << L3_NSW_PIPE_SHIFT));
  468. /* Clear Test Mode reset */
  469. xpsgtr_clr_set(gtr_dev, TM_CMN_RST, TM_CMN_RST_MASK, TM_CMN_RST_SET);
  470. return 0;
  471. }
  472. static int xpsgtr_phy_init(struct phy *phy)
  473. {
  474. struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
  475. struct xpsgtr_dev *gtr_dev = gtr_phy->dev;
  476. int ret = 0;
  477. mutex_lock(&gtr_dev->gtr_mutex);
  478. /* Skip initialization if not required. */
  479. if (!xpsgtr_phy_init_required(gtr_phy))
  480. goto out;
  481. if (gtr_dev->tx_term_fix) {
  482. ret = xpsgtr_phy_tx_term_fix(gtr_phy);
  483. if (ret < 0)
  484. goto out;
  485. gtr_dev->tx_term_fix = false;
  486. }
  487. /* Enable coarse code saturation limiting logic. */
  488. xpsgtr_write_phy(gtr_phy, L0_TM_PLL_DIG_37, L0_TM_COARSE_CODE_LIMIT);
  489. /*
  490. * Configure the PLL, the lane protocol, and perform protocol-specific
  491. * initialization.
  492. */
  493. xpsgtr_configure_pll(gtr_phy);
  494. xpsgtr_lane_set_protocol(gtr_phy);
  495. switch (gtr_phy->protocol) {
  496. case ICM_PROTOCOL_DP:
  497. xpsgtr_phy_init_dp(gtr_phy);
  498. break;
  499. case ICM_PROTOCOL_SATA:
  500. xpsgtr_phy_init_sata(gtr_phy);
  501. break;
  502. case ICM_PROTOCOL_SGMII:
  503. xpsgtr_phy_init_sgmii(gtr_phy);
  504. break;
  505. }
  506. out:
  507. mutex_unlock(&gtr_dev->gtr_mutex);
  508. return ret;
  509. }
  510. static int xpsgtr_phy_exit(struct phy *phy)
  511. {
  512. struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
  513. gtr_phy->skip_phy_init = false;
  514. return 0;
  515. }
  516. static int xpsgtr_phy_power_on(struct phy *phy)
  517. {
  518. struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
  519. int ret = 0;
  520. /*
  521. * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
  522. * cumulating waits for both lanes. The user is expected to initialize
  523. * lane 0 last.
  524. */
  525. if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
  526. gtr_phy->type == XPSGTR_TYPE_DP_0)
  527. ret = xpsgtr_wait_pll_lock(phy);
  528. return ret;
  529. }
  530. static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
  531. {
  532. struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);
  533. if (gtr_phy->protocol != ICM_PROTOCOL_DP)
  534. return 0;
  535. xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]);
  536. return 0;
  537. }
  538. static const struct phy_ops xpsgtr_phyops = {
  539. .init = xpsgtr_phy_init,
  540. .exit = xpsgtr_phy_exit,
  541. .power_on = xpsgtr_phy_power_on,
  542. .configure = xpsgtr_phy_configure,
  543. .owner = THIS_MODULE,
  544. };
  545. /*
  546. * OF Xlate Support
  547. */
  548. /* Set the lane type and protocol based on the PHY type and instance number. */
  549. static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
  550. unsigned int phy_instance)
  551. {
  552. unsigned int num_phy_types;
  553. const int *phy_types;
  554. switch (phy_type) {
  555. case PHY_TYPE_SATA: {
  556. static const int types[] = {
  557. XPSGTR_TYPE_SATA_0,
  558. XPSGTR_TYPE_SATA_1,
  559. };
  560. phy_types = types;
  561. num_phy_types = ARRAY_SIZE(types);
  562. gtr_phy->protocol = ICM_PROTOCOL_SATA;
  563. break;
  564. }
  565. case PHY_TYPE_USB3: {
  566. static const int types[] = {
  567. XPSGTR_TYPE_USB0,
  568. XPSGTR_TYPE_USB1,
  569. };
  570. phy_types = types;
  571. num_phy_types = ARRAY_SIZE(types);
  572. gtr_phy->protocol = ICM_PROTOCOL_USB;
  573. break;
  574. }
  575. case PHY_TYPE_DP: {
  576. static const int types[] = {
  577. XPSGTR_TYPE_DP_0,
  578. XPSGTR_TYPE_DP_1,
  579. };
  580. phy_types = types;
  581. num_phy_types = ARRAY_SIZE(types);
  582. gtr_phy->protocol = ICM_PROTOCOL_DP;
  583. break;
  584. }
  585. case PHY_TYPE_PCIE: {
  586. static const int types[] = {
  587. XPSGTR_TYPE_PCIE_0,
  588. XPSGTR_TYPE_PCIE_1,
  589. XPSGTR_TYPE_PCIE_2,
  590. XPSGTR_TYPE_PCIE_3,
  591. };
  592. phy_types = types;
  593. num_phy_types = ARRAY_SIZE(types);
  594. gtr_phy->protocol = ICM_PROTOCOL_PCIE;
  595. break;
  596. }
  597. case PHY_TYPE_SGMII: {
  598. static const int types[] = {
  599. XPSGTR_TYPE_SGMII0,
  600. XPSGTR_TYPE_SGMII1,
  601. XPSGTR_TYPE_SGMII2,
  602. XPSGTR_TYPE_SGMII3,
  603. };
  604. phy_types = types;
  605. num_phy_types = ARRAY_SIZE(types);
  606. gtr_phy->protocol = ICM_PROTOCOL_SGMII;
  607. break;
  608. }
  609. default:
  610. return -EINVAL;
  611. }
  612. if (phy_instance >= num_phy_types)
  613. return -EINVAL;
  614. gtr_phy->type = phy_types[phy_instance];
  615. return 0;
  616. }
  617. /*
  618. * Valid combinations of controllers and lanes (Interconnect Matrix).
  619. */
  620. static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
  621. { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
  622. XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
  623. { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
  624. XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
  625. { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
  626. XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
  627. { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
  628. XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
  629. };
  630. /* Translate OF phandle and args to PHY instance. */
  631. static struct phy *xpsgtr_xlate(struct device *dev,
  632. struct of_phandle_args *args)
  633. {
  634. struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
  635. struct xpsgtr_phy *gtr_phy;
  636. unsigned int phy_instance;
  637. unsigned int phy_lane;
  638. unsigned int phy_type;
  639. unsigned int refclk;
  640. unsigned int i;
  641. int ret;
  642. if (args->args_count != 4) {
  643. dev_err(dev, "Invalid number of cells in 'phy' property\n");
  644. return ERR_PTR(-EINVAL);
  645. }
  646. /*
  647. * Get the PHY parameters from the OF arguments and derive the lane
  648. * type.
  649. */
  650. phy_lane = args->args[0];
  651. if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) {
  652. dev_err(dev, "Invalid lane number %u\n", phy_lane);
  653. return ERR_PTR(-ENODEV);
  654. }
  655. gtr_phy = &gtr_dev->phys[phy_lane];
  656. phy_type = args->args[1];
  657. phy_instance = args->args[2];
  658. ret = xpsgtr_set_lane_type(gtr_phy, phy_type, phy_instance);
  659. if (ret < 0) {
  660. dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n");
  661. return ERR_PTR(ret);
  662. }
  663. refclk = args->args[3];
  664. if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) ||
  665. !gtr_dev->refclk_sscs[refclk]) {
  666. dev_err(dev, "Invalid reference clock number %u\n", refclk);
  667. return ERR_PTR(-EINVAL);
  668. }
  669. gtr_phy->refclk = refclk;
  670. /*
  671. * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
  672. * is allowed to operate on the lane.
  673. */
  674. for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
  675. if (icm_matrix[phy_lane][i] == gtr_phy->type)
  676. return gtr_phy->phy;
  677. }
  678. return ERR_PTR(-EINVAL);
  679. }
  680. /*
  681. * Power Management
  682. */
  683. static int __maybe_unused xpsgtr_suspend(struct device *dev)
  684. {
  685. struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
  686. /* Save the snapshot ICM_CFG registers. */
  687. gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
  688. gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
  689. return 0;
  690. }
  691. static int __maybe_unused xpsgtr_resume(struct device *dev)
  692. {
  693. struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
  694. unsigned int icm_cfg0, icm_cfg1;
  695. unsigned int i;
  696. bool skip_phy_init;
  697. icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
  698. icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
  699. /* Return if no GT lanes got configured before suspend. */
  700. if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1)
  701. return 0;
  702. /* Check if the ICM configurations changed after suspend. */
  703. if (icm_cfg0 == gtr_dev->saved_icm_cfg0 &&
  704. icm_cfg1 == gtr_dev->saved_icm_cfg1)
  705. skip_phy_init = true;
  706. else
  707. skip_phy_init = false;
  708. /* Update the skip_phy_init for all gtr_phy instances. */
  709. for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
  710. gtr_dev->phys[i].skip_phy_init = skip_phy_init;
  711. return 0;
  712. }
  713. static const struct dev_pm_ops xpsgtr_pm_ops = {
  714. SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume)
  715. };
  716. /*
  717. * Probe & Platform Driver
  718. */
  719. static int xpsgtr_get_ref_clocks(struct xpsgtr_dev *gtr_dev)
  720. {
  721. unsigned int refclk;
  722. for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) {
  723. unsigned long rate;
  724. unsigned int i;
  725. struct clk *clk;
  726. char name[8];
  727. snprintf(name, sizeof(name), "ref%u", refclk);
  728. clk = devm_clk_get_optional(gtr_dev->dev, name);
  729. if (IS_ERR(clk)) {
  730. if (PTR_ERR(clk) != -EPROBE_DEFER)
  731. dev_err(gtr_dev->dev,
  732. "Failed to get reference clock %u: %ld\n",
  733. refclk, PTR_ERR(clk));
  734. return PTR_ERR(clk);
  735. }
  736. if (!clk)
  737. continue;
  738. /*
  739. * Get the spread spectrum (SSC) settings for the reference
  740. * clock rate.
  741. */
  742. rate = clk_get_rate(clk);
  743. for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
  744. if (rate == ssc_lookup[i].refclk_rate) {
  745. gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
  746. break;
  747. }
  748. }
  749. if (i == ARRAY_SIZE(ssc_lookup)) {
  750. dev_err(gtr_dev->dev,
  751. "Invalid rate %lu for reference clock %u\n",
  752. rate, refclk);
  753. return -EINVAL;
  754. }
  755. }
  756. return 0;
  757. }
  758. static int xpsgtr_probe(struct platform_device *pdev)
  759. {
  760. struct device_node *np = pdev->dev.of_node;
  761. struct xpsgtr_dev *gtr_dev;
  762. struct phy_provider *provider;
  763. unsigned int port;
  764. int ret;
  765. gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL);
  766. if (!gtr_dev)
  767. return -ENOMEM;
  768. gtr_dev->dev = &pdev->dev;
  769. platform_set_drvdata(pdev, gtr_dev);
  770. mutex_init(&gtr_dev->gtr_mutex);
  771. if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr"))
  772. gtr_dev->tx_term_fix =
  773. of_property_read_bool(np, "xlnx,tx-termination-fix");
  774. /* Acquire resources. */
  775. gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes");
  776. if (IS_ERR(gtr_dev->serdes))
  777. return PTR_ERR(gtr_dev->serdes);
  778. gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou");
  779. if (IS_ERR(gtr_dev->siou))
  780. return PTR_ERR(gtr_dev->siou);
  781. ret = xpsgtr_get_ref_clocks(gtr_dev);
  782. if (ret)
  783. return ret;
  784. /* Create PHYs. */
  785. for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) {
  786. struct xpsgtr_phy *gtr_phy = &gtr_dev->phys[port];
  787. struct phy *phy;
  788. gtr_phy->lane = port;
  789. gtr_phy->dev = gtr_dev;
  790. phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops);
  791. if (IS_ERR(phy)) {
  792. dev_err(&pdev->dev, "failed to create PHY\n");
  793. return PTR_ERR(phy);
  794. }
  795. gtr_phy->phy = phy;
  796. phy_set_drvdata(phy, gtr_phy);
  797. }
  798. /* Register the PHY provider. */
  799. provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate);
  800. if (IS_ERR(provider)) {
  801. dev_err(&pdev->dev, "registering provider failed\n");
  802. return PTR_ERR(provider);
  803. }
  804. return 0;
  805. }
  806. static const struct of_device_id xpsgtr_of_match[] = {
  807. { .compatible = "xlnx,zynqmp-psgtr", },
  808. { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
  809. {},
  810. };
  811. MODULE_DEVICE_TABLE(of, xpsgtr_of_match);
  812. static struct platform_driver xpsgtr_driver = {
  813. .probe = xpsgtr_probe,
  814. .driver = {
  815. .name = "xilinx-psgtr",
  816. .of_match_table = xpsgtr_of_match,
  817. .pm = &xpsgtr_pm_ops,
  818. },
  819. };
  820. module_platform_driver(xpsgtr_driver);
  821. MODULE_AUTHOR("Xilinx Inc.");
  822. MODULE_LICENSE("GPL v2");
  823. MODULE_DESCRIPTION("Xilinx ZynqMP High speed Gigabit Transceiver");