phy-twl4030-usb.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
  4. *
  5. * Copyright (C) 2004-2007 Texas Instruments
  6. * Copyright (C) 2008 Nokia Corporation
  7. * Contact: Felipe Balbi <felipe.balbi@nokia.com>
  8. *
  9. * Current status:
  10. * - HS USB ULPI mode works.
  11. * - 3-pin mode support may be added in future.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/workqueue.h>
  18. #include <linux/io.h>
  19. #include <linux/delay.h>
  20. #include <linux/usb/otg.h>
  21. #include <linux/phy/phy.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/usb/musb.h>
  24. #include <linux/usb/ulpi.h>
  25. #include <linux/mfd/twl.h>
  26. #include <linux/regulator/consumer.h>
  27. #include <linux/err.h>
  28. #include <linux/slab.h>
  29. /* Register defines */
  30. #define MCPC_CTRL 0x30
  31. #define MCPC_CTRL_RTSOL (1 << 7)
  32. #define MCPC_CTRL_EXTSWR (1 << 6)
  33. #define MCPC_CTRL_EXTSWC (1 << 5)
  34. #define MCPC_CTRL_VOICESW (1 << 4)
  35. #define MCPC_CTRL_OUT64K (1 << 3)
  36. #define MCPC_CTRL_RTSCTSSW (1 << 2)
  37. #define MCPC_CTRL_HS_UART (1 << 0)
  38. #define MCPC_IO_CTRL 0x33
  39. #define MCPC_IO_CTRL_MICBIASEN (1 << 5)
  40. #define MCPC_IO_CTRL_CTS_NPU (1 << 4)
  41. #define MCPC_IO_CTRL_RXD_PU (1 << 3)
  42. #define MCPC_IO_CTRL_TXDTYP (1 << 2)
  43. #define MCPC_IO_CTRL_CTSTYP (1 << 1)
  44. #define MCPC_IO_CTRL_RTSTYP (1 << 0)
  45. #define MCPC_CTRL2 0x36
  46. #define MCPC_CTRL2_MCPC_CK_EN (1 << 0)
  47. #define OTHER_FUNC_CTRL 0x80
  48. #define OTHER_FUNC_CTRL_BDIS_ACON_EN (1 << 4)
  49. #define OTHER_FUNC_CTRL_FIVEWIRE_MODE (1 << 2)
  50. #define OTHER_IFC_CTRL 0x83
  51. #define OTHER_IFC_CTRL_OE_INT_EN (1 << 6)
  52. #define OTHER_IFC_CTRL_CEA2011_MODE (1 << 5)
  53. #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN (1 << 4)
  54. #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT (1 << 3)
  55. #define OTHER_IFC_CTRL_HIZ_ULPI (1 << 2)
  56. #define OTHER_IFC_CTRL_ALT_INT_REROUTE (1 << 0)
  57. #define OTHER_INT_EN_RISE 0x86
  58. #define OTHER_INT_EN_FALL 0x89
  59. #define OTHER_INT_STS 0x8C
  60. #define OTHER_INT_LATCH 0x8D
  61. #define OTHER_INT_VB_SESS_VLD (1 << 7)
  62. #define OTHER_INT_DM_HI (1 << 6) /* not valid for "latch" reg */
  63. #define OTHER_INT_DP_HI (1 << 5) /* not valid for "latch" reg */
  64. #define OTHER_INT_BDIS_ACON (1 << 3) /* not valid for "fall" regs */
  65. #define OTHER_INT_MANU (1 << 1)
  66. #define OTHER_INT_ABNORMAL_STRESS (1 << 0)
  67. #define ID_STATUS 0x96
  68. #define ID_RES_FLOAT (1 << 4)
  69. #define ID_RES_440K (1 << 3)
  70. #define ID_RES_200K (1 << 2)
  71. #define ID_RES_102K (1 << 1)
  72. #define ID_RES_GND (1 << 0)
  73. #define POWER_CTRL 0xAC
  74. #define POWER_CTRL_OTG_ENAB (1 << 5)
  75. #define OTHER_IFC_CTRL2 0xAF
  76. #define OTHER_IFC_CTRL2_ULPI_STP_LOW (1 << 4)
  77. #define OTHER_IFC_CTRL2_ULPI_TXEN_POL (1 << 3)
  78. #define OTHER_IFC_CTRL2_ULPI_4PIN_2430 (1 << 2)
  79. #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK (3 << 0) /* bits 0 and 1 */
  80. #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N (0 << 0)
  81. #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N (1 << 0)
  82. #define REG_CTRL_EN 0xB2
  83. #define REG_CTRL_ERROR 0xB5
  84. #define ULPI_I2C_CONFLICT_INTEN (1 << 0)
  85. #define OTHER_FUNC_CTRL2 0xB8
  86. #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN (1 << 0)
  87. /* following registers do not have separate _clr and _set registers */
  88. #define VBUS_DEBOUNCE 0xC0
  89. #define ID_DEBOUNCE 0xC1
  90. #define VBAT_TIMER 0xD3
  91. #define PHY_PWR_CTRL 0xFD
  92. #define PHY_PWR_PHYPWD (1 << 0)
  93. #define PHY_CLK_CTRL 0xFE
  94. #define PHY_CLK_CTRL_CLOCKGATING_EN (1 << 2)
  95. #define PHY_CLK_CTRL_CLK32K_EN (1 << 1)
  96. #define REQ_PHY_DPLL_CLK (1 << 0)
  97. #define PHY_CLK_CTRL_STS 0xFF
  98. #define PHY_DPLL_CLK (1 << 0)
  99. /* In module TWL_MODULE_PM_MASTER */
  100. #define STS_HW_CONDITIONS 0x0F
  101. /* In module TWL_MODULE_PM_RECEIVER */
  102. #define VUSB_DEDICATED1 0x7D
  103. #define VUSB_DEDICATED2 0x7E
  104. #define VUSB1V5_DEV_GRP 0x71
  105. #define VUSB1V5_TYPE 0x72
  106. #define VUSB1V5_REMAP 0x73
  107. #define VUSB1V8_DEV_GRP 0x74
  108. #define VUSB1V8_TYPE 0x75
  109. #define VUSB1V8_REMAP 0x76
  110. #define VUSB3V1_DEV_GRP 0x77
  111. #define VUSB3V1_TYPE 0x78
  112. #define VUSB3V1_REMAP 0x79
  113. /* In module TWL4030_MODULE_INTBR */
  114. #define PMBR1 0x0D
  115. #define GPIO_USB_4PIN_ULPI_2430C (3 << 0)
  116. static irqreturn_t twl4030_usb_irq(int irq, void *_twl);
  117. /*
  118. * If VBUS is valid or ID is ground, then we know a
  119. * cable is present and we need to be runtime-enabled
  120. */
  121. static inline bool cable_present(enum musb_vbus_id_status stat)
  122. {
  123. return stat == MUSB_VBUS_VALID ||
  124. stat == MUSB_ID_GROUND;
  125. }
  126. struct twl4030_usb {
  127. struct usb_phy phy;
  128. struct device *dev;
  129. /* TWL4030 internal USB regulator supplies */
  130. struct regulator *usb1v5;
  131. struct regulator *usb1v8;
  132. struct regulator *usb3v1;
  133. /* for vbus reporting with irqs disabled */
  134. struct mutex lock;
  135. /* pin configuration */
  136. enum twl4030_usb_mode usb_mode;
  137. int irq;
  138. enum musb_vbus_id_status linkstat;
  139. atomic_t connected;
  140. bool vbus_supplied;
  141. bool musb_mailbox_pending;
  142. struct delayed_work id_workaround_work;
  143. };
  144. /* internal define on top of container_of */
  145. #define phy_to_twl(x) container_of((x), struct twl4030_usb, phy)
  146. /*-------------------------------------------------------------------------*/
  147. static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
  148. u8 module, u8 data, u8 address)
  149. {
  150. u8 check = 0xFF;
  151. if ((twl_i2c_write_u8(module, data, address) >= 0) &&
  152. (twl_i2c_read_u8(module, &check, address) >= 0) &&
  153. (check == data))
  154. return 0;
  155. dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
  156. 1, module, address, check, data);
  157. /* Failed once: Try again */
  158. if ((twl_i2c_write_u8(module, data, address) >= 0) &&
  159. (twl_i2c_read_u8(module, &check, address) >= 0) &&
  160. (check == data))
  161. return 0;
  162. dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
  163. 2, module, address, check, data);
  164. /* Failed again: Return error */
  165. return -EBUSY;
  166. }
  167. #define twl4030_usb_write_verify(twl, address, data) \
  168. twl4030_i2c_write_u8_verify(twl, TWL_MODULE_USB, (data), (address))
  169. static inline int twl4030_usb_write(struct twl4030_usb *twl,
  170. u8 address, u8 data)
  171. {
  172. int ret = 0;
  173. ret = twl_i2c_write_u8(TWL_MODULE_USB, data, address);
  174. if (ret < 0)
  175. dev_dbg(twl->dev,
  176. "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
  177. return ret;
  178. }
  179. static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
  180. {
  181. u8 data;
  182. int ret = 0;
  183. ret = twl_i2c_read_u8(module, &data, address);
  184. if (ret >= 0)
  185. ret = data;
  186. else
  187. dev_dbg(twl->dev,
  188. "TWL4030:readb[0x%x,0x%x] Error %d\n",
  189. module, address, ret);
  190. return ret;
  191. }
  192. static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
  193. {
  194. return twl4030_readb(twl, TWL_MODULE_USB, address);
  195. }
  196. /*-------------------------------------------------------------------------*/
  197. static inline int
  198. twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
  199. {
  200. return twl4030_usb_write(twl, ULPI_SET(reg), bits);
  201. }
  202. static inline int
  203. twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
  204. {
  205. return twl4030_usb_write(twl, ULPI_CLR(reg), bits);
  206. }
  207. /*-------------------------------------------------------------------------*/
  208. static bool twl4030_is_driving_vbus(struct twl4030_usb *twl)
  209. {
  210. int ret;
  211. ret = twl4030_usb_read(twl, PHY_CLK_CTRL_STS);
  212. if (ret < 0 || !(ret & PHY_DPLL_CLK))
  213. /*
  214. * if clocks are off, registers are not updated,
  215. * but we can assume we don't drive VBUS in this case
  216. */
  217. return false;
  218. ret = twl4030_usb_read(twl, ULPI_OTG_CTRL);
  219. if (ret < 0)
  220. return false;
  221. return (ret & (ULPI_OTG_DRVVBUS | ULPI_OTG_CHRGVBUS)) ? true : false;
  222. }
  223. static enum musb_vbus_id_status
  224. twl4030_usb_linkstat(struct twl4030_usb *twl)
  225. {
  226. int status;
  227. enum musb_vbus_id_status linkstat = MUSB_UNKNOWN;
  228. twl->vbus_supplied = false;
  229. /*
  230. * For ID/VBUS sensing, see manual section 15.4.8 ...
  231. * except when using only battery backup power, two
  232. * comparators produce VBUS_PRES and ID_PRES signals,
  233. * which don't match docs elsewhere. But ... BIT(7)
  234. * and BIT(2) of STS_HW_CONDITIONS, respectively, do
  235. * seem to match up. If either is true the USB_PRES
  236. * signal is active, the OTG module is activated, and
  237. * its interrupt may be raised (may wake the system).
  238. */
  239. status = twl4030_readb(twl, TWL_MODULE_PM_MASTER, STS_HW_CONDITIONS);
  240. if (status < 0)
  241. dev_err(twl->dev, "USB link status err %d\n", status);
  242. else if (status & (BIT(7) | BIT(2))) {
  243. if (status & BIT(7)) {
  244. if (twl4030_is_driving_vbus(twl))
  245. status &= ~BIT(7);
  246. else
  247. twl->vbus_supplied = true;
  248. }
  249. if (status & BIT(2))
  250. linkstat = MUSB_ID_GROUND;
  251. else if (status & BIT(7))
  252. linkstat = MUSB_VBUS_VALID;
  253. else
  254. linkstat = MUSB_VBUS_OFF;
  255. } else {
  256. if (twl->linkstat != MUSB_UNKNOWN)
  257. linkstat = MUSB_VBUS_OFF;
  258. }
  259. kobject_uevent(&twl->dev->kobj, linkstat == MUSB_VBUS_VALID
  260. ? KOBJ_ONLINE : KOBJ_OFFLINE);
  261. dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
  262. status, status, linkstat);
  263. /* REVISIT this assumes host and peripheral controllers
  264. * are registered, and that both are active...
  265. */
  266. return linkstat;
  267. }
  268. static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
  269. {
  270. twl->usb_mode = mode;
  271. switch (mode) {
  272. case T2_USB_MODE_ULPI:
  273. twl4030_usb_clear_bits(twl, ULPI_IFC_CTRL,
  274. ULPI_IFC_CTRL_CARKITMODE);
  275. twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
  276. twl4030_usb_clear_bits(twl, ULPI_FUNC_CTRL,
  277. ULPI_FUNC_CTRL_XCVRSEL_MASK |
  278. ULPI_FUNC_CTRL_OPMODE_MASK);
  279. break;
  280. case -1:
  281. /* FIXME: power on defaults */
  282. break;
  283. default:
  284. dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
  285. mode);
  286. break;
  287. }
  288. }
  289. static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
  290. {
  291. unsigned long timeout;
  292. int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
  293. if (val >= 0) {
  294. if (on) {
  295. /* enable DPLL to access PHY registers over I2C */
  296. val |= REQ_PHY_DPLL_CLK;
  297. WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
  298. (u8)val) < 0);
  299. timeout = jiffies + HZ;
  300. while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
  301. PHY_DPLL_CLK)
  302. && time_before(jiffies, timeout))
  303. udelay(10);
  304. if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
  305. PHY_DPLL_CLK))
  306. dev_err(twl->dev, "Timeout setting T2 HSUSB "
  307. "PHY DPLL clock\n");
  308. } else {
  309. /* let ULPI control the DPLL clock */
  310. val &= ~REQ_PHY_DPLL_CLK;
  311. WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
  312. (u8)val) < 0);
  313. }
  314. }
  315. }
  316. static void __twl4030_phy_power(struct twl4030_usb *twl, int on)
  317. {
  318. u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
  319. if (on)
  320. pwr &= ~PHY_PWR_PHYPWD;
  321. else
  322. pwr |= PHY_PWR_PHYPWD;
  323. WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
  324. }
  325. static int __maybe_unused twl4030_usb_suspend(struct device *dev)
  326. {
  327. struct twl4030_usb *twl = dev_get_drvdata(dev);
  328. /*
  329. * we need enabled runtime on resume,
  330. * so turn irq off here, so we do not get it early
  331. * note: wakeup on usb plug works independently of this
  332. */
  333. dev_dbg(twl->dev, "%s\n", __func__);
  334. disable_irq(twl->irq);
  335. return 0;
  336. }
  337. static int __maybe_unused twl4030_usb_resume(struct device *dev)
  338. {
  339. struct twl4030_usb *twl = dev_get_drvdata(dev);
  340. dev_dbg(twl->dev, "%s\n", __func__);
  341. enable_irq(twl->irq);
  342. /* check whether cable status changed */
  343. twl4030_usb_irq(0, twl);
  344. return 0;
  345. }
  346. static int __maybe_unused twl4030_usb_runtime_suspend(struct device *dev)
  347. {
  348. struct twl4030_usb *twl = dev_get_drvdata(dev);
  349. dev_dbg(twl->dev, "%s\n", __func__);
  350. __twl4030_phy_power(twl, 0);
  351. regulator_disable(twl->usb1v5);
  352. regulator_disable(twl->usb1v8);
  353. regulator_disable(twl->usb3v1);
  354. return 0;
  355. }
  356. static int __maybe_unused twl4030_usb_runtime_resume(struct device *dev)
  357. {
  358. struct twl4030_usb *twl = dev_get_drvdata(dev);
  359. int res;
  360. dev_dbg(twl->dev, "%s\n", __func__);
  361. res = regulator_enable(twl->usb3v1);
  362. if (res)
  363. dev_err(twl->dev, "Failed to enable usb3v1\n");
  364. res = regulator_enable(twl->usb1v8);
  365. if (res)
  366. dev_err(twl->dev, "Failed to enable usb1v8\n");
  367. /*
  368. * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
  369. * in twl4030) resets the VUSB_DEDICATED2 register. This reset
  370. * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
  371. * SLEEP. We work around this by clearing the bit after usv3v1
  372. * is re-activated. This ensures that VUSB3V1 is really active.
  373. */
  374. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
  375. res = regulator_enable(twl->usb1v5);
  376. if (res)
  377. dev_err(twl->dev, "Failed to enable usb1v5\n");
  378. __twl4030_phy_power(twl, 1);
  379. twl4030_usb_write(twl, PHY_CLK_CTRL,
  380. twl4030_usb_read(twl, PHY_CLK_CTRL) |
  381. (PHY_CLK_CTRL_CLOCKGATING_EN |
  382. PHY_CLK_CTRL_CLK32K_EN));
  383. twl4030_i2c_access(twl, 1);
  384. twl4030_usb_set_mode(twl, twl->usb_mode);
  385. if (twl->usb_mode == T2_USB_MODE_ULPI)
  386. twl4030_i2c_access(twl, 0);
  387. /*
  388. * According to the TPS65950 TRM, there has to be at least 50ms
  389. * delay between setting POWER_CTRL_OTG_ENAB and enabling charging
  390. * so wait here so that a fully enabled phy can be expected after
  391. * resume
  392. */
  393. msleep(50);
  394. return 0;
  395. }
  396. static int twl4030_phy_power_off(struct phy *phy)
  397. {
  398. struct twl4030_usb *twl = phy_get_drvdata(phy);
  399. dev_dbg(twl->dev, "%s\n", __func__);
  400. return 0;
  401. }
  402. static int twl4030_phy_power_on(struct phy *phy)
  403. {
  404. struct twl4030_usb *twl = phy_get_drvdata(phy);
  405. dev_dbg(twl->dev, "%s\n", __func__);
  406. pm_runtime_get_sync(twl->dev);
  407. schedule_delayed_work(&twl->id_workaround_work, HZ);
  408. pm_runtime_mark_last_busy(twl->dev);
  409. pm_runtime_put_autosuspend(twl->dev);
  410. return 0;
  411. }
  412. static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
  413. {
  414. /* Enable writing to power configuration registers */
  415. twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG1,
  416. TWL4030_PM_MASTER_PROTECT_KEY);
  417. twl_i2c_write_u8(TWL_MODULE_PM_MASTER, TWL4030_PM_MASTER_KEY_CFG2,
  418. TWL4030_PM_MASTER_PROTECT_KEY);
  419. /* Keep VUSB3V1 LDO in sleep state until VBUS/ID change detected*/
  420. /*twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);*/
  421. /* input to VUSB3V1 LDO is from VBAT, not VBUS */
  422. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
  423. /* Initialize 3.1V regulator */
  424. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
  425. twl->usb3v1 = devm_regulator_get(twl->dev, "usb3v1");
  426. if (IS_ERR(twl->usb3v1))
  427. return -ENODEV;
  428. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
  429. /* Initialize 1.5V regulator */
  430. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
  431. twl->usb1v5 = devm_regulator_get(twl->dev, "usb1v5");
  432. if (IS_ERR(twl->usb1v5))
  433. return -ENODEV;
  434. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
  435. /* Initialize 1.8V regulator */
  436. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
  437. twl->usb1v8 = devm_regulator_get(twl->dev, "usb1v8");
  438. if (IS_ERR(twl->usb1v8))
  439. return -ENODEV;
  440. twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
  441. /* disable access to power configuration registers */
  442. twl_i2c_write_u8(TWL_MODULE_PM_MASTER, 0,
  443. TWL4030_PM_MASTER_PROTECT_KEY);
  444. return 0;
  445. }
  446. static ssize_t twl4030_usb_vbus_show(struct device *dev,
  447. struct device_attribute *attr, char *buf)
  448. {
  449. struct twl4030_usb *twl = dev_get_drvdata(dev);
  450. int ret = -EINVAL;
  451. mutex_lock(&twl->lock);
  452. ret = sprintf(buf, "%s\n",
  453. twl->vbus_supplied ? "on" : "off");
  454. mutex_unlock(&twl->lock);
  455. return ret;
  456. }
  457. static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
  458. static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
  459. {
  460. struct twl4030_usb *twl = _twl;
  461. enum musb_vbus_id_status status;
  462. int err;
  463. status = twl4030_usb_linkstat(twl);
  464. mutex_lock(&twl->lock);
  465. twl->linkstat = status;
  466. mutex_unlock(&twl->lock);
  467. if (cable_present(status)) {
  468. if (atomic_add_unless(&twl->connected, 1, 1)) {
  469. dev_dbg(twl->dev, "%s: cable connected %i\n",
  470. __func__, status);
  471. pm_runtime_get_sync(twl->dev);
  472. twl->musb_mailbox_pending = true;
  473. }
  474. } else {
  475. if (atomic_add_unless(&twl->connected, -1, 0)) {
  476. dev_dbg(twl->dev, "%s: cable disconnected %i\n",
  477. __func__, status);
  478. pm_runtime_mark_last_busy(twl->dev);
  479. pm_runtime_put_autosuspend(twl->dev);
  480. twl->musb_mailbox_pending = true;
  481. }
  482. }
  483. if (twl->musb_mailbox_pending) {
  484. err = musb_mailbox(status);
  485. if (!err)
  486. twl->musb_mailbox_pending = false;
  487. }
  488. /* don't schedule during sleep - irq works right then */
  489. if (status == MUSB_ID_GROUND && pm_runtime_active(twl->dev)) {
  490. cancel_delayed_work(&twl->id_workaround_work);
  491. schedule_delayed_work(&twl->id_workaround_work, HZ);
  492. }
  493. if (irq)
  494. sysfs_notify(&twl->dev->kobj, NULL, "vbus");
  495. return IRQ_HANDLED;
  496. }
  497. static void twl4030_id_workaround_work(struct work_struct *work)
  498. {
  499. struct twl4030_usb *twl = container_of(work, struct twl4030_usb,
  500. id_workaround_work.work);
  501. twl4030_usb_irq(0, twl);
  502. }
  503. static int twl4030_phy_init(struct phy *phy)
  504. {
  505. struct twl4030_usb *twl = phy_get_drvdata(phy);
  506. pm_runtime_get_sync(twl->dev);
  507. twl->linkstat = MUSB_UNKNOWN;
  508. schedule_delayed_work(&twl->id_workaround_work, HZ);
  509. pm_runtime_mark_last_busy(twl->dev);
  510. pm_runtime_put_autosuspend(twl->dev);
  511. return 0;
  512. }
  513. static int twl4030_set_peripheral(struct usb_otg *otg,
  514. struct usb_gadget *gadget)
  515. {
  516. if (!otg)
  517. return -ENODEV;
  518. otg->gadget = gadget;
  519. if (!gadget)
  520. otg->state = OTG_STATE_UNDEFINED;
  521. return 0;
  522. }
  523. static int twl4030_set_host(struct usb_otg *otg, struct usb_bus *host)
  524. {
  525. if (!otg)
  526. return -ENODEV;
  527. otg->host = host;
  528. if (!host)
  529. otg->state = OTG_STATE_UNDEFINED;
  530. return 0;
  531. }
  532. static const struct phy_ops ops = {
  533. .init = twl4030_phy_init,
  534. .power_on = twl4030_phy_power_on,
  535. .power_off = twl4030_phy_power_off,
  536. .owner = THIS_MODULE,
  537. };
  538. static const struct dev_pm_ops twl4030_usb_pm_ops = {
  539. SET_RUNTIME_PM_OPS(twl4030_usb_runtime_suspend,
  540. twl4030_usb_runtime_resume, NULL)
  541. SET_SYSTEM_SLEEP_PM_OPS(twl4030_usb_suspend, twl4030_usb_resume)
  542. };
  543. static int twl4030_usb_probe(struct platform_device *pdev)
  544. {
  545. struct twl4030_usb_data *pdata = dev_get_platdata(&pdev->dev);
  546. struct twl4030_usb *twl;
  547. struct phy *phy;
  548. int status, err;
  549. struct usb_otg *otg;
  550. struct device_node *np = pdev->dev.of_node;
  551. struct phy_provider *phy_provider;
  552. twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
  553. if (!twl)
  554. return -ENOMEM;
  555. if (np)
  556. of_property_read_u32(np, "usb_mode",
  557. (enum twl4030_usb_mode *)&twl->usb_mode);
  558. else if (pdata) {
  559. twl->usb_mode = pdata->usb_mode;
  560. } else {
  561. dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
  562. return -EINVAL;
  563. }
  564. otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
  565. if (!otg)
  566. return -ENOMEM;
  567. twl->dev = &pdev->dev;
  568. twl->irq = platform_get_irq(pdev, 0);
  569. twl->vbus_supplied = false;
  570. twl->linkstat = MUSB_UNKNOWN;
  571. twl->musb_mailbox_pending = false;
  572. twl->phy.dev = twl->dev;
  573. twl->phy.label = "twl4030";
  574. twl->phy.otg = otg;
  575. twl->phy.type = USB_PHY_TYPE_USB2;
  576. otg->usb_phy = &twl->phy;
  577. otg->set_host = twl4030_set_host;
  578. otg->set_peripheral = twl4030_set_peripheral;
  579. phy = devm_phy_create(twl->dev, NULL, &ops);
  580. if (IS_ERR(phy)) {
  581. dev_dbg(&pdev->dev, "Failed to create PHY\n");
  582. return PTR_ERR(phy);
  583. }
  584. phy_set_drvdata(phy, twl);
  585. phy_provider = devm_of_phy_provider_register(twl->dev,
  586. of_phy_simple_xlate);
  587. if (IS_ERR(phy_provider))
  588. return PTR_ERR(phy_provider);
  589. /* init mutex for workqueue */
  590. mutex_init(&twl->lock);
  591. INIT_DELAYED_WORK(&twl->id_workaround_work, twl4030_id_workaround_work);
  592. err = twl4030_usb_ldo_init(twl);
  593. if (err) {
  594. dev_err(&pdev->dev, "ldo init failed\n");
  595. return err;
  596. }
  597. usb_add_phy_dev(&twl->phy);
  598. platform_set_drvdata(pdev, twl);
  599. if (device_create_file(&pdev->dev, &dev_attr_vbus))
  600. dev_warn(&pdev->dev, "could not create sysfs file\n");
  601. ATOMIC_INIT_NOTIFIER_HEAD(&twl->phy.notifier);
  602. pm_runtime_use_autosuspend(&pdev->dev);
  603. pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
  604. pm_runtime_enable(&pdev->dev);
  605. pm_runtime_get_sync(&pdev->dev);
  606. /* Our job is to use irqs and status from the power module
  607. * to keep the transceiver disabled when nothing's connected.
  608. *
  609. * FIXME we actually shouldn't start enabling it until the
  610. * USB controller drivers have said they're ready, by calling
  611. * set_host() and/or set_peripheral() ... OTG_capable boards
  612. * need both handles, otherwise just one suffices.
  613. */
  614. status = devm_request_threaded_irq(twl->dev, twl->irq, NULL,
  615. twl4030_usb_irq, IRQF_TRIGGER_FALLING |
  616. IRQF_TRIGGER_RISING | IRQF_ONESHOT, "twl4030_usb", twl);
  617. if (status < 0) {
  618. dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
  619. twl->irq, status);
  620. return status;
  621. }
  622. if (pdata)
  623. err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
  624. if (err)
  625. return err;
  626. pm_runtime_mark_last_busy(&pdev->dev);
  627. pm_runtime_put_autosuspend(twl->dev);
  628. dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
  629. return 0;
  630. }
  631. static int twl4030_usb_remove(struct platform_device *pdev)
  632. {
  633. struct twl4030_usb *twl = platform_get_drvdata(pdev);
  634. int val;
  635. usb_remove_phy(&twl->phy);
  636. pm_runtime_get_sync(twl->dev);
  637. cancel_delayed_work_sync(&twl->id_workaround_work);
  638. device_remove_file(twl->dev, &dev_attr_vbus);
  639. /* set transceiver mode to power on defaults */
  640. twl4030_usb_set_mode(twl, -1);
  641. /* idle ulpi before powering off */
  642. if (cable_present(twl->linkstat))
  643. pm_runtime_put_noidle(twl->dev);
  644. pm_runtime_mark_last_busy(twl->dev);
  645. pm_runtime_dont_use_autosuspend(&pdev->dev);
  646. pm_runtime_put_sync(twl->dev);
  647. pm_runtime_disable(twl->dev);
  648. /* autogate 60MHz ULPI clock,
  649. * clear dpll clock request for i2c access,
  650. * disable 32KHz
  651. */
  652. val = twl4030_usb_read(twl, PHY_CLK_CTRL);
  653. if (val >= 0) {
  654. val |= PHY_CLK_CTRL_CLOCKGATING_EN;
  655. val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
  656. twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
  657. }
  658. /* disable complete OTG block */
  659. twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
  660. return 0;
  661. }
  662. #ifdef CONFIG_OF
  663. static const struct of_device_id twl4030_usb_id_table[] = {
  664. { .compatible = "ti,twl4030-usb" },
  665. {}
  666. };
  667. MODULE_DEVICE_TABLE(of, twl4030_usb_id_table);
  668. #endif
  669. static struct platform_driver twl4030_usb_driver = {
  670. .probe = twl4030_usb_probe,
  671. .remove = twl4030_usb_remove,
  672. .driver = {
  673. .name = "twl4030_usb",
  674. .pm = &twl4030_usb_pm_ops,
  675. .of_match_table = of_match_ptr(twl4030_usb_id_table),
  676. },
  677. };
  678. static int __init twl4030_usb_init(void)
  679. {
  680. return platform_driver_register(&twl4030_usb_driver);
  681. }
  682. subsys_initcall(twl4030_usb_init);
  683. static void __exit twl4030_usb_exit(void)
  684. {
  685. platform_driver_unregister(&twl4030_usb_driver);
  686. }
  687. module_exit(twl4030_usb_exit);
  688. MODULE_ALIAS("platform:twl4030_usb");
  689. MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
  690. MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
  691. MODULE_LICENSE("GPL");