phy-ti-pipe3.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * phy-ti-pipe3 - PIPE3 PHY driver.
  4. *
  5. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
  6. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7. */
  8. #include <linux/module.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/slab.h>
  11. #include <linux/phy/phy.h>
  12. #include <linux/of.h>
  13. #include <linux/clk.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/delay.h>
  18. #include <linux/phy/omap_control_phy.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/mfd/syscon.h>
  21. #include <linux/regmap.h>
  22. #define PLL_STATUS 0x00000004
  23. #define PLL_GO 0x00000008
  24. #define PLL_CONFIGURATION1 0x0000000C
  25. #define PLL_CONFIGURATION2 0x00000010
  26. #define PLL_CONFIGURATION3 0x00000014
  27. #define PLL_CONFIGURATION4 0x00000020
  28. #define PLL_REGM_MASK 0x001FFE00
  29. #define PLL_REGM_SHIFT 0x9
  30. #define PLL_REGM_F_MASK 0x0003FFFF
  31. #define PLL_REGM_F_SHIFT 0x0
  32. #define PLL_REGN_MASK 0x000001FE
  33. #define PLL_REGN_SHIFT 0x1
  34. #define PLL_SELFREQDCO_MASK 0x0000000E
  35. #define PLL_SELFREQDCO_SHIFT 0x1
  36. #define PLL_SD_MASK 0x0003FC00
  37. #define PLL_SD_SHIFT 10
  38. #define SET_PLL_GO 0x1
  39. #define PLL_LDOPWDN BIT(15)
  40. #define PLL_TICOPWDN BIT(16)
  41. #define PLL_LOCK 0x2
  42. #define PLL_IDLE 0x1
  43. #define SATA_PLL_SOFT_RESET BIT(18)
  44. #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
  45. #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
  46. #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
  47. #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  48. #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  49. #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  50. #define PCIE_PCS_MASK 0xFF0000
  51. #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
  52. #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
  53. #define INTERFACE_MASK GENMASK(31, 27)
  54. #define INTERFACE_SHIFT 27
  55. #define INTERFACE_MODE_USBSS BIT(4)
  56. #define INTERFACE_MODE_SATA_1P5 BIT(3)
  57. #define INTERFACE_MODE_SATA_3P0 BIT(2)
  58. #define INTERFACE_MODE_PCIE BIT(0)
  59. #define LOSD_MASK GENMASK(17, 14)
  60. #define LOSD_SHIFT 14
  61. #define MEM_PLLDIV GENMASK(6, 5)
  62. #define PIPE3_PHY_RX_TRIM 0x0000001C
  63. #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
  64. #define MEM_DLL_TRIM_SHIFT 30
  65. #define PIPE3_PHY_RX_DLL 0x00000024
  66. #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
  67. #define MEM_DLL_PHINT_RATE_SHIFT 30
  68. #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
  69. #define MEM_HS_RATE_MASK GENMASK(28, 27)
  70. #define MEM_HS_RATE_SHIFT 27
  71. #define MEM_OVRD_HS_RATE BIT(26)
  72. #define MEM_OVRD_HS_RATE_SHIFT 26
  73. #define MEM_CDR_FASTLOCK BIT(23)
  74. #define MEM_CDR_FASTLOCK_SHIFT 23
  75. #define MEM_CDR_LBW_MASK GENMASK(22, 21)
  76. #define MEM_CDR_LBW_SHIFT 21
  77. #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
  78. #define MEM_CDR_STEPCNT_SHIFT 19
  79. #define MEM_CDR_STL_MASK GENMASK(18, 16)
  80. #define MEM_CDR_STL_SHIFT 16
  81. #define MEM_CDR_THR_MASK GENMASK(15, 13)
  82. #define MEM_CDR_THR_SHIFT 13
  83. #define MEM_CDR_THR_MODE BIT(12)
  84. #define MEM_CDR_THR_MODE_SHIFT 12
  85. #define MEM_CDR_2NDO_SDM_MODE BIT(11)
  86. #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
  87. #define PIPE3_PHY_RX_EQUALIZER 0x00000038
  88. #define MEM_EQLEV_MASK GENMASK(31, 16)
  89. #define MEM_EQLEV_SHIFT 16
  90. #define MEM_EQFTC_MASK GENMASK(15, 11)
  91. #define MEM_EQFTC_SHIFT 11
  92. #define MEM_EQCTL_MASK GENMASK(10, 7)
  93. #define MEM_EQCTL_SHIFT 7
  94. #define MEM_OVRD_EQLEV BIT(2)
  95. #define MEM_OVRD_EQLEV_SHIFT 2
  96. #define MEM_OVRD_EQFTC BIT(1)
  97. #define MEM_OVRD_EQFTC_SHIFT 1
  98. #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
  99. #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
  100. #define MEM_CDR_LOS_SOURCE_SHIFT 9
  101. /*
  102. * This is an Empirical value that works, need to confirm the actual
  103. * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
  104. * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
  105. */
  106. #define PLL_IDLE_TIME 100 /* in milliseconds */
  107. #define PLL_LOCK_TIME 100 /* in milliseconds */
  108. enum pipe3_mode { PIPE3_MODE_PCIE = 1,
  109. PIPE3_MODE_SATA,
  110. PIPE3_MODE_USBSS };
  111. struct pipe3_dpll_params {
  112. u16 m;
  113. u8 n;
  114. u8 freq:3;
  115. u8 sd;
  116. u32 mf;
  117. };
  118. struct pipe3_dpll_map {
  119. unsigned long rate;
  120. struct pipe3_dpll_params params;
  121. };
  122. struct pipe3_settings {
  123. u8 ana_interface;
  124. u8 ana_losd;
  125. u8 dig_fastlock;
  126. u8 dig_lbw;
  127. u8 dig_stepcnt;
  128. u8 dig_stl;
  129. u8 dig_thr;
  130. u8 dig_thr_mode;
  131. u8 dig_2ndo_sdm_mode;
  132. u8 dig_hs_rate;
  133. u8 dig_ovrd_hs_rate;
  134. u8 dll_trim_sel;
  135. u8 dll_phint_rate;
  136. u8 eq_lev;
  137. u8 eq_ftc;
  138. u8 eq_ctl;
  139. u8 eq_ovrd_lev;
  140. u8 eq_ovrd_ftc;
  141. };
  142. struct ti_pipe3 {
  143. void __iomem *pll_ctrl_base;
  144. void __iomem *phy_rx;
  145. void __iomem *phy_tx;
  146. struct device *dev;
  147. struct device *control_dev;
  148. struct clk *wkupclk;
  149. struct clk *sys_clk;
  150. struct clk *refclk;
  151. struct clk *div_clk;
  152. struct pipe3_dpll_map *dpll_map;
  153. struct regmap *phy_power_syscon; /* ctrl. reg. acces */
  154. struct regmap *pcs_syscon; /* ctrl. reg. acces */
  155. struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
  156. unsigned int dpll_reset_reg; /* reg. index within syscon */
  157. unsigned int power_reg; /* power reg. index within syscon */
  158. unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
  159. bool sata_refclk_enabled;
  160. enum pipe3_mode mode;
  161. struct pipe3_settings settings;
  162. };
  163. static struct pipe3_dpll_map dpll_map_usb[] = {
  164. {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
  165. {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
  166. {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
  167. {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
  168. {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
  169. {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
  170. { }, /* Terminator */
  171. };
  172. static struct pipe3_dpll_map dpll_map_sata[] = {
  173. {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
  174. {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
  175. {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
  176. {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
  177. {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
  178. {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
  179. { }, /* Terminator */
  180. };
  181. struct pipe3_data {
  182. enum pipe3_mode mode;
  183. struct pipe3_dpll_map *dpll_map;
  184. struct pipe3_settings settings;
  185. };
  186. static struct pipe3_data data_usb = {
  187. .mode = PIPE3_MODE_USBSS,
  188. .dpll_map = dpll_map_usb,
  189. .settings = {
  190. /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
  191. .ana_interface = INTERFACE_MODE_USBSS,
  192. .ana_losd = 0xa,
  193. .dig_fastlock = 1,
  194. .dig_lbw = 3,
  195. .dig_stepcnt = 0,
  196. .dig_stl = 0x3,
  197. .dig_thr = 1,
  198. .dig_thr_mode = 1,
  199. .dig_2ndo_sdm_mode = 0,
  200. .dig_hs_rate = 0,
  201. .dig_ovrd_hs_rate = 1,
  202. .dll_trim_sel = 0x2,
  203. .dll_phint_rate = 0x3,
  204. .eq_lev = 0,
  205. .eq_ftc = 0,
  206. .eq_ctl = 0x9,
  207. .eq_ovrd_lev = 0,
  208. .eq_ovrd_ftc = 0,
  209. },
  210. };
  211. static struct pipe3_data data_sata = {
  212. .mode = PIPE3_MODE_SATA,
  213. .dpll_map = dpll_map_sata,
  214. .settings = {
  215. /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
  216. .ana_interface = INTERFACE_MODE_SATA_3P0,
  217. .ana_losd = 0x5,
  218. .dig_fastlock = 1,
  219. .dig_lbw = 3,
  220. .dig_stepcnt = 0,
  221. .dig_stl = 0x3,
  222. .dig_thr = 1,
  223. .dig_thr_mode = 1,
  224. .dig_2ndo_sdm_mode = 0,
  225. .dig_hs_rate = 0, /* Not in TRM preferred settings */
  226. .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
  227. .dll_trim_sel = 0x1,
  228. .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
  229. .eq_lev = 0,
  230. .eq_ftc = 0x1f,
  231. .eq_ctl = 0,
  232. .eq_ovrd_lev = 1,
  233. .eq_ovrd_ftc = 1,
  234. },
  235. };
  236. static struct pipe3_data data_pcie = {
  237. .mode = PIPE3_MODE_PCIE,
  238. .settings = {
  239. /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
  240. .ana_interface = INTERFACE_MODE_PCIE,
  241. .ana_losd = 0xa,
  242. .dig_fastlock = 1,
  243. .dig_lbw = 3,
  244. .dig_stepcnt = 0,
  245. .dig_stl = 0x3,
  246. .dig_thr = 1,
  247. .dig_thr_mode = 1,
  248. .dig_2ndo_sdm_mode = 0,
  249. .dig_hs_rate = 0,
  250. .dig_ovrd_hs_rate = 0,
  251. .dll_trim_sel = 0x2,
  252. .dll_phint_rate = 0x3,
  253. .eq_lev = 0,
  254. .eq_ftc = 0x1f,
  255. .eq_ctl = 1,
  256. .eq_ovrd_lev = 0,
  257. .eq_ovrd_ftc = 0,
  258. },
  259. };
  260. static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
  261. {
  262. return __raw_readl(addr + offset);
  263. }
  264. static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
  265. u32 data)
  266. {
  267. __raw_writel(data, addr + offset);
  268. }
  269. static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
  270. {
  271. unsigned long rate;
  272. struct pipe3_dpll_map *dpll_map = phy->dpll_map;
  273. rate = clk_get_rate(phy->sys_clk);
  274. for (; dpll_map->rate; dpll_map++) {
  275. if (rate == dpll_map->rate)
  276. return &dpll_map->params;
  277. }
  278. dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
  279. return NULL;
  280. }
  281. static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
  282. static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
  283. static int ti_pipe3_power_off(struct phy *x)
  284. {
  285. int ret;
  286. struct ti_pipe3 *phy = phy_get_drvdata(x);
  287. if (!phy->phy_power_syscon) {
  288. omap_control_phy_power(phy->control_dev, 0);
  289. return 0;
  290. }
  291. ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
  292. PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0);
  293. return ret;
  294. }
  295. static void ti_pipe3_calibrate(struct ti_pipe3 *phy);
  296. static int ti_pipe3_power_on(struct phy *x)
  297. {
  298. u32 val;
  299. u32 mask;
  300. unsigned long rate;
  301. struct ti_pipe3 *phy = phy_get_drvdata(x);
  302. bool rx_pending = false;
  303. if (!phy->phy_power_syscon) {
  304. omap_control_phy_power(phy->control_dev, 1);
  305. return 0;
  306. }
  307. rate = clk_get_rate(phy->sys_clk);
  308. if (!rate) {
  309. dev_err(phy->dev, "Invalid clock rate\n");
  310. return -EINVAL;
  311. }
  312. rate = rate / 1000000;
  313. mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
  314. val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
  315. regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
  316. mask, val);
  317. /*
  318. * For PCIe, TX and RX must be powered on simultaneously.
  319. * For USB and SATA, TX must be powered on before RX
  320. */
  321. mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
  322. if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) {
  323. val = PIPE3_PHY_TX_POWERON;
  324. rx_pending = true;
  325. } else {
  326. val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
  327. }
  328. regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
  329. mask, val);
  330. if (rx_pending) {
  331. val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
  332. regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
  333. mask, val);
  334. }
  335. if (phy->mode == PIPE3_MODE_PCIE)
  336. ti_pipe3_calibrate(phy);
  337. return 0;
  338. }
  339. static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
  340. {
  341. u32 val;
  342. unsigned long timeout;
  343. timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
  344. do {
  345. cpu_relax();
  346. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  347. if (val & PLL_LOCK)
  348. return 0;
  349. } while (!time_after(jiffies, timeout));
  350. dev_err(phy->dev, "DPLL failed to lock\n");
  351. return -EBUSY;
  352. }
  353. static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
  354. {
  355. u32 val;
  356. struct pipe3_dpll_params *dpll_params;
  357. dpll_params = ti_pipe3_get_dpll_params(phy);
  358. if (!dpll_params)
  359. return -EINVAL;
  360. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  361. val &= ~PLL_REGN_MASK;
  362. val |= dpll_params->n << PLL_REGN_SHIFT;
  363. ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  364. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  365. val &= ~PLL_SELFREQDCO_MASK;
  366. val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
  367. ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  368. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
  369. val &= ~PLL_REGM_MASK;
  370. val |= dpll_params->m << PLL_REGM_SHIFT;
  371. ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
  372. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
  373. val &= ~PLL_REGM_F_MASK;
  374. val |= dpll_params->mf << PLL_REGM_F_SHIFT;
  375. ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
  376. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
  377. val &= ~PLL_SD_MASK;
  378. val |= dpll_params->sd << PLL_SD_SHIFT;
  379. ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
  380. ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
  381. return ti_pipe3_dpll_wait_lock(phy);
  382. }
  383. static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
  384. {
  385. u32 val;
  386. struct pipe3_settings *s = &phy->settings;
  387. val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
  388. val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
  389. val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
  390. ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
  391. val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
  392. val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
  393. MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
  394. MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
  395. val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
  396. s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
  397. s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
  398. s->dig_lbw << MEM_CDR_LBW_SHIFT |
  399. s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
  400. s->dig_stl << MEM_CDR_STL_SHIFT |
  401. s->dig_thr << MEM_CDR_THR_SHIFT |
  402. s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
  403. s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
  404. ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
  405. val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
  406. val &= ~MEM_DLL_TRIM_SEL_MASK;
  407. val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
  408. ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
  409. val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
  410. val &= ~MEM_DLL_PHINT_RATE_MASK;
  411. val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
  412. ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
  413. val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
  414. val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
  415. MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
  416. val |= s->eq_lev << MEM_EQLEV_SHIFT |
  417. s->eq_ftc << MEM_EQFTC_SHIFT |
  418. s->eq_ctl << MEM_EQCTL_SHIFT |
  419. s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
  420. s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
  421. ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
  422. if (phy->mode == PIPE3_MODE_SATA) {
  423. val = ti_pipe3_readl(phy->phy_rx,
  424. SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
  425. val &= ~MEM_CDR_LOS_SOURCE_MASK;
  426. ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
  427. val);
  428. }
  429. }
  430. static int ti_pipe3_init(struct phy *x)
  431. {
  432. struct ti_pipe3 *phy = phy_get_drvdata(x);
  433. u32 val;
  434. int ret = 0;
  435. ti_pipe3_enable_clocks(phy);
  436. /*
  437. * Set pcie_pcs register to 0x96 for proper functioning of phy
  438. * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
  439. * 18-1804.
  440. */
  441. if (phy->mode == PIPE3_MODE_PCIE) {
  442. if (!phy->pcs_syscon) {
  443. omap_control_pcie_pcs(phy->control_dev, 0x96);
  444. return 0;
  445. }
  446. val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
  447. ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
  448. PCIE_PCS_MASK, val);
  449. return ret;
  450. }
  451. /* Bring it out of IDLE if it is IDLE */
  452. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  453. if (val & PLL_IDLE) {
  454. val &= ~PLL_IDLE;
  455. ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  456. ret = ti_pipe3_dpll_wait_lock(phy);
  457. }
  458. /* SATA has issues if re-programmed when locked */
  459. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  460. if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
  461. return ret;
  462. /* Program the DPLL */
  463. ret = ti_pipe3_dpll_program(phy);
  464. if (ret) {
  465. ti_pipe3_disable_clocks(phy);
  466. return -EINVAL;
  467. }
  468. ti_pipe3_calibrate(phy);
  469. return ret;
  470. }
  471. static int ti_pipe3_exit(struct phy *x)
  472. {
  473. struct ti_pipe3 *phy = phy_get_drvdata(x);
  474. u32 val;
  475. unsigned long timeout;
  476. /* If dpll_reset_syscon is not present we wont power down SATA DPLL
  477. * due to Errata i783
  478. */
  479. if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
  480. return 0;
  481. /* PCIe doesn't have internal DPLL */
  482. if (phy->mode != PIPE3_MODE_PCIE) {
  483. /* Put DPLL in IDLE mode */
  484. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
  485. val |= PLL_IDLE;
  486. ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
  487. /* wait for LDO and Oscillator to power down */
  488. timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
  489. do {
  490. cpu_relax();
  491. val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
  492. if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
  493. break;
  494. } while (!time_after(jiffies, timeout));
  495. if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
  496. dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
  497. val);
  498. return -EBUSY;
  499. }
  500. }
  501. /* i783: SATA needs control bit toggle after PLL unlock */
  502. if (phy->mode == PIPE3_MODE_SATA) {
  503. regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
  504. SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
  505. regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
  506. SATA_PLL_SOFT_RESET, 0);
  507. }
  508. ti_pipe3_disable_clocks(phy);
  509. return 0;
  510. }
  511. static const struct phy_ops ops = {
  512. .init = ti_pipe3_init,
  513. .exit = ti_pipe3_exit,
  514. .power_on = ti_pipe3_power_on,
  515. .power_off = ti_pipe3_power_off,
  516. .owner = THIS_MODULE,
  517. };
  518. static const struct of_device_id ti_pipe3_id_table[];
  519. static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
  520. {
  521. struct clk *clk;
  522. struct device *dev = phy->dev;
  523. phy->refclk = devm_clk_get(dev, "refclk");
  524. if (IS_ERR(phy->refclk)) {
  525. dev_err(dev, "unable to get refclk\n");
  526. /* older DTBs have missing refclk in SATA PHY
  527. * so don't bail out in case of SATA PHY.
  528. */
  529. if (phy->mode != PIPE3_MODE_SATA)
  530. return PTR_ERR(phy->refclk);
  531. }
  532. if (phy->mode != PIPE3_MODE_SATA) {
  533. phy->wkupclk = devm_clk_get(dev, "wkupclk");
  534. if (IS_ERR(phy->wkupclk)) {
  535. dev_err(dev, "unable to get wkupclk\n");
  536. return PTR_ERR(phy->wkupclk);
  537. }
  538. } else {
  539. phy->wkupclk = ERR_PTR(-ENODEV);
  540. }
  541. if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) {
  542. phy->sys_clk = devm_clk_get(dev, "sysclk");
  543. if (IS_ERR(phy->sys_clk)) {
  544. dev_err(dev, "unable to get sysclk\n");
  545. return -EINVAL;
  546. }
  547. }
  548. if (phy->mode == PIPE3_MODE_PCIE) {
  549. clk = devm_clk_get(dev, "dpll_ref");
  550. if (IS_ERR(clk)) {
  551. dev_err(dev, "unable to get dpll ref clk\n");
  552. return PTR_ERR(clk);
  553. }
  554. clk_set_rate(clk, 1500000000);
  555. clk = devm_clk_get(dev, "dpll_ref_m2");
  556. if (IS_ERR(clk)) {
  557. dev_err(dev, "unable to get dpll ref m2 clk\n");
  558. return PTR_ERR(clk);
  559. }
  560. clk_set_rate(clk, 100000000);
  561. clk = devm_clk_get(dev, "phy-div");
  562. if (IS_ERR(clk)) {
  563. dev_err(dev, "unable to get phy-div clk\n");
  564. return PTR_ERR(clk);
  565. }
  566. clk_set_rate(clk, 100000000);
  567. phy->div_clk = devm_clk_get(dev, "div-clk");
  568. if (IS_ERR(phy->div_clk)) {
  569. dev_err(dev, "unable to get div-clk\n");
  570. return PTR_ERR(phy->div_clk);
  571. }
  572. } else {
  573. phy->div_clk = ERR_PTR(-ENODEV);
  574. }
  575. return 0;
  576. }
  577. static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
  578. {
  579. struct device *dev = phy->dev;
  580. struct device_node *node = dev->of_node;
  581. struct device_node *control_node;
  582. struct platform_device *control_pdev;
  583. phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
  584. "syscon-phy-power");
  585. if (IS_ERR(phy->phy_power_syscon)) {
  586. dev_dbg(dev,
  587. "can't get syscon-phy-power, using control device\n");
  588. phy->phy_power_syscon = NULL;
  589. } else {
  590. if (of_property_read_u32_index(node,
  591. "syscon-phy-power", 1,
  592. &phy->power_reg)) {
  593. dev_err(dev, "couldn't get power reg. offset\n");
  594. return -EINVAL;
  595. }
  596. }
  597. if (!phy->phy_power_syscon) {
  598. control_node = of_parse_phandle(node, "ctrl-module", 0);
  599. if (!control_node) {
  600. dev_err(dev, "Failed to get control device phandle\n");
  601. return -EINVAL;
  602. }
  603. control_pdev = of_find_device_by_node(control_node);
  604. if (!control_pdev) {
  605. dev_err(dev, "Failed to get control device\n");
  606. return -EINVAL;
  607. }
  608. phy->control_dev = &control_pdev->dev;
  609. }
  610. if (phy->mode == PIPE3_MODE_PCIE) {
  611. phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,
  612. "syscon-pcs");
  613. if (IS_ERR(phy->pcs_syscon)) {
  614. dev_dbg(dev,
  615. "can't get syscon-pcs, using omap control\n");
  616. phy->pcs_syscon = NULL;
  617. } else {
  618. if (of_property_read_u32_index(node,
  619. "syscon-pcs", 1,
  620. &phy->pcie_pcs_reg)) {
  621. dev_err(dev,
  622. "couldn't get pcie pcs reg. offset\n");
  623. return -EINVAL;
  624. }
  625. }
  626. }
  627. if (phy->mode == PIPE3_MODE_SATA) {
  628. phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
  629. "syscon-pllreset");
  630. if (IS_ERR(phy->dpll_reset_syscon)) {
  631. dev_info(dev,
  632. "can't get syscon-pllreset, sata dpll won't idle\n");
  633. phy->dpll_reset_syscon = NULL;
  634. } else {
  635. if (of_property_read_u32_index(node,
  636. "syscon-pllreset", 1,
  637. &phy->dpll_reset_reg)) {
  638. dev_err(dev,
  639. "couldn't get pllreset reg. offset\n");
  640. return -EINVAL;
  641. }
  642. }
  643. }
  644. return 0;
  645. }
  646. static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
  647. {
  648. struct resource *res;
  649. struct device *dev = phy->dev;
  650. struct platform_device *pdev = to_platform_device(dev);
  651. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  652. "phy_rx");
  653. phy->phy_rx = devm_ioremap_resource(dev, res);
  654. if (IS_ERR(phy->phy_rx))
  655. return PTR_ERR(phy->phy_rx);
  656. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  657. "phy_tx");
  658. phy->phy_tx = devm_ioremap_resource(dev, res);
  659. return PTR_ERR_OR_ZERO(phy->phy_tx);
  660. }
  661. static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
  662. {
  663. struct resource *res;
  664. struct device *dev = phy->dev;
  665. struct platform_device *pdev = to_platform_device(dev);
  666. if (phy->mode == PIPE3_MODE_PCIE)
  667. return 0;
  668. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  669. "pll_ctrl");
  670. phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
  671. return PTR_ERR_OR_ZERO(phy->pll_ctrl_base);
  672. }
  673. static int ti_pipe3_probe(struct platform_device *pdev)
  674. {
  675. struct ti_pipe3 *phy;
  676. struct phy *generic_phy;
  677. struct phy_provider *phy_provider;
  678. struct device *dev = &pdev->dev;
  679. int ret;
  680. const struct of_device_id *match;
  681. struct pipe3_data *data;
  682. phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
  683. if (!phy)
  684. return -ENOMEM;
  685. match = of_match_device(ti_pipe3_id_table, dev);
  686. if (!match)
  687. return -EINVAL;
  688. data = (struct pipe3_data *)match->data;
  689. if (!data) {
  690. dev_err(dev, "no driver data\n");
  691. return -EINVAL;
  692. }
  693. phy->dev = dev;
  694. phy->mode = data->mode;
  695. phy->dpll_map = data->dpll_map;
  696. phy->settings = data->settings;
  697. ret = ti_pipe3_get_pll_base(phy);
  698. if (ret)
  699. return ret;
  700. ret = ti_pipe3_get_tx_rx_base(phy);
  701. if (ret)
  702. return ret;
  703. ret = ti_pipe3_get_sysctrl(phy);
  704. if (ret)
  705. return ret;
  706. ret = ti_pipe3_get_clk(phy);
  707. if (ret)
  708. return ret;
  709. platform_set_drvdata(pdev, phy);
  710. pm_runtime_enable(dev);
  711. /*
  712. * Prevent auto-disable of refclk for SATA PHY due to Errata i783
  713. */
  714. if (phy->mode == PIPE3_MODE_SATA) {
  715. if (!IS_ERR(phy->refclk)) {
  716. clk_prepare_enable(phy->refclk);
  717. phy->sata_refclk_enabled = true;
  718. }
  719. }
  720. generic_phy = devm_phy_create(dev, NULL, &ops);
  721. if (IS_ERR(generic_phy))
  722. return PTR_ERR(generic_phy);
  723. phy_set_drvdata(generic_phy, phy);
  724. ti_pipe3_power_off(generic_phy);
  725. phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  726. return PTR_ERR_OR_ZERO(phy_provider);
  727. }
  728. static int ti_pipe3_remove(struct platform_device *pdev)
  729. {
  730. struct ti_pipe3 *phy = platform_get_drvdata(pdev);
  731. if (phy->mode == PIPE3_MODE_SATA) {
  732. clk_disable_unprepare(phy->refclk);
  733. phy->sata_refclk_enabled = false;
  734. }
  735. pm_runtime_disable(&pdev->dev);
  736. return 0;
  737. }
  738. static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
  739. {
  740. int ret = 0;
  741. if (!IS_ERR(phy->refclk)) {
  742. ret = clk_prepare_enable(phy->refclk);
  743. if (ret) {
  744. dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
  745. return ret;
  746. }
  747. }
  748. if (!IS_ERR(phy->wkupclk)) {
  749. ret = clk_prepare_enable(phy->wkupclk);
  750. if (ret) {
  751. dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
  752. goto disable_refclk;
  753. }
  754. }
  755. if (!IS_ERR(phy->div_clk)) {
  756. ret = clk_prepare_enable(phy->div_clk);
  757. if (ret) {
  758. dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
  759. goto disable_wkupclk;
  760. }
  761. }
  762. return 0;
  763. disable_wkupclk:
  764. if (!IS_ERR(phy->wkupclk))
  765. clk_disable_unprepare(phy->wkupclk);
  766. disable_refclk:
  767. if (!IS_ERR(phy->refclk))
  768. clk_disable_unprepare(phy->refclk);
  769. return ret;
  770. }
  771. static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
  772. {
  773. if (!IS_ERR(phy->wkupclk))
  774. clk_disable_unprepare(phy->wkupclk);
  775. if (!IS_ERR(phy->refclk))
  776. clk_disable_unprepare(phy->refclk);
  777. if (!IS_ERR(phy->div_clk))
  778. clk_disable_unprepare(phy->div_clk);
  779. }
  780. static const struct of_device_id ti_pipe3_id_table[] = {
  781. {
  782. .compatible = "ti,phy-usb3",
  783. .data = &data_usb,
  784. },
  785. {
  786. .compatible = "ti,omap-usb3",
  787. .data = &data_usb,
  788. },
  789. {
  790. .compatible = "ti,phy-pipe3-sata",
  791. .data = &data_sata,
  792. },
  793. {
  794. .compatible = "ti,phy-pipe3-pcie",
  795. .data = &data_pcie,
  796. },
  797. {}
  798. };
  799. MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
  800. static struct platform_driver ti_pipe3_driver = {
  801. .probe = ti_pipe3_probe,
  802. .remove = ti_pipe3_remove,
  803. .driver = {
  804. .name = "ti-pipe3",
  805. .of_match_table = ti_pipe3_id_table,
  806. },
  807. };
  808. module_platform_driver(ti_pipe3_driver);
  809. MODULE_ALIAS("platform:ti_pipe3");
  810. MODULE_AUTHOR("Texas Instruments Inc.");
  811. MODULE_DESCRIPTION("TI PIPE3 phy driver");
  812. MODULE_LICENSE("GPL v2");